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ece92f85 JJ |
1 | /**************************************************************************** |
2 | * | |
3 | * BIOS emulator and interface | |
4 | * to Realmode X86 Emulator Library | |
5 | * | |
6 | * ======================================================================== | |
7 | * | |
4c2e3da8 | 8 | * Copyright (C) 2007 Freescale Semiconductor, Inc. |
ece92f85 JJ |
9 | * Jason Jin<[email protected]> |
10 | * | |
11 | * Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved. | |
12 | * | |
13 | * This file may be distributed and/or modified under the terms of the | |
14 | * GNU General Public License version 2.0 as published by the Free | |
15 | * Software Foundation and appearing in the file LICENSE.GPL included | |
16 | * in the packaging of this file. | |
17 | * | |
18 | * Licensees holding a valid Commercial License for this product from | |
19 | * SciTech Software, Inc. may use this file in accordance with the | |
20 | * Commercial License Agreement provided with the Software. | |
21 | * | |
22 | * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING | |
23 | * THE WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
24 | * PURPOSE. | |
25 | * | |
26 | * See http://www.scitechsoft.com/license/ for information about | |
27 | * the licensing options available and how to purchase a Commercial | |
28 | * License Agreement. | |
29 | * | |
30 | * Contact [email protected] if any conditions of this licensing | |
31 | * are not clear to you, or you have questions about licensing options. | |
32 | * | |
33 | * ======================================================================== | |
34 | * | |
35 | * Language: ANSI C | |
36 | * Environment: Any | |
37 | * Developer: Kendall Bennett | |
38 | * | |
39 | * Description: This file includes BIOS emulator I/O and memory access | |
40 | * functions. | |
41 | * | |
42 | * Jason ported this file to u-boot to run the ATI video card | |
43 | * BIOS in u-boot. Removed some emulate functions such as the | |
44 | * timer port access. Made all the VGA port except reading 0x3c3 | |
45 | * be emulated. Seems like reading 0x3c3 should return the high | |
46 | * 16 bit of the io port. | |
47 | * | |
48 | ****************************************************************************/ | |
49 | ||
b2da8038 | 50 | #define __io |
f46f3f35 | 51 | #include <asm/io.h> |
ece92f85 JJ |
52 | #include "biosemui.h" |
53 | ||
54 | /*------------------------- Global Variables ------------------------------*/ | |
55 | ||
ad6edca3 | 56 | #ifndef CONFIG_X86EMU_RAW_IO |
ece92f85 JJ |
57 | static char *BE_biosDate = "08/14/99"; |
58 | static u8 BE_model = 0xFC; | |
59 | static u8 BE_submodel = 0x00; | |
60 | #endif | |
61 | ||
b3521f2e SG |
62 | #undef DEBUG_IO_ACCESS |
63 | ||
64 | #ifdef DEBUG_IO_ACCESS | |
65 | #define debug_io(fmt, ...) printf(fmt, ##__VA_ARGS__) | |
66 | #else | |
67 | #define debug_io(x, b...) | |
68 | #endif | |
69 | ||
ece92f85 JJ |
70 | /*----------------------------- Implementation ----------------------------*/ |
71 | ||
72 | /**************************************************************************** | |
73 | PARAMETERS: | |
74 | addr - Emulator memory address to convert | |
75 | ||
76 | RETURNS: | |
77 | Actual memory address to read or write the data | |
78 | ||
79 | REMARKS: | |
80 | This function converts an emulator memory address in a 32-bit range to | |
81 | a real memory address that we wish to access. It handles splitting up the | |
82 | memory address space appropriately to access the emulator BIOS image, video | |
83 | memory and system BIOS etc. | |
84 | ****************************************************************************/ | |
85 | static u8 *BE_memaddr(u32 addr) | |
86 | { | |
87 | if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { | |
88 | return (u8*)(_BE_env.biosmem_base + addr - 0xC0000); | |
89 | } else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) { | |
ad6edca3 SG |
90 | DB(printf("BE_memaddr: address %#lx may be invalid!\n", |
91 | (ulong)addr);) | |
92 | return (u8 *)M.mem_base; | |
ece92f85 JJ |
93 | } else if (addr >= 0xA0000 && addr <= 0xBFFFF) { |
94 | return (u8*)(_BE_env.busmem_base + addr - 0xA0000); | |
95 | } | |
ad6edca3 | 96 | #ifdef CONFIG_X86EMU_RAW_IO |
ece92f85 JJ |
97 | else if (addr >= 0xD0000 && addr <= 0xFFFFF) { |
98 | /* We map the real System BIOS directly on real PC's */ | |
ad6edca3 SG |
99 | DB(printf("BE_memaddr: System BIOS address %#lx\n", |
100 | (ulong)addr);) | |
101 | return (u8 *)_BE_env.busmem_base + addr - 0xA0000; | |
ece92f85 JJ |
102 | } |
103 | #else | |
104 | else if (addr >= 0xFFFF5 && addr < 0xFFFFE) { | |
105 | /* Return a faked BIOS date string for non-x86 machines */ | |
b3521f2e | 106 | debug_io("BE_memaddr - Returning BIOS date\n"); |
409ecdc0 | 107 | return (u8 *)(BE_biosDate + addr - 0xFFFF5); |
ece92f85 JJ |
108 | } else if (addr == 0xFFFFE) { |
109 | /* Return system model identifier for non-x86 machines */ | |
b3521f2e | 110 | debug_io("BE_memaddr - Returning model\n"); |
ece92f85 JJ |
111 | return &BE_model; |
112 | } else if (addr == 0xFFFFF) { | |
113 | /* Return system submodel identifier for non-x86 machines */ | |
b3521f2e | 114 | debug_io("BE_memaddr - Returning submodel\n"); |
ece92f85 JJ |
115 | return &BE_submodel; |
116 | } | |
117 | #endif | |
118 | else if (addr > M.mem_size - 1) { | |
119 | HALT_SYS(); | |
ad6edca3 | 120 | return (u8 *)M.mem_base; |
ece92f85 JJ |
121 | } |
122 | ||
ad6edca3 | 123 | return (u8 *)(M.mem_base + addr); |
ece92f85 JJ |
124 | } |
125 | ||
126 | /**************************************************************************** | |
127 | PARAMETERS: | |
128 | addr - Emulator memory address to read | |
129 | ||
130 | RETURNS: | |
131 | Byte value read from emulator memory. | |
132 | ||
133 | REMARKS: | |
134 | Reads a byte value from the emulator memory. We have three distinct memory | |
135 | regions that are handled differently, which this function handles. | |
136 | ****************************************************************************/ | |
137 | u8 X86API BE_rdb(u32 addr) | |
138 | { | |
139 | if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF) | |
140 | return 0; | |
141 | else { | |
142 | u8 val = readb_le(BE_memaddr(addr)); | |
143 | return val; | |
144 | } | |
145 | } | |
146 | ||
147 | /**************************************************************************** | |
148 | PARAMETERS: | |
149 | addr - Emulator memory address to read | |
150 | ||
151 | RETURNS: | |
152 | Word value read from emulator memory. | |
153 | ||
154 | REMARKS: | |
155 | Reads a word value from the emulator memory. We have three distinct memory | |
156 | regions that are handled differently, which this function handles. | |
157 | ****************************************************************************/ | |
158 | u16 X86API BE_rdw(u32 addr) | |
159 | { | |
160 | if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF) | |
161 | return 0; | |
162 | else { | |
163 | u8 *base = BE_memaddr(addr); | |
164 | u16 val = readw_le(base); | |
165 | return val; | |
166 | } | |
167 | } | |
168 | ||
169 | /**************************************************************************** | |
170 | PARAMETERS: | |
171 | addr - Emulator memory address to read | |
172 | ||
173 | RETURNS: | |
174 | Long value read from emulator memory. | |
175 | ||
176 | REMARKS: | |
177 | Reads a 32-bit value from the emulator memory. We have three distinct memory | |
178 | regions that are handled differently, which this function handles. | |
179 | ****************************************************************************/ | |
180 | u32 X86API BE_rdl(u32 addr) | |
181 | { | |
182 | if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF) | |
183 | return 0; | |
184 | else { | |
185 | u8 *base = BE_memaddr(addr); | |
186 | u32 val = readl_le(base); | |
187 | return val; | |
188 | } | |
189 | } | |
190 | ||
191 | /**************************************************************************** | |
192 | PARAMETERS: | |
193 | addr - Emulator memory address to read | |
194 | val - Value to store | |
195 | ||
196 | REMARKS: | |
197 | Writes a byte value to emulator memory. We have three distinct memory | |
198 | regions that are handled differently, which this function handles. | |
199 | ****************************************************************************/ | |
200 | void X86API BE_wrb(u32 addr, u8 val) | |
201 | { | |
202 | if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) { | |
203 | writeb_le(BE_memaddr(addr), val); | |
204 | } | |
205 | } | |
206 | ||
207 | /**************************************************************************** | |
208 | PARAMETERS: | |
209 | addr - Emulator memory address to read | |
210 | val - Value to store | |
211 | ||
212 | REMARKS: | |
213 | Writes a word value to emulator memory. We have three distinct memory | |
214 | regions that are handled differently, which this function handles. | |
215 | ****************************************************************************/ | |
216 | void X86API BE_wrw(u32 addr, u16 val) | |
217 | { | |
218 | if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) { | |
219 | u8 *base = BE_memaddr(addr); | |
220 | writew_le(base, val); | |
221 | ||
222 | } | |
223 | } | |
224 | ||
225 | /**************************************************************************** | |
226 | PARAMETERS: | |
227 | addr - Emulator memory address to read | |
228 | val - Value to store | |
229 | ||
230 | REMARKS: | |
231 | Writes a 32-bit value to emulator memory. We have three distinct memory | |
232 | regions that are handled differently, which this function handles. | |
233 | ****************************************************************************/ | |
234 | void X86API BE_wrl(u32 addr, u32 val) | |
235 | { | |
236 | if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) { | |
237 | u8 *base = BE_memaddr(addr); | |
238 | writel_le(base, val); | |
239 | } | |
240 | } | |
241 | ||
ad6edca3 | 242 | #if !defined(CONFIG_X86EMU_RAW_IO) |
ece92f85 JJ |
243 | |
244 | /* For Non-Intel machines we may need to emulate some I/O port accesses that | |
245 | * the BIOS may try to access, such as the PCI config registers. | |
246 | */ | |
247 | ||
248 | #define IS_TIMER_PORT(port) (0x40 <= port && port <= 0x43) | |
249 | #define IS_CMOS_PORT(port) (0x70 <= port && port <= 0x71) | |
250 | /*#define IS_VGA_PORT(port) (_BE_env.emulateVGA && 0x3C0 <= port && port <= 0x3DA)*/ | |
251 | #define IS_VGA_PORT(port) (0x3C0 <= port && port <= 0x3DA) | |
252 | #define IS_PCI_PORT(port) (0xCF8 <= port && port <= 0xCFF) | |
253 | #define IS_SPKR_PORT(port) (port == 0x61) | |
254 | ||
255 | /**************************************************************************** | |
256 | PARAMETERS: | |
257 | port - Port to read from | |
258 | type - Type of access to perform | |
259 | ||
260 | REMARKS: | |
261 | Performs an emulated read from the Standard VGA I/O ports. If the target | |
262 | hardware does not support mapping the VGA I/O and memory (such as some | |
263 | PowerPC systems), we emulate the VGA so that the BIOS will still be able to | |
264 | set NonVGA display modes such as on ATI hardware. | |
265 | ****************************************************************************/ | |
9c7e4b06 | 266 | static u8 VGA_inpb (const int port) |
ece92f85 | 267 | { |
9c7e4b06 WD |
268 | u8 val = 0xff; |
269 | ||
b3521f2e | 270 | debug_io("vga_inb.%04X -> ", (u16) port); |
9c7e4b06 WD |
271 | switch (port) { |
272 | case 0x3C0: | |
273 | /* 3C0 has funky characteristics because it can act as either | |
274 | a data register or index register depending on the state | |
275 | of an internal flip flop in the hardware. Hence we have | |
276 | to emulate that functionality in here. */ | |
277 | if (_BE_env.flipFlop3C0 == 0) { | |
278 | /* Access 3C0 as index register */ | |
279 | val = _BE_env.emu3C0; | |
280 | } else { | |
281 | /* Access 3C0 as data register */ | |
282 | if (_BE_env.emu3C0 < ATT_C) | |
283 | val = _BE_env.emu3C1[_BE_env.emu3C0]; | |
284 | } | |
285 | _BE_env.flipFlop3C0 ^= 1; | |
286 | break; | |
287 | case 0x3C1: | |
288 | if (_BE_env.emu3C0 < ATT_C) | |
289 | return _BE_env.emu3C1[_BE_env.emu3C0]; | |
290 | break; | |
291 | case 0x3CC: | |
292 | return _BE_env.emu3C2; | |
293 | case 0x3C4: | |
294 | return _BE_env.emu3C4; | |
295 | case 0x3C5: | |
296 | if (_BE_env.emu3C4 < ATT_C) | |
297 | return _BE_env.emu3C5[_BE_env.emu3C4]; | |
298 | break; | |
299 | case 0x3C6: | |
300 | return _BE_env.emu3C6; | |
301 | case 0x3C7: | |
302 | return _BE_env.emu3C7; | |
303 | case 0x3C8: | |
304 | return _BE_env.emu3C8; | |
305 | case 0x3C9: | |
306 | if (_BE_env.emu3C7 < PAL_C) | |
307 | return _BE_env.emu3C9[_BE_env.emu3C7++]; | |
308 | break; | |
309 | case 0x3CE: | |
310 | return _BE_env.emu3CE; | |
311 | case 0x3CF: | |
312 | if (_BE_env.emu3CE < GRA_C) | |
313 | return _BE_env.emu3CF[_BE_env.emu3CE]; | |
314 | break; | |
315 | case 0x3D4: | |
316 | if (_BE_env.emu3C2 & 0x1) | |
317 | return _BE_env.emu3D4; | |
318 | break; | |
319 | case 0x3D5: | |
320 | if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) | |
321 | return _BE_env.emu3D5[_BE_env.emu3D4]; | |
322 | break; | |
323 | case 0x3DA: | |
324 | _BE_env.flipFlop3C0 = 0; | |
325 | val = _BE_env.emu3DA; | |
326 | _BE_env.emu3DA ^= 0x9; | |
327 | break; | |
328 | } | |
329 | return val; | |
ece92f85 JJ |
330 | } |
331 | ||
332 | /**************************************************************************** | |
333 | PARAMETERS: | |
334 | port - Port to write to | |
335 | type - Type of access to perform | |
336 | ||
337 | REMARKS: | |
338 | Performs an emulated write to one of the 8253 timer registers. For now | |
339 | we only emulate timer 0 which is the only timer that the BIOS code appears | |
340 | to use. | |
341 | ****************************************************************************/ | |
9c7e4b06 | 342 | static void VGA_outpb (int port, u8 val) |
ece92f85 | 343 | { |
9c7e4b06 WD |
344 | switch (port) { |
345 | case 0x3C0: | |
346 | /* 3C0 has funky characteristics because it can act as either | |
347 | a data register or index register depending on the state | |
348 | of an internal flip flop in the hardware. Hence we have | |
349 | to emulate that functionality in here. */ | |
350 | if (_BE_env.flipFlop3C0 == 0) { | |
351 | /* Access 3C0 as index register */ | |
352 | _BE_env.emu3C0 = val; | |
353 | } else { | |
354 | /* Access 3C0 as data register */ | |
355 | if (_BE_env.emu3C0 < ATT_C) | |
356 | _BE_env.emu3C1[_BE_env.emu3C0] = val; | |
357 | } | |
358 | _BE_env.flipFlop3C0 ^= 1; | |
359 | break; | |
360 | case 0x3C2: | |
361 | _BE_env.emu3C2 = val; | |
362 | break; | |
363 | case 0x3C4: | |
364 | _BE_env.emu3C4 = val; | |
365 | break; | |
366 | case 0x3C5: | |
367 | if (_BE_env.emu3C4 < ATT_C) | |
368 | _BE_env.emu3C5[_BE_env.emu3C4] = val; | |
369 | break; | |
370 | case 0x3C6: | |
371 | _BE_env.emu3C6 = val; | |
372 | break; | |
373 | case 0x3C7: | |
374 | _BE_env.emu3C7 = (int) val *3; | |
375 | ||
376 | break; | |
377 | case 0x3C8: | |
378 | _BE_env.emu3C8 = (int) val *3; | |
379 | ||
380 | break; | |
381 | case 0x3C9: | |
382 | if (_BE_env.emu3C8 < PAL_C) | |
383 | _BE_env.emu3C9[_BE_env.emu3C8++] = val; | |
384 | break; | |
385 | case 0x3CE: | |
386 | _BE_env.emu3CE = val; | |
387 | break; | |
388 | case 0x3CF: | |
389 | if (_BE_env.emu3CE < GRA_C) | |
390 | _BE_env.emu3CF[_BE_env.emu3CE] = val; | |
391 | break; | |
392 | case 0x3D4: | |
393 | if (_BE_env.emu3C2 & 0x1) | |
394 | _BE_env.emu3D4 = val; | |
395 | break; | |
396 | case 0x3D5: | |
397 | if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) | |
398 | _BE_env.emu3D5[_BE_env.emu3D4] = val; | |
399 | break; | |
400 | } | |
ece92f85 JJ |
401 | } |
402 | ||
403 | /**************************************************************************** | |
404 | PARAMETERS: | |
405 | regOffset - Offset into register space for non-DWORD accesses | |
406 | value - Value to write to register for PCI_WRITE_* operations | |
407 | func - Function to perform (PCIAccessRegFlags) | |
408 | ||
409 | RETURNS: | |
410 | Value read from configuration register for PCI_READ_* operations | |
411 | ||
412 | REMARKS: | |
413 | Accesses a PCI configuration space register by decoding the value currently | |
414 | stored in the _BE_env.configAddress variable and passing it through to the | |
415 | portable PCI_accessReg function. | |
416 | ****************************************************************************/ | |
417 | static u32 BE_accessReg(int regOffset, u32 value, int func) | |
418 | { | |
419 | #ifdef __KERNEL__ | |
420 | int function, device, bus; | |
421 | u8 val8; | |
422 | u16 val16; | |
423 | u32 val32; | |
424 | ||
425 | ||
426 | /* Decode the configuration register values for the register we wish to | |
427 | * access | |
428 | */ | |
429 | regOffset += (_BE_env.configAddress & 0xFF); | |
430 | function = (_BE_env.configAddress >> 8) & 0x7; | |
431 | device = (_BE_env.configAddress >> 11) & 0x1F; | |
432 | bus = (_BE_env.configAddress >> 16) & 0xFF; | |
433 | ||
434 | /* Ignore accesses to all devices other than the one we're POSTing */ | |
435 | if ((function == _BE_env.vgaInfo.function) && | |
436 | (device == _BE_env.vgaInfo.device) && | |
437 | (bus == _BE_env.vgaInfo.bus)) { | |
438 | switch (func) { | |
439 | case REG_READ_BYTE: | |
440 | pci_read_config_byte(_BE_env.vgaInfo.pcidev, regOffset, | |
441 | &val8); | |
442 | return val8; | |
443 | case REG_READ_WORD: | |
444 | pci_read_config_word(_BE_env.vgaInfo.pcidev, regOffset, | |
445 | &val16); | |
446 | return val16; | |
447 | case REG_READ_DWORD: | |
448 | pci_read_config_dword(_BE_env.vgaInfo.pcidev, regOffset, | |
449 | &val32); | |
450 | return val32; | |
451 | case REG_WRITE_BYTE: | |
452 | pci_write_config_byte(_BE_env.vgaInfo.pcidev, regOffset, | |
453 | value); | |
454 | ||
455 | return 0; | |
456 | case REG_WRITE_WORD: | |
457 | pci_write_config_word(_BE_env.vgaInfo.pcidev, regOffset, | |
458 | value); | |
459 | ||
460 | return 0; | |
461 | case REG_WRITE_DWORD: | |
462 | pci_write_config_dword(_BE_env.vgaInfo.pcidev, | |
463 | regOffset, value); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | } | |
468 | return 0; | |
469 | #else | |
470 | PCIDeviceInfo pciInfo; | |
471 | ||
472 | pciInfo.mech1 = 1; | |
473 | pciInfo.slot.i = 0; | |
474 | pciInfo.slot.p.Function = (_BE_env.configAddress >> 8) & 0x7; | |
475 | pciInfo.slot.p.Device = (_BE_env.configAddress >> 11) & 0x1F; | |
476 | pciInfo.slot.p.Bus = (_BE_env.configAddress >> 16) & 0xFF; | |
477 | pciInfo.slot.p.Enable = 1; | |
478 | ||
479 | /* Ignore accesses to all devices other than the one we're POSTing */ | |
480 | if ((pciInfo.slot.p.Function == | |
481 | _BE_env.vgaInfo.pciInfo->slot.p.Function) | |
482 | && (pciInfo.slot.p.Device == _BE_env.vgaInfo.pciInfo->slot.p.Device) | |
483 | && (pciInfo.slot.p.Bus == _BE_env.vgaInfo.pciInfo->slot.p.Bus)) | |
484 | return PCI_accessReg((_BE_env.configAddress & 0xFF) + regOffset, | |
485 | value, func, &pciInfo); | |
486 | return 0; | |
487 | #endif | |
488 | } | |
489 | ||
490 | /**************************************************************************** | |
491 | PARAMETERS: | |
492 | port - Port to read from | |
493 | type - Type of access to perform | |
494 | ||
495 | REMARKS: | |
496 | Performs an emulated read from one of the PCI configuration space registers. | |
497 | We emulate this using our PCI_accessReg function which will access the PCI | |
498 | configuration space registers in a portable fashion. | |
499 | ****************************************************************************/ | |
500 | static u32 PCI_inp(int port, int type) | |
501 | { | |
502 | switch (type) { | |
503 | case REG_READ_BYTE: | |
504 | if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port | |
505 | && port <= 0xCFF) | |
506 | return BE_accessReg(port - 0xCFC, 0, REG_READ_BYTE); | |
507 | break; | |
508 | case REG_READ_WORD: | |
509 | if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port | |
510 | && port <= 0xCFF) | |
511 | return BE_accessReg(port - 0xCFC, 0, REG_READ_WORD); | |
512 | break; | |
513 | case REG_READ_DWORD: | |
514 | if (port == 0xCF8) | |
515 | return _BE_env.configAddress; | |
516 | else if ((_BE_env.configAddress & 0x80000000) && port == 0xCFC) | |
517 | return BE_accessReg(0, 0, REG_READ_DWORD); | |
518 | break; | |
519 | } | |
520 | return 0; | |
521 | } | |
522 | ||
523 | /**************************************************************************** | |
524 | PARAMETERS: | |
525 | port - Port to write to | |
526 | type - Type of access to perform | |
527 | ||
528 | REMARKS: | |
529 | Performs an emulated write to one of the PCI control registers. | |
530 | ****************************************************************************/ | |
531 | static void PCI_outp(int port, u32 val, int type) | |
532 | { | |
533 | switch (type) { | |
534 | case REG_WRITE_BYTE: | |
535 | if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port | |
536 | && port <= 0xCFF) | |
537 | BE_accessReg(port - 0xCFC, val, REG_WRITE_BYTE); | |
538 | break; | |
539 | case REG_WRITE_WORD: | |
540 | if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port | |
541 | && port <= 0xCFF) | |
542 | BE_accessReg(port - 0xCFC, val, REG_WRITE_WORD); | |
543 | break; | |
544 | case REG_WRITE_DWORD: | |
545 | if (port == 0xCF8) | |
546 | { | |
547 | _BE_env.configAddress = val & 0x80FFFFFC; | |
548 | } | |
549 | else if ((_BE_env.configAddress & 0x80000000) && port == 0xCFC) | |
550 | BE_accessReg(0, val, REG_WRITE_DWORD); | |
551 | break; | |
552 | } | |
553 | } | |
554 | ||
555 | #endif | |
556 | ||
557 | /**************************************************************************** | |
558 | PARAMETERS: | |
559 | port - Port to write to | |
560 | ||
561 | RETURNS: | |
562 | Value read from the I/O port | |
563 | ||
564 | REMARKS: | |
565 | Performs an emulated 8-bit read from an I/O port. We handle special cases | |
566 | that we need to emulate in here, and fall through to reflecting the write | |
567 | through to the real hardware if we don't need to special case it. | |
568 | ****************************************************************************/ | |
569 | u8 X86API BE_inb(X86EMU_pioAddr port) | |
570 | { | |
571 | u8 val = 0; | |
572 | ||
ad6edca3 | 573 | #if !defined(CONFIG_X86EMU_RAW_IO) |
ece92f85 JJ |
574 | if (IS_VGA_PORT(port)){ |
575 | /*seems reading port 0x3c3 return the high 16 bit of io port*/ | |
576 | if(port == 0x3c3) | |
577 | val = LOG_inpb(port); | |
578 | else | |
579 | val = VGA_inpb(port); | |
580 | } | |
581 | else if (IS_TIMER_PORT(port)) | |
582 | DB(printf("Can not interept TIMER port now!\n");) | |
583 | else if (IS_SPKR_PORT(port)) | |
584 | DB(printf("Can not interept SPEAKER port now!\n");) | |
585 | else if (IS_CMOS_PORT(port)) | |
586 | DB(printf("Can not interept CMOS port now!\n");) | |
587 | else if (IS_PCI_PORT(port)) | |
588 | val = PCI_inp(port, REG_READ_BYTE); | |
589 | else if (port < 0x100) { | |
590 | DB(printf("WARN: INVALID inb.%04X -> %02X\n", (u16) port, val);) | |
591 | val = LOG_inpb(port); | |
592 | } else | |
593 | #endif | |
b3521f2e SG |
594 | { |
595 | debug_io("inb.%04X -> ", (u16) port); | |
ece92f85 | 596 | val = LOG_inpb(port); |
b3521f2e SG |
597 | debug_io("%02X\n", val); |
598 | } | |
599 | ||
ece92f85 JJ |
600 | return val; |
601 | } | |
602 | ||
603 | /**************************************************************************** | |
604 | PARAMETERS: | |
605 | port - Port to write to | |
606 | ||
607 | RETURNS: | |
608 | Value read from the I/O port | |
609 | ||
610 | REMARKS: | |
611 | Performs an emulated 16-bit read from an I/O port. We handle special cases | |
612 | that we need to emulate in here, and fall through to reflecting the write | |
613 | through to the real hardware if we don't need to special case it. | |
614 | ****************************************************************************/ | |
615 | u16 X86API BE_inw(X86EMU_pioAddr port) | |
616 | { | |
617 | u16 val = 0; | |
618 | ||
ad6edca3 | 619 | #if !defined(CONFIG_X86EMU_RAW_IO) |
ece92f85 JJ |
620 | if (IS_PCI_PORT(port)) |
621 | val = PCI_inp(port, REG_READ_WORD); | |
622 | else if (port < 0x100) { | |
623 | DB(printf("WARN: Maybe INVALID inw.%04X -> %04X\n", (u16) port, val);) | |
624 | val = LOG_inpw(port); | |
625 | } else | |
626 | #endif | |
b3521f2e SG |
627 | { |
628 | debug_io("inw.%04X -> ", (u16) port); | |
ece92f85 | 629 | val = LOG_inpw(port); |
b3521f2e SG |
630 | debug_io("%04X\n", val); |
631 | } | |
632 | ||
ece92f85 JJ |
633 | return val; |
634 | } | |
635 | ||
636 | /**************************************************************************** | |
637 | PARAMETERS: | |
638 | port - Port to write to | |
639 | ||
640 | RETURNS: | |
641 | Value read from the I/O port | |
642 | ||
643 | REMARKS: | |
644 | Performs an emulated 32-bit read from an I/O port. We handle special cases | |
645 | that we need to emulate in here, and fall through to reflecting the write | |
646 | through to the real hardware if we don't need to special case it. | |
647 | ****************************************************************************/ | |
648 | u32 X86API BE_inl(X86EMU_pioAddr port) | |
649 | { | |
650 | u32 val = 0; | |
651 | ||
ad6edca3 | 652 | #if !defined(CONFIG_X86EMU_RAW_IO) |
ece92f85 JJ |
653 | if (IS_PCI_PORT(port)) |
654 | val = PCI_inp(port, REG_READ_DWORD); | |
655 | else if (port < 0x100) { | |
656 | val = LOG_inpd(port); | |
657 | } else | |
658 | #endif | |
b3521f2e SG |
659 | { |
660 | debug_io("inl.%04X -> ", (u16) port); | |
ece92f85 | 661 | val = LOG_inpd(port); |
b3521f2e SG |
662 | debug_io("%08X\n", val); |
663 | } | |
664 | ||
ece92f85 JJ |
665 | return val; |
666 | } | |
667 | ||
668 | /**************************************************************************** | |
669 | PARAMETERS: | |
670 | port - Port to write to | |
671 | val - Value to write to port | |
672 | ||
673 | REMARKS: | |
674 | Performs an emulated 8-bit write to an I/O port. We handle special cases | |
675 | that we need to emulate in here, and fall through to reflecting the write | |
676 | through to the real hardware if we don't need to special case it. | |
677 | ****************************************************************************/ | |
678 | void X86API BE_outb(X86EMU_pioAddr port, u8 val) | |
679 | { | |
ad6edca3 | 680 | #if !defined(CONFIG_X86EMU_RAW_IO) |
ece92f85 JJ |
681 | if (IS_VGA_PORT(port)) |
682 | VGA_outpb(port, val); | |
683 | else if (IS_TIMER_PORT(port)) | |
684 | DB(printf("Can not interept TIMER port now!\n");) | |
685 | else if (IS_SPKR_PORT(port)) | |
686 | DB(printf("Can not interept SPEAKER port now!\n");) | |
687 | else if (IS_CMOS_PORT(port)) | |
688 | DB(printf("Can not interept CMOS port now!\n");) | |
689 | else if (IS_PCI_PORT(port)) | |
690 | PCI_outp(port, val, REG_WRITE_BYTE); | |
691 | else if (port < 0x100) { | |
692 | DB(printf("WARN:Maybe INVALID outb.%04X <- %02X\n", (u16) port, val);) | |
693 | LOG_outpb(port, val); | |
694 | } else | |
695 | #endif | |
b3521f2e SG |
696 | { |
697 | debug_io("outb.%04X <- %02X", (u16) port, val); | |
ece92f85 | 698 | LOG_outpb(port, val); |
b3521f2e SG |
699 | debug_io("\n"); |
700 | } | |
ece92f85 JJ |
701 | } |
702 | ||
703 | /**************************************************************************** | |
704 | PARAMETERS: | |
705 | port - Port to write to | |
706 | val - Value to write to port | |
707 | ||
708 | REMARKS: | |
709 | Performs an emulated 16-bit write to an I/O port. We handle special cases | |
710 | that we need to emulate in here, and fall through to reflecting the write | |
711 | through to the real hardware if we don't need to special case it. | |
712 | ****************************************************************************/ | |
713 | void X86API BE_outw(X86EMU_pioAddr port, u16 val) | |
714 | { | |
ad6edca3 | 715 | #if !defined(CONFIG_X86EMU_RAW_IO) |
b3521f2e SG |
716 | if (IS_VGA_PORT(port)) { |
717 | VGA_outpb(port, val); | |
718 | VGA_outpb(port + 1, val >> 8); | |
719 | } else if (IS_PCI_PORT(port)) { | |
720 | PCI_outp(port, val, REG_WRITE_WORD); | |
721 | } else if (port < 0x100) { | |
722 | DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16)port, | |
723 | val);) | |
724 | LOG_outpw(port, val); | |
725 | } else | |
ece92f85 | 726 | #endif |
b3521f2e SG |
727 | { |
728 | debug_io("outw.%04X <- %04X", (u16) port, val); | |
729 | LOG_outpw(port, val); | |
730 | debug_io("\n"); | |
731 | } | |
ece92f85 JJ |
732 | } |
733 | ||
734 | /**************************************************************************** | |
735 | PARAMETERS: | |
736 | port - Port to write to | |
737 | val - Value to write to port | |
738 | ||
739 | REMARKS: | |
740 | Performs an emulated 32-bit write to an I/O port. We handle special cases | |
741 | that we need to emulate in here, and fall through to reflecting the write | |
742 | through to the real hardware if we don't need to special case it. | |
743 | ****************************************************************************/ | |
744 | void X86API BE_outl(X86EMU_pioAddr port, u32 val) | |
745 | { | |
ad6edca3 | 746 | #if !defined(CONFIG_X86EMU_RAW_IO) |
4c59f953 | 747 | if (IS_PCI_PORT(port)) { |
ece92f85 | 748 | PCI_outp(port, val, REG_WRITE_DWORD); |
4c59f953 | 749 | } else if (port < 0x100) { |
ece92f85 JJ |
750 | DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);) |
751 | LOG_outpd(port, val); | |
752 | } else | |
753 | #endif | |
b3521f2e SG |
754 | { |
755 | debug_io("outl.%04X <- %08X", (u16) port, val); | |
ece92f85 | 756 | LOG_outpd(port, val); |
b3521f2e SG |
757 | debug_io("\n"); |
758 | } | |
ece92f85 | 759 | } |