[J-u-boot.git] / include / power / stpmic1.h

/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#ifndef __PMIC_STPMIC1_H_
#define __PMIC_STPMIC1_H_

#define STPMIC1_MAIN_CR			0x10
#define STPMIC1_BUCKS_MRST_CR		0x18
#define STPMIC1_LDOS_MRST_CR		0x1a
#define STPMIC1_BUCKX_MAIN_CR(buck)	(0x20 + (buck))
#define STPMIC1_REFDDR_MAIN_CR		0x24
#define STPMIC1_LDOX_MAIN_CR(ldo)	(0x25 + (ldo))
#define STPMIC1_BST_SW_CR		0x40
#define STPMIC1_NVM_SR			0xb8
#define STPMIC1_NVM_CR			0xb9

/* Main PMIC Control Register (MAIN_CR) */
#define STPMIC1_SWOFF			BIT(0)
#define STPMIC1_RREQ_EN			BIT(1)

/* BUCKS_MRST_CR */
#define STPMIC1_MRST_BUCK(buck)		BIT(buck)
#define STPMIC1_MRST_BUCK_DEBUG		(STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
					 STPMIC1_MRST_BUCK(STPMIC1_BUCK3))

/* LDOS_MRST_CR */
#define STPMIC1_MRST_LDO(ldo)		BIT(ldo)
#define STPMIC1_MRST_LDO_DEBUG		0

/* BUCKx_MAIN_CR (x=1...4) */
#define STPMIC1_BUCK_ENA		BIT(0)
#define STPMIC1_BUCK_PREG_MODE		BIT(1)
#define STPMIC1_BUCK_VOUT_MASK		GENMASK(7, 2)
#define STPMIC1_BUCK_VOUT_SHIFT		2
#define STPMIC1_BUCK_VOUT(sel)		(sel << STPMIC1_BUCK_VOUT_SHIFT)

#define STPMIC1_BUCK2_1200000V		STPMIC1_BUCK_VOUT(24)
#define STPMIC1_BUCK2_1250000V		STPMIC1_BUCK_VOUT(26)
#define STPMIC1_BUCK2_1350000V		STPMIC1_BUCK_VOUT(30)

#define STPMIC1_BUCK3_1800000V		STPMIC1_BUCK_VOUT(39)

/* REFDDR_MAIN_CR */
#define STPMIC1_VREF_ENA		BIT(0)

/* LDOX_MAIN_CR */
#define STPMIC1_LDO_ENA			BIT(0)
#define STPMIC1_LDO12356_VOUT_MASK	GENMASK(6, 2)
#define STPMIC1_LDO12356_VOUT_SHIFT	2
#define STPMIC1_LDO_VOUT(sel)		(sel << STPMIC1_LDO12356_VOUT_SHIFT)

#define STPMIC1_LDO3_MODE		BIT(7)
#define STPMIC1_LDO3_DDR_SEL		31
#define STPMIC1_LDO3_1800000		STPMIC1_LDO_VOUT(9)

#define STPMIC1_LDO4_UV			3300000

/* BST_SW_CR */
#define STPMIC1_BST_ON			BIT(0)
#define STPMIC1_VBUSOTG_ON		BIT(1)
#define STPMIC1_SWOUT_ON		BIT(2)
#define STPMIC1_PWR_SW_ON		(STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)

/* NVM_SR */
#define STPMIC1_NVM_BUSY		BIT(0)

/* NVM_CR */
#define STPMIC1_NVM_CMD_PROGRAM		1
#define STPMIC1_NVM_CMD_READ		2

/* Timeout */
#define STPMIC1_DEFAULT_START_UP_DELAY_MS	1
#define STPMIC1_DEFAULT_STOP_DELAY_MS		5
#define STPMIC1_USB_BOOST_START_UP_DELAY_MS	10

enum {
	STPMIC1_BUCK1,
	STPMIC1_BUCK2,
	STPMIC1_BUCK3,
	STPMIC1_BUCK4,
	STPMIC1_MAX_BUCK,
};

enum {
	STPMIC1_PREG_MODE_HP,
	STPMIC1_PREG_MODE_LP,
};

enum {
	STPMIC1_LDO1,
	STPMIC1_LDO2,
	STPMIC1_LDO3,
	STPMIC1_LDO4,
	STPMIC1_LDO5,
	STPMIC1_LDO6,
	STPMIC1_MAX_LDO,
};

enum {
	STPMIC1_LDO_MODE_NORMAL,
	STPMIC1_LDO_MODE_BYPASS,
	STPMIC1_LDO_MODE_SINK_SOURCE,
};

enum {
	STPMIC1_PWR_SW1,
	STPMIC1_PWR_SW2,
	STPMIC1_MAX_PWR_SW,
};
#endif
Commit	Line	Data
4549e789	1	/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
5d0c74e6 PD	2	/*
5d0c74e6 PD	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
5d0c74e6 PD	4	*/
5d0c74e6 PD	5
42f01aac PD	6	#ifndef __PMIC_STPMIC1_H_
	7	#define __PMIC_STPMIC1_H_
	8
db4ff0df PD	9	#define STPMIC1_MAIN_CR 0x10
	10	#define STPMIC1_BUCKS_MRST_CR 0x18
	11	#define STPMIC1_LDOS_MRST_CR 0x1a
	12	#define STPMIC1_BUCKX_MAIN_CR(buck) (0x20 + (buck))
	13	#define STPMIC1_REFDDR_MAIN_CR 0x24
	14	#define STPMIC1_LDOX_MAIN_CR(ldo) (0x25 + (ldo))
	15	#define STPMIC1_BST_SW_CR 0x40
	16	#define STPMIC1_NVM_SR 0xb8
	17	#define STPMIC1_NVM_CR 0xb9
	18
	19	/* Main PMIC Control Register (MAIN_CR) */
	20	#define STPMIC1_SWOFF BIT(0)
	21	#define STPMIC1_RREQ_EN BIT(1)
	22
	23	/* BUCKS_MRST_CR */
	24	#define STPMIC1_MRST_BUCK(buck) BIT(buck)
178a4155 PD	25	#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) \| \
178a4155 PD	26	STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
db4ff0df PD	27
	28	/* LDOS_MRST_CR */
	29	#define STPMIC1_MRST_LDO(ldo) BIT(ldo)
178a4155	30	#define STPMIC1_MRST_LDO_DEBUG 0
db4ff0df PD	31
	32	/* BUCKx_MAIN_CR (x=1...4) */
	33	#define STPMIC1_BUCK_ENA BIT(0)
	34	#define STPMIC1_BUCK_PREG_MODE BIT(1)
	35	#define STPMIC1_BUCK_VOUT_MASK GENMASK(7, 2)
	36	#define STPMIC1_BUCK_VOUT_SHIFT 2
	37	#define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT)
	38
	39	#define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24)
e9a20f8a	40	#define STPMIC1_BUCK2_1250000V STPMIC1_BUCK_VOUT(26)
db4ff0df PD	41	#define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30)
	42
	43	#define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39)
	44
	45	/* REFDDR_MAIN_CR */
	46	#define STPMIC1_VREF_ENA BIT(0)
	47
	48	/* LDOX_MAIN_CR */
	49	#define STPMIC1_LDO_ENA BIT(0)
	50	#define STPMIC1_LDO12356_VOUT_MASK GENMASK(6, 2)
	51	#define STPMIC1_LDO12356_VOUT_SHIFT 2
	52	#define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT)
	53
42f01aac PD	54	#define STPMIC1_LDO3_MODE BIT(7)
42f01aac PD	55	#define STPMIC1_LDO3_DDR_SEL 31
db4ff0df PD	56	#define STPMIC1_LDO3_1800000 STPMIC1_LDO_VOUT(9)
db4ff0df PD	57
42f01aac PD	58	#define STPMIC1_LDO4_UV 3300000
42f01aac PD	59
db4ff0df PD	60	/* BST_SW_CR */
	61	#define STPMIC1_BST_ON BIT(0)
	62	#define STPMIC1_VBUSOTG_ON BIT(1)
	63	#define STPMIC1_SWOUT_ON BIT(2)
	64	#define STPMIC1_PWR_SW_ON (STPMIC1_VBUSOTG_ON \| STPMIC1_SWOUT_ON)
42f01aac	65
db4ff0df PD	66	/* NVM_SR */
db4ff0df PD	67	#define STPMIC1_NVM_BUSY BIT(0)
42f01aac	68
db4ff0df PD	69	/* NVM_CR */
	70	#define STPMIC1_NVM_CMD_PROGRAM 1
	71	#define STPMIC1_NVM_CMD_READ 2
42f01aac	72
db4ff0df	73	/* Timeout */
42f01aac PD	74	#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1
	75	#define STPMIC1_DEFAULT_STOP_DELAY_MS 5
	76	#define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10
5d0c74e6 PD	77
5d0c74e6 PD	78	enum {
42f01aac PD	79	STPMIC1_BUCK1,
	80	STPMIC1_BUCK2,
	81	STPMIC1_BUCK3,
	82	STPMIC1_BUCK4,
	83	STPMIC1_MAX_BUCK,
5d0c74e6 PD	84	};
	85
	86	enum {
db4ff0df PD	87	STPMIC1_PREG_MODE_HP,
db4ff0df PD	88	STPMIC1_PREG_MODE_LP,
5d0c74e6 PD	89	};
	90
	91	enum {
42f01aac PD	92	STPMIC1_LDO1,
	93	STPMIC1_LDO2,
	94	STPMIC1_LDO3,
	95	STPMIC1_LDO4,
	96	STPMIC1_LDO5,
	97	STPMIC1_LDO6,
	98	STPMIC1_MAX_LDO,
5d0c74e6 PD	99	};
	100
	101	enum {
42f01aac PD	102	STPMIC1_LDO_MODE_NORMAL,
	103	STPMIC1_LDO_MODE_BYPASS,
	104	STPMIC1_LDO_MODE_SINK_SOURCE,
5d0c74e6 PD	105	};
	106
	107	enum {
42f01aac PD	108	STPMIC1_PWR_SW1,
	109	STPMIC1_PWR_SW2,
	110	STPMIC1_MAX_PWR_SW,
5d0c74e6	111	};
5d0c74e6	112	#endif