[J-u-boot.git] / drivers / ram / stm32mp1 / stm32mp1_ram.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <init.h>
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include "stm32mp1_ddr.h"

static const char *const clkname[] = {
	"ddrc1",
	"ddrc2",
	"ddrcapb",
	"ddrphycapb",
	"ddrphyc" /* LAST clock => used for get_rate() */
};

int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
{
	unsigned long ddrphy_clk;
	unsigned long ddr_clk;
	struct clk clk;
	int ret;
	unsigned int idx;

	for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
		ret = clk_get_by_name(priv->dev, clkname[idx], &clk);

		if (!ret)
			ret = clk_enable(&clk);

		if (ret) {
			printf("error for %s : %d\n", clkname[idx], ret);
			return ret;
		}
	}

	priv->clk = clk;
	ddrphy_clk = clk_get_rate(&priv->clk);

	debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
	      mem_speed, (u32)(ddrphy_clk / 1000));
	/* max 10% frequency delta */
	ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
	if (ddr_clk > (mem_speed * 100)) {
		pr_err("DDR expected freq %d kHz, current is %d kHz\n",
		       mem_speed, (u32)(ddrphy_clk / 1000));
		return -EINVAL;
	}

	return 0;
}

static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
{
	struct ddr_info *priv = dev_get_priv(dev);
	int ret;
	unsigned int idx;
	struct clk axidcg;
	struct stm32mp1_ddr_config config;

#define PARAM(x, y, z)							\
	{	.name = x,						\
		.offset = offsetof(struct stm32mp1_ddr_config, y),	\
		.size = sizeof(config.y) / sizeof(u32),			\
		.present = z,						\
	}

#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)

	const struct {
		const char *name; /* name in DT */
		const u32 offset; /* offset in config struct */
		const u32 size;   /* size of parameters */
		bool * const present;  /* presence indication for opt */
	} param[] = {
		CTL_PARAM(reg),
		CTL_PARAM(timing),
		CTL_PARAM(map),
		CTL_PARAM(perf),
		PHY_PARAM(reg),
		PHY_PARAM(timing),
		PHY_PARAM_OPT(cal)
	};

	config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
	config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
	config.info.name = dev_read_string(dev, "st,mem-name");
	if (!config.info.name) {
		debug("%s: no st,mem-name\n", __func__);
		return -EINVAL;
	}
	printf("RAM: %s\n", config.info.name);

	for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
		ret = dev_read_u32_array(dev, param[idx].name,
					 (void *)((u32)&config +
						  param[idx].offset),
					 param[idx].size);
		debug("%s: %s[0x%x] = %d\n", __func__,
		      param[idx].name, param[idx].size, ret);
		if (ret &&
		    (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
			pr_err("%s: Cannot read %s, error=%d\n",
			       __func__, param[idx].name, ret);
			return -EINVAL;
		}
		if (param[idx].present) {
			/* save presence of optional parameters */
			*param[idx].present = true;
			if (ret == -FDT_ERR_NOTFOUND) {
				*param[idx].present = false;
#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
				/* reset values if used later */
				memset((void *)((u32)&config +
						param[idx].offset),
					0, param[idx].size * sizeof(u32));
#endif
			}
		}
	}

	ret = clk_get_by_name(dev, "axidcg", &axidcg);
	if (ret) {
		debug("%s: Cannot found axidcg\n", __func__);
		return -EINVAL;
	}
	clk_disable(&axidcg); /* disable clock gating during init */

	stm32mp1_ddr_init(priv, &config);

	clk_enable(&axidcg); /* enable clock gating */

	/* check size */
	debug("%s : get_ram_size(%x, %x)\n", __func__,
	      (u32)priv->info.base, (u32)STM32_DDR_SIZE);

	priv->info.size = get_ram_size((long *)priv->info.base,
				       STM32_DDR_SIZE);

	debug("%s : %x\n", __func__, (u32)priv->info.size);

	/* check memory access for all memory */
	if (config.info.size != priv->info.size) {
		printf("DDR invalid size : 0x%x, expected 0x%x\n",
		       priv->info.size, config.info.size);
		return -EINVAL;
	}
	return 0;
}

static int stm32mp1_ddr_probe(struct udevice *dev)
{
	struct ddr_info *priv = dev_get_priv(dev);
	struct regmap *map;
	int ret;

	debug("STM32MP1 DDR probe\n");
	priv->dev = dev;

	ret = regmap_init_mem(dev_ofnode(dev), &map);
	if (ret)
		return ret;

	priv->ctl = regmap_get_range(map, 0);
	priv->phy = regmap_get_range(map, 1);

	priv->rcc = STM32_RCC_BASE;

	priv->info.base = STM32_DDR_BASE;

#if !defined(CONFIG_STM32MP1_TRUSTED) && \
	(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
	priv->info.size = 0;
	return stm32mp1_ddr_setup(dev);
#else
	priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
	return 0;
#endif
}

static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
{
	struct ddr_info *priv = dev_get_priv(dev);

	*info = priv->info;

	return 0;
}

static struct ram_ops stm32mp1_ddr_ops = {
	.get_info = stm32mp1_ddr_get_info,
};

static const struct udevice_id stm32mp1_ddr_ids[] = {
	{ .compatible = "st,stm32mp1-ddr" },
	{ }
};

U_BOOT_DRIVER(ddr_stm32mp1) = {
	.name = "stm32mp1_ddr",
	.id = UCLASS_RAM,
	.of_match = stm32mp1_ddr_ids,
	.ops = &stm32mp1_ddr_ops,
	.probe = stm32mp1_ddr_probe,
	.priv_auto_alloc_size = sizeof(struct ddr_info),
};
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
e70f70aa PD	2	/*
e70f70aa PD	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
e70f70aa PD	4	*/
	5
	6	#include <common.h>
	7	#include <clk.h>
	8	#include <dm.h>
9b4a205f	9	#include <init.h>
e70f70aa PD	10	#include <ram.h>
	11	#include <regmap.h>
	12	#include <syscon.h>
	13	#include <asm/io.h>
	14	#include "stm32mp1_ddr.h"
	15
e70f70aa PD	16	static const char *const clkname[] = {
	17	"ddrc1",
	18	"ddrc2",
	19	"ddrcapb",
	20	"ddrphycapb",
	21	"ddrphyc" /* LAST clock => used for get_rate() */
	22	};
	23
c60fed14	24	int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
e70f70aa PD	25	{
	26	unsigned long ddrphy_clk;
	27	unsigned long ddr_clk;
	28	struct clk clk;
	29	int ret;
58844851	30	unsigned int idx;
e70f70aa PD	31
	32	for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
	33	ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
	34
	35	if (!ret)
	36	ret = clk_enable(&clk);
	37
	38	if (ret) {
	39	printf("error for %s : %d\n", clkname[idx], ret);
	40	return ret;
	41	}
	42	}
	43
	44	priv->clk = clk;
	45	ddrphy_clk = clk_get_rate(&priv->clk);
	46
c60fed14 PD	47	debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
c60fed14 PD	48	mem_speed, (u32)(ddrphy_clk / 1000));
e70f70aa	49	/* max 10% frequency delta */
c60fed14 PD	50	ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
	51	if (ddr_clk > (mem_speed * 100)) {
	52	pr_err("DDR expected freq %d kHz, current is %d kHz\n",
	53	mem_speed, (u32)(ddrphy_clk / 1000));
e70f70aa PD	54	return -EINVAL;
	55	}
	56
	57	return 0;
	58	}
	59
	60	static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
	61	{
	62	struct ddr_info *priv = dev_get_priv(dev);
58844851 PD	63	int ret;
58844851 PD	64	unsigned int idx;
e70f70aa PD	65	struct clk axidcg;
	66	struct stm32mp1_ddr_config config;
	67
9368bdfe PD	68	#define PARAM(x, y, z) \
	69	{ .name = x, \
	70	.offset = offsetof(struct stm32mp1_ddr_config, y), \
	71	.size = sizeof(config.y) / sizeof(u32), \
	72	.present = z, \
	73	}
e70f70aa	74
9368bdfe PD	75	#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
	76	#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
	77	#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
e70f70aa PD	78
	79	const struct {
	80	const char name; / name in DT */
	81	const u32 offset; /* offset in config struct */
	82	const u32 size; /* size of parameters */
9368bdfe	83	bool * const present; /* presence indication for opt */
e70f70aa PD	84	} param[] = {
	85	CTL_PARAM(reg),
	86	CTL_PARAM(timing),
	87	CTL_PARAM(map),
	88	CTL_PARAM(perf),
	89	PHY_PARAM(reg),
	90	PHY_PARAM(timing),
9368bdfe	91	PHY_PARAM_OPT(cal)
e70f70aa PD	92	};
	93
	94	config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
	95	config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
	96	config.info.name = dev_read_string(dev, "st,mem-name");
	97	if (!config.info.name) {
	98	debug("%s: no st,mem-name\n", __func__);
	99	return -EINVAL;
	100	}
	101	printf("RAM: %s\n", config.info.name);
	102
	103	for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
	104	ret = dev_read_u32_array(dev, param[idx].name,
	105	(void *)((u32)&config +
	106	param[idx].offset),
	107	param[idx].size);
	108	debug("%s: %s[0x%x] = %d\n", __func__,
	109	param[idx].name, param[idx].size, ret);
9368bdfe PD	110	if (ret &&
9368bdfe PD	111	(ret != -FDT_ERR_NOTFOUND \|\| !param[idx].present)) {
53bb8316 PD	112	pr_err("%s: Cannot read %s, error=%d\n",
53bb8316 PD	113	__func__, param[idx].name, ret);
e70f70aa PD	114	return -EINVAL;
e70f70aa PD	115	}
9368bdfe PD	116	if (param[idx].present) {
	117	/* save presence of optional parameters */
	118	*param[idx].present = true;
	119	if (ret == -FDT_ERR_NOTFOUND) {
	120	*param[idx].present = false;
	121	#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
	122	/* reset values if used later */
	123	memset((void *)((u32)&config +
	124	param[idx].offset),
	125	0, param[idx].size * sizeof(u32));
	126	#endif
	127	}
	128	}
e70f70aa PD	129	}
	130
	131	ret = clk_get_by_name(dev, "axidcg", &axidcg);
	132	if (ret) {
	133	debug("%s: Cannot found axidcg\n", __func__);
	134	return -EINVAL;
	135	}
	136	clk_disable(&axidcg); /* disable clock gating during init */
	137
	138	stm32mp1_ddr_init(priv, &config);
	139
	140	clk_enable(&axidcg); /* enable clock gating */
	141
	142	/* check size */
	143	debug("%s : get_ram_size(%x, %x)\n", __func__,
	144	(u32)priv->info.base, (u32)STM32_DDR_SIZE);
	145
	146	priv->info.size = get_ram_size((long *)priv->info.base,
	147	STM32_DDR_SIZE);
	148
	149	debug("%s : %x\n", __func__, (u32)priv->info.size);
	150
	151	/* check memory access for all memory */
	152	if (config.info.size != priv->info.size) {
	153	printf("DDR invalid size : 0x%x, expected 0x%x\n",
	154	priv->info.size, config.info.size);
	155	return -EINVAL;
	156	}
	157	return 0;
	158	}
	159
	160	static int stm32mp1_ddr_probe(struct udevice *dev)
	161	{
	162	struct ddr_info *priv = dev_get_priv(dev);
	163	struct regmap *map;
	164	int ret;
	165
	166	debug("STM32MP1 DDR probe\n");
	167	priv->dev = dev;
	168
d3581236	169	ret = regmap_init_mem(dev_ofnode(dev), &map);
e70f70aa PD	170	if (ret)
	171	return ret;
	172
	173	priv->ctl = regmap_get_range(map, 0);
	174	priv->phy = regmap_get_range(map, 1);
	175
	176	priv->rcc = STM32_RCC_BASE;
	177
	178	priv->info.base = STM32_DDR_BASE;
	179
abf2678f PD	180	#if !defined(CONFIG_STM32MP1_TRUSTED) && \
abf2678f PD	181	(!defined(CONFIG_SPL) \|\| defined(CONFIG_SPL_BUILD))
e70f70aa PD	182	priv->info.size = 0;
	183	return stm32mp1_ddr_setup(dev);
	184	#else
	185	priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
	186	return 0;
	187	#endif
	188	}
	189
	190	static int stm32mp1_ddr_get_info(struct udevice dev, struct ram_info info)
	191	{
	192	struct ddr_info *priv = dev_get_priv(dev);
	193
	194	*info = priv->info;
	195
	196	return 0;
	197	}
	198
	199	static struct ram_ops stm32mp1_ddr_ops = {
	200	.get_info = stm32mp1_ddr_get_info,
	201	};
	202
	203	static const struct udevice_id stm32mp1_ddr_ids[] = {
	204	{ .compatible = "st,stm32mp1-ddr" },
	205	{ }
	206	};
	207
	208	U_BOOT_DRIVER(ddr_stm32mp1) = {
	209	.name = "stm32mp1_ddr",
	210	.id = UCLASS_RAM,
	211	.of_match = stm32mp1_ddr_ids,
	212	.ops = &stm32mp1_ddr_ops,
	213	.probe = stm32mp1_ddr_probe,
	214	.priv_auto_alloc_size = sizeof(struct ddr_info),
	215	};