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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
2 | /* |
3 | * Copyright (c) 2011 The Chromium OS Authors. | |
4 | * (C) Copyright 2002-2006 | |
5 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
6 | * | |
7 | * (C) Copyright 2002 | |
8 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
9 | * Marius Groeger <[email protected]> | |
1938f4a5 SG |
10 | */ |
11 | ||
03de305e | 12 | #include <config.h> |
f0293d33 | 13 | #include <bloblist.h> |
52f24238 | 14 | #include <bootstage.h> |
d96c2604 | 15 | #include <clock_legacy.h> |
24b852a7 | 16 | #include <console.h> |
5d6c61ac | 17 | #include <cpu.h> |
30c7c434 | 18 | #include <cpu_func.h> |
70545642 | 19 | #include <cyclic.h> |
4e4bf944 | 20 | #include <display_options.h> |
ab7cd627 | 21 | #include <dm.h> |
4bfd1f5d | 22 | #include <env.h> |
f3998fdc | 23 | #include <env_internal.h> |
5a421904 | 24 | #include <event.h> |
1938f4a5 | 25 | #include <fdtdec.h> |
f828bf25 | 26 | #include <fs.h> |
db41d65a | 27 | #include <hang.h> |
e4fef6cf | 28 | #include <i2c.h> |
67c4e9f8 | 29 | #include <init.h> |
1938f4a5 | 30 | #include <initcall.h> |
f7ae49fc | 31 | #include <log.h> |
fb5cf7f1 | 32 | #include <malloc.h> |
0eb25b61 | 33 | #include <mapmem.h> |
a733b06b | 34 | #include <os.h> |
1938f4a5 | 35 | #include <post.h> |
e47b2d67 | 36 | #include <relocate.h> |
b03e0510 | 37 | #include <serial.h> |
b0edea3c | 38 | #include <spl.h> |
c5d4001a | 39 | #include <status_led.h> |
23471aed | 40 | #include <sysreset.h> |
1057e6cf | 41 | #include <timer.h> |
71c52dba | 42 | #include <trace.h> |
0fc406ab | 43 | #include <upl.h> |
5a541945 | 44 | #include <video.h> |
e4fef6cf | 45 | #include <watchdog.h> |
90526e9f | 46 | #include <asm/cache.h> |
401d1c4f | 47 | #include <asm/global_data.h> |
1938f4a5 SG |
48 | #include <asm/io.h> |
49 | #include <asm/sections.h> | |
ab7cd627 | 50 | #include <dm/root.h> |
056285fd | 51 | #include <linux/errno.h> |
236f7396 | 52 | #include <linux/log2.h> |
1938f4a5 | 53 | |
1938f4a5 | 54 | DECLARE_GLOBAL_DATA_PTR; |
1938f4a5 SG |
55 | |
56 | /* | |
4c509343 | 57 | * TODO([email protected]): IMO this code should be |
1938f4a5 SG |
58 | * refactored to a single function, something like: |
59 | * | |
60 | * void led_set_state(enum led_colour_t colour, int on); | |
61 | */ | |
62 | /************************************************************************ | |
63 | * Coloured LED functionality | |
64 | ************************************************************************ | |
65 | * May be supplied by boards if desired | |
66 | */ | |
c5d4001a JH |
67 | __weak void coloured_LED_init(void) {} |
68 | __weak void red_led_on(void) {} | |
69 | __weak void red_led_off(void) {} | |
70 | __weak void green_led_on(void) {} | |
71 | __weak void green_led_off(void) {} | |
72 | __weak void yellow_led_on(void) {} | |
73 | __weak void yellow_led_off(void) {} | |
74 | __weak void blue_led_on(void) {} | |
75 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
76 | |
77 | /* | |
78 | * Why is gd allocated a register? Prior to reloc it might be better to | |
79 | * just pass it around to each function in this file? | |
80 | * | |
81 | * After reloc one could argue that it is hardly used and doesn't need | |
82 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
83 | * global data for all modules, so that post-reloc we can avoid the massive | |
84 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
85 | * a structure... | |
86 | */ | |
87 | ||
d54d7eb9 | 88 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
89 | static int init_func_watchdog_init(void) |
90 | { | |
ea3310e8 TR |
91 | # if defined(CONFIG_HW_WATCHDOG) && \ |
92 | (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
1473f6ac | 93 | defined(CONFIG_SH) || \ |
46d7a3b3 | 94 | defined(CONFIG_DESIGNWARE_WATCHDOG) || \ |
14a380a8 | 95 | defined(CONFIG_IMX_WATCHDOG)) |
d54d7eb9 | 96 | hw_watchdog_init(); |
e4fef6cf | 97 | puts(" Watchdog enabled\n"); |
ba169d98 | 98 | # endif |
29caf930 | 99 | schedule(); |
e4fef6cf SG |
100 | |
101 | return 0; | |
102 | } | |
103 | ||
104 | int init_func_watchdog_reset(void) | |
105 | { | |
29caf930 | 106 | schedule(); |
e4fef6cf SG |
107 | |
108 | return 0; | |
109 | } | |
110 | #endif /* CONFIG_WATCHDOG */ | |
111 | ||
dd2a6cd0 | 112 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
113 | { |
114 | /* please define platform specific board_add_ram_info() */ | |
115 | } | |
116 | ||
1938f4a5 SG |
117 | static int init_baud_rate(void) |
118 | { | |
bfebc8c9 | 119 | gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); |
1938f4a5 SG |
120 | return 0; |
121 | } | |
122 | ||
123 | static int display_text_info(void) | |
124 | { | |
9b217498 | 125 | #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) |
9fdee7d7 | 126 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 127 | |
ccea96f4 SY |
128 | bss_start = (ulong)__bss_start; |
129 | bss_end = (ulong)__bss_end; | |
b60eff31 | 130 | |
98463903 SG |
131 | #ifdef CONFIG_TEXT_BASE |
132 | text_base = CONFIG_TEXT_BASE; | |
d54d7eb9 | 133 | #else |
9fdee7d7 | 134 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 135 | #endif |
9fdee7d7 DS |
136 | |
137 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
16ef1474 | 138 | text_base, bss_start, bss_end); |
a733b06b | 139 | #endif |
1938f4a5 | 140 | |
1938f4a5 SG |
141 | return 0; |
142 | } | |
143 | ||
23471aed MS |
144 | #ifdef CONFIG_SYSRESET |
145 | static int print_resetinfo(void) | |
146 | { | |
147 | struct udevice *dev; | |
148 | char status[256]; | |
9259bd17 | 149 | bool status_printed = false; |
23471aed MS |
150 | int ret; |
151 | ||
d8cb1dc9 BM |
152 | /* |
153 | * Not all boards have sysreset drivers available during early | |
9259bd17 MS |
154 | * boot, so don't fail if one can't be found. |
155 | */ | |
156 | for (ret = uclass_first_device_check(UCLASS_SYSRESET, &dev); dev; | |
d8cb1dc9 | 157 | ret = uclass_next_device_check(&dev)) { |
9259bd17 MS |
158 | if (ret) { |
159 | debug("%s: %s sysreset device (error: %d)\n", | |
160 | __func__, dev->name, ret); | |
161 | continue; | |
162 | } | |
163 | ||
164 | if (!sysreset_get_status(dev, status, sizeof(status))) { | |
165 | printf("%s%s", status_printed ? " " : "", status); | |
166 | status_printed = true; | |
167 | } | |
23471aed | 168 | } |
9259bd17 MS |
169 | if (status_printed) |
170 | printf("\n"); | |
23471aed MS |
171 | |
172 | return 0; | |
173 | } | |
174 | #endif | |
175 | ||
5d6c61ac MS |
176 | #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) |
177 | static int print_cpuinfo(void) | |
178 | { | |
179 | struct udevice *dev; | |
180 | char desc[512]; | |
181 | int ret; | |
182 | ||
f5b66af2 YL |
183 | dev = cpu_get_current_dev(); |
184 | if (!dev) { | |
185 | debug("%s: Could not get CPU device\n", | |
186 | __func__); | |
187 | return -ENODEV; | |
5d6c61ac MS |
188 | } |
189 | ||
190 | ret = cpu_get_desc(dev, desc, sizeof(desc)); | |
191 | if (ret) { | |
192 | debug("%s: Could not get CPU description (err = %d)\n", | |
193 | dev->name, ret); | |
194 | return ret; | |
195 | } | |
196 | ||
ecfe6633 | 197 | printf("CPU: %s\n", desc); |
5d6c61ac MS |
198 | |
199 | return 0; | |
200 | } | |
201 | #endif | |
202 | ||
1938f4a5 SG |
203 | static int announce_dram_init(void) |
204 | { | |
205 | puts("DRAM: "); | |
206 | return 0; | |
207 | } | |
208 | ||
236f7396 T |
209 | /* |
210 | * From input size calculate its nearest rounded unit scale (multiply of 2^10) | |
211 | * and value in calculated unit scale multiplied by 10 (as fractional fixed | |
212 | * point number with one decimal digit), which is human natural format, | |
213 | * same what uses print_size() function for displaying. Mathematically it is: | |
214 | * round_nearest(val * 2^scale) = size * 10; where: 10 <= val < 10240. | |
215 | * | |
216 | * For example for size=87654321 we calculate scale=20 and val=836 which means | |
217 | * that input has natural human format 83.6 M (mega = 2^20). | |
218 | */ | |
219 | #define compute_size_scale_val(size, scale, val) do { \ | |
220 | scale = ilog2(size) / 10 * 10; \ | |
221 | val = (10 * size + ((1ULL << scale) >> 1)) >> scale; \ | |
222 | if (val == 10240) { val = 10; scale += 10; } \ | |
223 | } while (0) | |
224 | ||
225 | /* | |
226 | * Check if the sizes in their natural units written in decimal format with | |
227 | * one fraction number are same. | |
228 | */ | |
229 | static int sizes_near(unsigned long long size1, unsigned long long size2) | |
230 | { | |
231 | unsigned int size1_scale, size1_val, size2_scale, size2_val; | |
232 | ||
233 | compute_size_scale_val(size1, size1_scale, size1_val); | |
234 | compute_size_scale_val(size2, size2_scale, size2_val); | |
235 | ||
236 | return size1_scale == size2_scale && size1_val == size2_val; | |
237 | } | |
238 | ||
1938f4a5 SG |
239 | static int show_dram_config(void) |
240 | { | |
fa39ffe5 | 241 | unsigned long long size; |
1938f4a5 SG |
242 | int i; |
243 | ||
244 | debug("\nRAM Configuration:\n"); | |
245 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
246 | size += gd->bd->bi_dram[i].size; | |
715f599f BM |
247 | debug("Bank #%d: %llx ", i, |
248 | (unsigned long long)(gd->bd->bi_dram[i].start)); | |
1938f4a5 SG |
249 | #ifdef DEBUG |
250 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
251 | #endif | |
252 | } | |
253 | debug("\nDRAM: "); | |
1938f4a5 | 254 | |
236f7396 T |
255 | print_size(gd->ram_size, ""); |
256 | if (!sizes_near(gd->ram_size, size)) { | |
257 | printf(" (effective "); | |
258 | print_size(size, ")"); | |
259 | } | |
e4fef6cf SG |
260 | board_add_ram_info(0); |
261 | putc('\n'); | |
1938f4a5 SG |
262 | |
263 | return 0; | |
264 | } | |
265 | ||
76b00aca | 266 | __weak int dram_init_banksize(void) |
1938f4a5 | 267 | { |
f120aa75 | 268 | gd->bd->bi_dram[0].start = gd->ram_base; |
1938f4a5 | 269 | gd->bd->bi_dram[0].size = get_effective_memsize(); |
76b00aca SG |
270 | |
271 | return 0; | |
1938f4a5 SG |
272 | } |
273 | ||
55dabcc8 | 274 | #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) |
e4fef6cf SG |
275 | static int init_func_i2c(void) |
276 | { | |
277 | puts("I2C: "); | |
815a76f2 | 278 | i2c_init_all(); |
e4fef6cf SG |
279 | puts("ready\n"); |
280 | return 0; | |
281 | } | |
282 | #endif | |
283 | ||
1938f4a5 SG |
284 | static int setup_mon_len(void) |
285 | { | |
d819250c SB |
286 | #if defined(CONFIG_ARCH_NEXELL) |
287 | gd->mon_len = (ulong)__bss_end - (ulong)__image_copy_start; | |
288 | #elif defined(__ARM__) || defined(__MICROBLAZE__) | |
ccea96f4 | 289 | gd->mon_len = (ulong)__bss_end - (ulong)_start; |
2c88d5e1 | 290 | #elif defined(CONFIG_SANDBOX) && !defined(__riscv) |
ccea96f4 | 291 | gd->mon_len = (ulong)_end - (ulong)_init; |
3c9fc23c | 292 | #elif defined(CONFIG_SANDBOX) |
2c88d5e1 | 293 | /* gcc does not provide _init in crti.o on RISC-V */ |
3c9fc23c HS |
294 | gd->mon_len = 0; |
295 | #elif defined(CONFIG_EFI_APP) | |
ccea96f4 | 296 | gd->mon_len = (ulong)_end - (ulong)_init; |
ea3310e8 | 297 | #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) |
d54d7eb9 | 298 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
11232139 | 299 | #elif defined(CONFIG_SH) || defined(CONFIG_RISCV) |
ccea96f4 | 300 | gd->mon_len = (ulong)(__bss_end) - (ulong)(_start); |
b0b35953 | 301 | #elif defined(CONFIG_SYS_MONITOR_BASE) |
ccea96f4 SY |
302 | /* TODO: use (ulong)__bss_end - (ulong)__text_start; ? */ |
303 | gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 304 | #endif |
1938f4a5 SG |
305 | return 0; |
306 | } | |
307 | ||
308 | __weak int arch_cpu_init(void) | |
309 | { | |
310 | return 0; | |
311 | } | |
312 | ||
8ebf5069 PB |
313 | __weak int mach_cpu_init(void) |
314 | { | |
315 | return 0; | |
316 | } | |
317 | ||
1938f4a5 | 318 | /* Get the top of usable RAM */ |
d768dd88 | 319 | __weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size) |
1938f4a5 | 320 | { |
aa6e94de | 321 | #if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0 |
1e4d11a5 | 322 | /* |
4c509343 | 323 | * Detect whether we have so much RAM that it goes past the end of our |
1e4d11a5 SW |
324 | * 32-bit address space. If so, clip the usable RAM so it doesn't. |
325 | */ | |
aa6e94de | 326 | if (gd->ram_top < CFG_SYS_SDRAM_BASE) |
1e4d11a5 SW |
327 | /* |
328 | * Will wrap back to top of 32-bit space when reservations | |
329 | * are made. | |
330 | */ | |
331 | return 0; | |
332 | #endif | |
1938f4a5 SG |
333 | return gd->ram_top; |
334 | } | |
335 | ||
d63fc994 OP |
336 | __weak int arch_setup_dest_addr(void) |
337 | { | |
338 | return 0; | |
339 | } | |
340 | ||
1938f4a5 SG |
341 | static int setup_dest_addr(void) |
342 | { | |
5aa828e3 | 343 | debug("Monitor len: %08x\n", gd->mon_len); |
1938f4a5 SG |
344 | /* |
345 | * Ram is setup, size stored in gd !! | |
346 | */ | |
d92aee57 | 347 | debug("Ram size: %08llX\n", (unsigned long long)gd->ram_size); |
24c904f3 | 348 | #if CONFIG_VAL(SYS_MEM_TOP_HIDE) |
1938f4a5 SG |
349 | /* |
350 | * Subtract specified amount of memory to hide so that it won't | |
351 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
352 | * the Linux kernel should now get passed the now "corrected" | |
36cc0de0 YS |
353 | * memory size and won't touch it either. This should work |
354 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
355 | * arch/powerpc with bootwrapper support, that recalculate the | |
356 | * memory size from the SDRAM controller setup will have to | |
357 | * get fixed. | |
1938f4a5 | 358 | */ |
36cc0de0 YS |
359 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
360 | #endif | |
aa6e94de TR |
361 | #ifdef CFG_SYS_SDRAM_BASE |
362 | gd->ram_base = CFG_SYS_SDRAM_BASE; | |
1938f4a5 | 363 | #endif |
1473b12a | 364 | gd->ram_top = gd->ram_base + get_effective_memsize(); |
1938f4a5 | 365 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 366 | gd->relocaddr = gd->ram_top; |
d92aee57 | 367 | debug("Ram top: %08llX\n", (unsigned long long)gd->ram_top); |
d63fc994 OP |
368 | |
369 | return arch_setup_dest_addr(); | |
1938f4a5 SG |
370 | } |
371 | ||
7c5c137c | 372 | #ifdef CFG_PRAM |
1938f4a5 SG |
373 | /* reserve protected RAM */ |
374 | static int reserve_pram(void) | |
375 | { | |
376 | ulong reg; | |
377 | ||
7c5c137c | 378 | reg = env_get_ulong("pram", 10, CFG_PRAM); |
a0ba279a | 379 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 380 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 381 | gd->relocaddr); |
1938f4a5 SG |
382 | return 0; |
383 | } | |
7c5c137c | 384 | #endif /* CFG_PRAM */ |
1938f4a5 SG |
385 | |
386 | /* Round memory pointer down to next 4 kB limit */ | |
387 | static int reserve_round_4k(void) | |
388 | { | |
a0ba279a | 389 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
390 | return 0; |
391 | } | |
392 | ||
79926e4f OP |
393 | __weak int arch_reserve_mmu(void) |
394 | { | |
395 | return 0; | |
396 | } | |
397 | ||
4ef9c772 | 398 | static int reserve_video_from_videoblob(void) |
5a541945 | 399 | { |
456bdb70 | 400 | if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() > PHASE_SPL) { |
5bc610a7 | 401 | struct video_handoff *ho; |
eefe23c1 | 402 | int ret = 0; |
5bc610a7 NJ |
403 | |
404 | ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho)); | |
405 | if (!ho) | |
eefe23c1 DT |
406 | return log_msg_ret("Missing video bloblist", -ENOENT); |
407 | ||
408 | ret = video_reserve_from_bloblist(ho); | |
409 | if (ret) | |
410 | return log_msg_ret("Invalid Video handoff info", ret); | |
4ef9c772 DT |
411 | |
412 | /* Sanity check fb from blob is before current relocaddr */ | |
413 | if (likely(gd->relocaddr > (unsigned long)ho->fb)) | |
414 | gd->relocaddr = ho->fb; | |
415 | } | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | /* | |
421 | * Check if any bloblist received specifying reserved areas from previous stage and adjust | |
422 | * gd->relocaddr accordingly, so that we start reserving after pre-reserved areas | |
423 | * from previous stage. | |
424 | * | |
425 | * NOTE: | |
426 | * IT is recommended that all bloblists from previous stage are reserved from ram_top | |
427 | * as next stage will simply start reserving further regions after them. | |
428 | */ | |
429 | static int setup_relocaddr_from_bloblist(void) | |
430 | { | |
431 | reserve_video_from_videoblob(); | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
436 | static int reserve_video(void) | |
437 | { | |
438 | if (CONFIG_IS_ENABLED(VIDEO)) { | |
f9b7bd7e SG |
439 | ulong addr; |
440 | int ret; | |
441 | ||
442 | addr = gd->relocaddr; | |
443 | ret = video_reserve(&addr); | |
444 | if (ret) | |
445 | return ret; | |
446 | debug("Reserving %luk for video at: %08lx\n", | |
447 | ((unsigned long)gd->relocaddr - addr) >> 10, addr); | |
448 | gd->relocaddr = addr; | |
449 | } | |
e4fef6cf SG |
450 | |
451 | return 0; | |
452 | } | |
e4fef6cf | 453 | |
8703ef3f SG |
454 | static int reserve_trace(void) |
455 | { | |
456 | #ifdef CONFIG_TRACE | |
457 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
458 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
7ea33579 HS |
459 | debug("Reserving %luk for trace data at: %08lx\n", |
460 | (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
8703ef3f SG |
461 | #endif |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
1938f4a5 SG |
466 | static int reserve_uboot(void) |
467 | { | |
ff2b2ba8 AB |
468 | if (!(gd->flags & GD_FLG_SKIP_RELOC)) { |
469 | /* | |
470 | * reserve memory for U-Boot code, data & bss | |
471 | * round down to next 4 kB limit | |
472 | */ | |
473 | gd->relocaddr -= gd->mon_len; | |
474 | gd->relocaddr &= ~(4096 - 1); | |
475 | #if defined(CONFIG_E500) || defined(CONFIG_MIPS) | |
476 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
477 | gd->relocaddr &= ~(65536 - 1); | |
478 | #endif | |
479 | ||
5aa828e3 | 480 | debug("Reserving %dk for U-Boot at: %08lx\n", |
ff2b2ba8 AB |
481 | gd->mon_len >> 10, gd->relocaddr); |
482 | } | |
a0ba279a MY |
483 | |
484 | gd->start_addr_sp = gd->relocaddr; | |
485 | ||
1938f4a5 SG |
486 | return 0; |
487 | } | |
488 | ||
65c141eb PD |
489 | /* |
490 | * reserve after start_addr_sp the requested size and make the stack pointer | |
491 | * 16-byte aligned, this alignment is needed for cast on the reserved memory | |
492 | * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes | |
493 | * = ARMv8 Instruction Set Overview: quad word, 16 bytes | |
494 | */ | |
495 | static unsigned long reserve_stack_aligned(size_t size) | |
496 | { | |
497 | return ALIGN_DOWN(gd->start_addr_sp - size, 16); | |
498 | } | |
499 | ||
5f7adb5b VM |
500 | #ifdef CONFIG_SYS_NONCACHED_MEMORY |
501 | static int reserve_noncached(void) | |
502 | { | |
5e0404ff | 503 | /* |
09f5be61 SG |
504 | * The value of gd->start_addr_sp must match the value of |
505 | * mem_malloc_start calculated in board_r.c:initr_malloc(), which is | |
506 | * passed to dlmalloc.c:mem_malloc_init() and then used by | |
5e0404ff SW |
507 | * cache.c:noncached_init() |
508 | * | |
509 | * These calculations must match the code in cache.c:noncached_init() | |
510 | */ | |
511 | gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - | |
512 | MMU_SECTION_SIZE; | |
513 | gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY, | |
514 | MMU_SECTION_SIZE); | |
5f7adb5b VM |
515 | debug("Reserving %dM for noncached_alloc() at: %08lx\n", |
516 | CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp); | |
517 | ||
518 | return 0; | |
519 | } | |
520 | #endif | |
521 | ||
1938f4a5 SG |
522 | /* reserve memory for malloc() area */ |
523 | static int reserve_malloc(void) | |
524 | { | |
65c141eb | 525 | gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN); |
1938f4a5 | 526 | debug("Reserving %dk for malloc() at: %08lx\n", |
16ef1474 | 527 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
5f7adb5b VM |
528 | #ifdef CONFIG_SYS_NONCACHED_MEMORY |
529 | reserve_noncached(); | |
530 | #endif | |
531 | ||
1938f4a5 SG |
532 | return 0; |
533 | } | |
534 | ||
535 | /* (permanently) allocate a Board Info struct */ | |
536 | static int reserve_board(void) | |
537 | { | |
d54d7eb9 | 538 | if (!gd->bd) { |
b75d8dc5 MY |
539 | gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info)); |
540 | gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp, | |
541 | sizeof(struct bd_info)); | |
542 | memset(gd->bd, '\0', sizeof(struct bd_info)); | |
d54d7eb9 | 543 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", |
b75d8dc5 | 544 | sizeof(struct bd_info), gd->start_addr_sp); |
d54d7eb9 | 545 | } |
1938f4a5 SG |
546 | return 0; |
547 | } | |
548 | ||
1938f4a5 SG |
549 | static int reserve_global_data(void) |
550 | { | |
65c141eb | 551 | gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t)); |
a0ba279a | 552 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); |
1938f4a5 | 553 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
16ef1474 | 554 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
555 | return 0; |
556 | } | |
557 | ||
558 | static int reserve_fdt(void) | |
559 | { | |
19b18daa OP |
560 | if (!IS_ENABLED(CONFIG_OF_EMBED)) { |
561 | /* | |
562 | * If the device tree is sitting immediately above our image | |
563 | * then we must relocate it. If it is embedded in the data | |
564 | * section, then it will be relocated with other data. | |
565 | */ | |
566 | if (gd->fdt_blob) { | |
5019d328 SG |
567 | gd->boardf->fdt_size = |
568 | ALIGN(fdt_totalsize(gd->fdt_blob), 32); | |
19b18daa | 569 | |
5019d328 SG |
570 | gd->start_addr_sp = reserve_stack_aligned( |
571 | gd->boardf->fdt_size); | |
572 | gd->boardf->new_fdt = map_sysmem(gd->start_addr_sp, | |
573 | gd->boardf->fdt_size); | |
19b18daa | 574 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
5019d328 | 575 | gd->boardf->fdt_size, gd->start_addr_sp); |
19b18daa | 576 | } |
1938f4a5 SG |
577 | } |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
25e7dc6a SG |
582 | static int reserve_bootstage(void) |
583 | { | |
584 | #ifdef CONFIG_BOOTSTAGE | |
48008ec7 | 585 | int size = bootstage_get_size(true); |
25e7dc6a | 586 | |
65c141eb | 587 | gd->start_addr_sp = reserve_stack_aligned(size); |
89419728 | 588 | gd->boardf->new_bootstage = map_sysmem(gd->start_addr_sp, size); |
25e7dc6a SG |
589 | debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, |
590 | gd->start_addr_sp); | |
591 | #endif | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
d6f87712 | 596 | __weak int arch_reserve_stacks(void) |
1938f4a5 | 597 | { |
68145d4c AB |
598 | return 0; |
599 | } | |
8cae8a68 | 600 | |
68145d4c AB |
601 | static int reserve_stacks(void) |
602 | { | |
603 | /* make stack pointer 16-byte aligned */ | |
65c141eb | 604 | gd->start_addr_sp = reserve_stack_aligned(16); |
1938f4a5 SG |
605 | |
606 | /* | |
4c509343 | 607 | * let the architecture-specific code tailor gd->start_addr_sp and |
68145d4c | 608 | * gd->irq_sp |
1938f4a5 | 609 | */ |
68145d4c | 610 | return arch_reserve_stacks(); |
1938f4a5 SG |
611 | } |
612 | ||
f0293d33 SG |
613 | static int reserve_bloblist(void) |
614 | { | |
615 | #ifdef CONFIG_BLOBLIST | |
4a08fae1 | 616 | /* Align to a 4KB boundary for easier reading of addresses */ |
9fe06464 SG |
617 | gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - |
618 | CONFIG_BLOBLIST_SIZE_RELOC, 0x1000); | |
e8218976 SG |
619 | gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp, |
620 | CONFIG_BLOBLIST_SIZE_RELOC); | |
f0293d33 SG |
621 | #endif |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
1938f4a5 SG |
626 | static int display_new_sp(void) |
627 | { | |
a0ba279a | 628 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
629 | |
630 | return 0; | |
631 | } | |
632 | ||
81e7cb1e | 633 | __weak int arch_setup_bdinfo(void) |
ba743103 OP |
634 | { |
635 | return 0; | |
636 | } | |
637 | ||
81e7cb1e OP |
638 | int setup_bdinfo(void) |
639 | { | |
a4aa1889 OP |
640 | struct bd_info *bd = gd->bd; |
641 | ||
49122242 OP |
642 | if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) { |
643 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
644 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
645 | } | |
646 | ||
81e7cb1e OP |
647 | return arch_setup_bdinfo(); |
648 | } | |
649 | ||
1938f4a5 SG |
650 | #ifdef CONFIG_POST |
651 | static int init_post(void) | |
652 | { | |
653 | post_bootmode_init(); | |
654 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
655 | ||
656 | return 0; | |
657 | } | |
658 | #endif | |
659 | ||
1938f4a5 SG |
660 | static int reloc_fdt(void) |
661 | { | |
19b18daa | 662 | if (!IS_ENABLED(CONFIG_OF_EMBED)) { |
6abd992a SG |
663 | if (gd->boardf->new_fdt) { |
664 | memcpy(gd->boardf->new_fdt, gd->fdt_blob, | |
19b18daa | 665 | fdt_totalsize(gd->fdt_blob)); |
6abd992a | 666 | gd->fdt_blob = gd->boardf->new_fdt; |
19b18daa | 667 | } |
1938f4a5 SG |
668 | } |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
25e7dc6a SG |
673 | static int reloc_bootstage(void) |
674 | { | |
675 | #ifdef CONFIG_BOOTSTAGE | |
676 | if (gd->flags & GD_FLG_SKIP_RELOC) | |
677 | return 0; | |
89419728 SG |
678 | if (gd->boardf->new_bootstage) |
679 | bootstage_relocate(gd->boardf->new_bootstage); | |
25e7dc6a SG |
680 | #endif |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
f0293d33 SG |
685 | static int reloc_bloblist(void) |
686 | { | |
687 | #ifdef CONFIG_BLOBLIST | |
d5b6e91b SG |
688 | /* |
689 | * Relocate only if we are supposed to send it | |
690 | */ | |
691 | if ((gd->flags & GD_FLG_SKIP_RELOC) && | |
692 | CONFIG_BLOBLIST_SIZE == CONFIG_BLOBLIST_SIZE_RELOC) { | |
693 | debug("Not relocating bloblist\n"); | |
f0293d33 | 694 | return 0; |
d5b6e91b | 695 | } |
e8218976 | 696 | if (gd->boardf->new_bloblist) { |
f0293d33 | 697 | debug("Copying bloblist from %p to %p, size %x\n", |
e8218976 SG |
698 | gd->bloblist, gd->boardf->new_bloblist, |
699 | gd->bloblist->total_size); | |
700 | return bloblist_reloc(gd->boardf->new_bloblist, | |
1ef43f3b | 701 | CONFIG_BLOBLIST_SIZE_RELOC); |
f0293d33 SG |
702 | } |
703 | #endif | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
7bceb161 | 708 | void mcheck_on_ramrelocation(size_t offset); |
1938f4a5 SG |
709 | static int setup_reloc(void) |
710 | { | |
47d7d036 | 711 | if (!(gd->flags & GD_FLG_SKIP_RELOC)) { |
98463903 | 712 | #ifdef CONFIG_TEXT_BASE |
53207bfd | 713 | #ifdef ARM |
47d7d036 | 714 | gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; |
d58c0074 MS |
715 | #elif defined(CONFIG_MICROBLAZE) |
716 | gd->reloc_off = gd->relocaddr - (u32)_start; | |
53207bfd | 717 | #elif defined(CONFIG_M68K) |
47d7d036 MV |
718 | /* |
719 | * On all ColdFire arch cpu, monitor code starts always | |
720 | * just after the default vector table location, so at 0x400 | |
721 | */ | |
98463903 | 722 | gd->reloc_off = gd->relocaddr - (CONFIG_TEXT_BASE + 0x400); |
001d1885 | 723 | #elif !defined(CONFIG_SANDBOX) |
98463903 | 724 | gd->reloc_off = gd->relocaddr - CONFIG_TEXT_BASE; |
e310b93e | 725 | #endif |
d54d7eb9 | 726 | #endif |
47d7d036 MV |
727 | } |
728 | ||
1938f4a5 SG |
729 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
730 | ||
47d7d036 MV |
731 | if (gd->flags & GD_FLG_SKIP_RELOC) { |
732 | debug("Skipping relocation due to flag\n"); | |
733 | } else { | |
7bceb161 EU |
734 | #ifdef MCHECK_HEAP_PROTECTION |
735 | mcheck_on_ramrelocation(gd->reloc_off); | |
736 | #endif | |
47d7d036 MV |
737 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); |
738 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", | |
739 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), | |
740 | gd->start_addr_sp); | |
741 | } | |
1938f4a5 SG |
742 | |
743 | return 0; | |
744 | } | |
745 | ||
2a792753 | 746 | #ifdef CONFIG_OF_BOARD_FIXUP |
747 | static int fix_fdt(void) | |
748 | { | |
749 | return board_fix_fdt((void *)gd->fdt_blob); | |
750 | } | |
751 | #endif | |
752 | ||
1938f4a5 | 753 | /* ARM calls relocate_code from its crt0.S */ |
8f015d37 | 754 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
755 | |
756 | static int jump_to_copy(void) | |
757 | { | |
f05ad9ba SG |
758 | if (gd->flags & GD_FLG_SKIP_RELOC) |
759 | return 0; | |
48a33806 SG |
760 | /* |
761 | * x86 is special, but in a nice way. It uses a trampoline which | |
762 | * enables the dcache if possible. | |
763 | * | |
764 | * For now, other archs use relocate_code(), which is implemented | |
765 | * similarly for all archs. When we do generic relocation, hopefully | |
766 | * we can make all archs enable the dcache prior to relocation. | |
767 | */ | |
3fb80163 | 768 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
769 | /* |
770 | * SDRAM and console are now initialised. The final stack can now | |
771 | * be setup in SDRAM. Code execution will continue in Flash, but | |
772 | * with the stack in SDRAM and Global Data in temporary memory | |
773 | * (CPU cache) | |
774 | */ | |
f0c7d9c7 | 775 | arch_setup_gd(gd->new_gd); |
8f015d37 SG |
776 | # if CONFIG_IS_ENABLED(X86_64) |
777 | board_init_f_r_trampoline64(gd->new_gd, gd->start_addr_sp); | |
778 | # else | |
779 | board_init_f_r_trampoline(gd->start_addr_sp); | |
780 | # endif | |
48a33806 | 781 | #else |
a0ba279a | 782 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 783 | #endif |
1938f4a5 SG |
784 | |
785 | return 0; | |
786 | } | |
787 | #endif | |
788 | ||
789 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
b383d6c0 | 790 | static int initf_bootstage(void) |
1938f4a5 | 791 | { |
baa7d345 SG |
792 | bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && |
793 | IS_ENABLED(CONFIG_BOOTSTAGE_STASH); | |
b383d6c0 SG |
794 | int ret; |
795 | ||
824bb1b4 | 796 | ret = bootstage_init(!from_spl); |
b383d6c0 SG |
797 | if (ret) |
798 | return ret; | |
824bb1b4 | 799 | if (from_spl) { |
e83ced1a | 800 | ret = bootstage_unstash_default(); |
824bb1b4 SG |
801 | if (ret && ret != -ENOENT) { |
802 | debug("Failed to unstash bootstage: err=%d\n", ret); | |
803 | return ret; | |
804 | } | |
805 | } | |
b383d6c0 | 806 | |
1938f4a5 SG |
807 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
ab7cd627 SG |
812 | static int initf_dm(void) |
813 | { | |
3d6d5075 | 814 | #if defined(CONFIG_DM) && CONFIG_IS_ENABLED(SYS_MALLOC_F) |
ab7cd627 SG |
815 | int ret; |
816 | ||
b67eefdb | 817 | bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f"); |
ab7cd627 | 818 | ret = dm_init_and_scan(true); |
b67eefdb | 819 | bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F); |
ab7cd627 SG |
820 | if (ret) |
821 | return ret; | |
4b9a121f OP |
822 | |
823 | if (IS_ENABLED(CONFIG_TIMER_EARLY)) { | |
824 | ret = dm_timer_init(); | |
825 | if (ret) | |
826 | return ret; | |
827 | } | |
1057e6cf | 828 | #endif |
ab7cd627 SG |
829 | |
830 | return 0; | |
831 | } | |
832 | ||
146251f8 SG |
833 | /* Architecture-specific memory reservation */ |
834 | __weak int reserve_arch(void) | |
835 | { | |
836 | return 0; | |
837 | } | |
838 | ||
016e4ae7 OP |
839 | __weak int checkcpu(void) |
840 | { | |
841 | return 0; | |
842 | } | |
843 | ||
fbf9c154 OP |
844 | __weak int clear_bss(void) |
845 | { | |
846 | return 0; | |
847 | } | |
848 | ||
0fc406ab SG |
849 | static int initf_upl(void) |
850 | { | |
851 | struct upl *upl; | |
852 | int ret; | |
853 | ||
854 | if (!IS_ENABLED(CONFIG_UPL_IN) || !(gd->flags & GD_FLG_UPL)) | |
855 | return 0; | |
856 | ||
857 | upl = malloc(sizeof(struct upl)); | |
858 | if (upl) | |
859 | ret = upl_read_handoff(upl, oftree_default()); | |
860 | if (ret) { | |
861 | printf("UPL handoff: read failure (err=%dE)\n", ret); | |
862 | return ret; | |
863 | } | |
864 | gd_set_upl(upl); | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
4acff452 | 869 | static const init_fnc_t init_sequence_f[] = { |
1938f4a5 | 870 | setup_mon_len, |
b45122fd | 871 | #ifdef CONFIG_OF_CONTROL |
0879361f | 872 | fdtdec_setup, |
b45122fd | 873 | #endif |
7ef8e9b0 | 874 | #ifdef CONFIG_TRACE_EARLY |
71c52dba | 875 | trace_early_init, |
d210718d | 876 | #endif |
768e0f52 | 877 | initf_malloc, |
0fc406ab | 878 | initf_upl, |
af1bc0cf | 879 | log_init, |
5ac44a55 | 880 | initf_bootstage, /* uses its own timer, so does not need DM */ |
5a421904 | 881 | event_init, |
3d653180 | 882 | bloblist_maybe_init, |
8e8d45ee OP |
883 | #if defined(CONFIG_CONSOLE_RECORD_INIT_F) |
884 | console_record_init, | |
885 | #endif | |
13a7db9a | 886 | INITCALL_EVENT(EVT_FSP_INIT_F), |
1938f4a5 | 887 | arch_cpu_init, /* basic arch cpu dependent setup */ |
8ebf5069 | 888 | mach_cpu_init, /* SoC/machine dependent CPU setup */ |
3ea0953d | 889 | initf_dm, |
1938f4a5 SG |
890 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
891 | board_early_init_f, | |
892 | #endif | |
727e94a4 | 893 | #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) |
c252c068 | 894 | /* get CPU and bus clocks according to the environment variable */ |
e4fef6cf | 895 | get_clocks, /* get CPU and bus clocks (etc.) */ |
1793e782 | 896 | #endif |
56c3aa9a | 897 | #if !defined(CONFIG_M68K) || (defined(CONFIG_M68K) && !defined(CONFIG_MCFTMR)) |
1938f4a5 | 898 | timer_init, /* initialize timer */ |
0ce45287 | 899 | #endif |
e4fef6cf SG |
900 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
901 | board_postclk_init, | |
1938f4a5 SG |
902 | #endif |
903 | env_init, /* initialize environment */ | |
904 | init_baud_rate, /* initialze baudrate settings */ | |
905 | serial_init, /* serial communications setup */ | |
906 | console_init_f, /* stage 1 init of console */ | |
907 | display_options, /* say that we are here */ | |
908 | display_text_info, /* show debugging info if required */ | |
e4fef6cf | 909 | checkcpu, |
23471aed MS |
910 | #if defined(CONFIG_SYSRESET) |
911 | print_resetinfo, | |
912 | #endif | |
cc664000 | 913 | #if defined(CONFIG_DISPLAY_CPUINFO) |
1938f4a5 | 914 | print_cpuinfo, /* display cpu info (and speed) */ |
cc664000 | 915 | #endif |
af9e6ad4 CJF |
916 | #if defined(CONFIG_DTB_RESELECT) |
917 | embedded_dtb_select, | |
918 | #endif | |
1938f4a5 | 919 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 920 | show_board_info, |
e4fef6cf SG |
921 | #endif |
922 | INIT_FUNC_WATCHDOG_INIT | |
c9eff0a6 | 923 | INITCALL_EVENT(EVT_MISC_INIT_F), |
e4fef6cf | 924 | INIT_FUNC_WATCHDOG_RESET |
55dabcc8 | 925 | #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) |
e4fef6cf | 926 | init_func_i2c, |
1938f4a5 SG |
927 | #endif |
928 | announce_dram_init, | |
1938f4a5 | 929 | dram_init, /* configure available RAM banks */ |
e4fef6cf SG |
930 | #ifdef CONFIG_POST |
931 | post_init_f, | |
932 | #endif | |
933 | INIT_FUNC_WATCHDOG_RESET | |
65cc0e2a | 934 | #if defined(CFG_SYS_DRAM_TEST) |
e4fef6cf | 935 | testdram, |
65cc0e2a | 936 | #endif /* CFG_SYS_DRAM_TEST */ |
e4fef6cf SG |
937 | INIT_FUNC_WATCHDOG_RESET |
938 | ||
1938f4a5 SG |
939 | #ifdef CONFIG_POST |
940 | init_post, | |
941 | #endif | |
e4fef6cf | 942 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
943 | /* |
944 | * Now that we have DRAM mapped and working, we can | |
945 | * relocate the code and continue running from DRAM. | |
946 | * | |
947 | * Reserve memory at end of RAM for (top down in that order): | |
948 | * - area that won't get touched by U-Boot and Linux (optional) | |
949 | * - kernel log buffer | |
950 | * - protected RAM | |
951 | * - LCD framebuffer | |
952 | * - monitor code | |
953 | * - board info struct | |
954 | */ | |
955 | setup_dest_addr, | |
0858e03b | 956 | #if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_OF_INITIAL_DTB_READONLY) |
313981c2 PP |
957 | fix_fdt, |
958 | #endif | |
7c5c137c | 959 | #ifdef CFG_PRAM |
1938f4a5 SG |
960 | reserve_pram, |
961 | #endif | |
962 | reserve_round_4k, | |
4ef9c772 | 963 | setup_relocaddr_from_bloblist, |
79926e4f | 964 | arch_reserve_mmu, |
5a541945 | 965 | reserve_video, |
8703ef3f | 966 | reserve_trace, |
1938f4a5 SG |
967 | reserve_uboot, |
968 | reserve_malloc, | |
969 | reserve_board, | |
1938f4a5 SG |
970 | reserve_global_data, |
971 | reserve_fdt, | |
0858e03b T |
972 | #if defined(CONFIG_OF_BOARD_FIXUP) && defined(CONFIG_OF_INITIAL_DTB_READONLY) |
973 | reloc_fdt, | |
974 | fix_fdt, | |
975 | #endif | |
25e7dc6a | 976 | reserve_bootstage, |
f0293d33 | 977 | reserve_bloblist, |
146251f8 | 978 | reserve_arch, |
1938f4a5 | 979 | reserve_stacks, |
76b00aca | 980 | dram_init_banksize, |
1938f4a5 | 981 | show_dram_config, |
e4fef6cf | 982 | INIT_FUNC_WATCHDOG_RESET |
1532885c | 983 | setup_bdinfo, |
1938f4a5 | 984 | display_new_sp, |
e4fef6cf | 985 | INIT_FUNC_WATCHDOG_RESET |
0858e03b | 986 | #if !defined(CONFIG_OF_BOARD_FIXUP) || !defined(CONFIG_OF_INITIAL_DTB_READONLY) |
1938f4a5 | 987 | reloc_fdt, |
0858e03b | 988 | #endif |
25e7dc6a | 989 | reloc_bootstage, |
f0293d33 | 990 | reloc_bloblist, |
1938f4a5 | 991 | setup_reloc, |
3fb80163 | 992 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 | 993 | copy_uboot_to_ram, |
313aef37 SG |
994 | do_elf_reloc_fixups, |
995 | #endif | |
de5e5cea | 996 | clear_bss, |
50128aeb RV |
997 | /* |
998 | * Deregister all cyclic functions before relocation, so that | |
999 | * gd->cyclic_list does not contain any references to pre-relocation | |
1000 | * devices. Drivers will register their cyclic functions anew when the | |
1001 | * devices are probed again. | |
1002 | * | |
1003 | * This should happen as late as possible so that the window where a | |
1004 | * watchdog device is not serviced is as small as possible. | |
1005 | */ | |
1006 | cyclic_unregister_all, | |
8f015d37 | 1007 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
1008 | jump_to_copy, |
1009 | #endif | |
1010 | NULL, | |
1011 | }; | |
1012 | ||
1013 | void board_init_f(ulong boot_flags) | |
1014 | { | |
6abd992a SG |
1015 | struct board_f boardf; |
1016 | ||
1938f4a5 | 1017 | gd->flags = boot_flags; |
f44fded2 | 1018 | gd->flags &= ~GD_FLG_HAVE_CONSOLE; |
6abd992a | 1019 | gd->boardf = &boardf; |
1938f4a5 SG |
1020 | |
1021 | if (initcall_run_list(init_sequence_f)) | |
1022 | hang(); | |
1023 | ||
9b217498 | 1024 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
264d298f AB |
1025 | !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ |
1026 | !defined(CONFIG_ARC) | |
1938f4a5 SG |
1027 | /* NOTREACHED - jump_to_copy() does not return */ |
1028 | hang(); | |
1029 | #endif | |
1030 | } | |
1031 | ||
3fb80163 | 1032 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
1033 | /* |
1034 | * For now this code is only used on x86. | |
1035 | * | |
1036 | * init_sequence_f_r is the list of init functions which are run when | |
1037 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
1038 | * The following limitations must be considered when implementing an | |
1039 | * '_f_r' function: | |
1040 | * - 'static' variables are read-only | |
1041 | * - Global Data (gd->xxx) is read/write | |
1042 | * | |
1043 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
1044 | * supported). It _should_, if possible, copy global data to RAM and | |
1045 | * initialise the CPU caches (to speed up the relocation process) | |
1046 | * | |
1047 | * NOTE: At present only x86 uses this route, but it is intended that | |
1048 | * all archs will move to this when generic relocation is implemented. | |
1049 | */ | |
4acff452 | 1050 | static const init_fnc_t init_sequence_f_r[] = { |
530f27ea | 1051 | #if !CONFIG_IS_ENABLED(X86_64) |
48a33806 | 1052 | init_cache_f_r, |
530f27ea | 1053 | #endif |
48a33806 SG |
1054 | |
1055 | NULL, | |
1056 | }; | |
1057 | ||
1058 | void board_init_f_r(void) | |
1059 | { | |
1060 | if (initcall_run_list(init_sequence_f_r)) | |
1061 | hang(); | |
1062 | ||
e4d6ab0c SG |
1063 | /* |
1064 | * The pre-relocation drivers may be using memory that has now gone | |
1065 | * away. Mark serial as unavailable - this will fall back to the debug | |
1066 | * UART if available. | |
af1bc0cf SG |
1067 | * |
1068 | * Do the same with log drivers since the memory may not be available. | |
e4d6ab0c | 1069 | */ |
af1bc0cf | 1070 | gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); |
5ee94b4f SG |
1071 | #ifdef CONFIG_TIMER |
1072 | gd->timer = NULL; | |
1073 | #endif | |
e4d6ab0c | 1074 | |
48a33806 SG |
1075 | /* |
1076 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1077 | * Transfer execution from Flash to RAM by calculating the address | |
1078 | * of the in-RAM copy of board_init_r() and calling it | |
1079 | */ | |
7bf9f20d | 1080 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
1081 | |
1082 | /* NOTREACHED - board_init_r() does not return */ | |
1083 | hang(); | |
1084 | } | |
5bcd19aa | 1085 | #endif /* CONFIG_X86 */ |