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53dd6ce4 WD |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Sangmoon Kim, [email protected]. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #define CONFIG_MPC824X 1 | |
28 | #define CONFIG_MPC8245 1 | |
29 | #define CONFIG_KVME080 1 | |
30 | ||
2ae18241 WD |
31 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
32 | ||
53dd6ce4 WD |
33 | #define CONFIG_CONS_INDEX 1 |
34 | ||
35 | #define CONFIG_BAUDRATE 115200 | |
36 | ||
37 | #define CONFIG_BOOTDELAY 5 | |
38 | ||
39 | #define CONFIG_IPADDR 192.168.0.2 | |
40 | #define CONFIG_NETMASK 255.255.255.0 | |
41 | #define CONFIG_SERVERIP 192.168.0.1 | |
42 | ||
43 | #define CONFIG_BOOTARGS \ | |
44 | "console=ttyS0,115200 " \ | |
45 | "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \ | |
46 | "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \ | |
47 | "kvme080:eth0:none " \ | |
48 | "mtdparts=phys_mapped_flash:12m(root),-(kernel)" | |
49 | ||
50 | #define CONFIG_BOOTCOMMAND \ | |
51 | "tftp 800000 kvme080/uImage; " \ | |
52 | "bootm 800000" | |
53 | ||
54 | #define CONFIG_LOADADDR 800000 | |
55 | ||
56 | #define CONFIG_BOARD_EARLY_INIT_F | |
57 | #define CONFIG_BOARD_EARLY_INIT_R | |
58 | #define CONFIG_MISC_INIT_R | |
59 | ||
60 | #define CONFIG_LOADS_ECHO 1 | |
6d0f6bcf | 61 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
53dd6ce4 WD |
62 | |
63 | #undef CONFIG_WATCHDOG | |
64 | ||
2fd90ce5 JL |
65 | /* |
66 | * BOOTP options | |
67 | */ | |
68 | #define CONFIG_BOOTP_SUBNETMASK | |
69 | #define CONFIG_BOOTP_GATEWAY | |
70 | #define CONFIG_BOOTP_HOSTNAME | |
71 | #define CONFIG_BOOTP_BOOTPATH | |
72 | #define CONFIG_BOOTP_BOOTFILESIZE | |
73 | ||
53dd6ce4 WD |
74 | |
75 | #define CONFIG_MAC_PARTITION | |
76 | #define CONFIG_DOS_PARTITION | |
77 | ||
78 | #define CONFIG_RTC_DS164x | |
79 | ||
53dd6ce4 | 80 | |
bc234c12 JL |
81 | /* |
82 | * Command line configuration. | |
83 | */ | |
84 | #include <config_cmd_default.h> | |
85 | ||
86 | #define CONFIG_CMD_ASKENV | |
87 | #define CONFIG_CMD_CACHE | |
88 | #define CONFIG_CMD_DATE | |
89 | #define CONFIG_CMD_DHCP | |
90 | #define CONFIG_CMD_DIAG | |
91 | #define CONFIG_CMD_EEPROM | |
92 | #define CONFIG_CMD_ELF | |
93 | #define CONFIG_CMD_I2C | |
94 | #define CONFIG_CMD_JFFS2 | |
95 | #define CONFIG_CMD_NFS | |
96 | #define CONFIG_CMD_PCI | |
97 | #define CONFIG_CMD_PING | |
98 | #define CONFIG_CMD_SDRAM | |
99 | #define CONFIG_CMD_SNTP | |
53dd6ce4 | 100 | |
bc234c12 JL |
101 | |
102 | #define CONFIG_NETCONSOLE | |
53dd6ce4 | 103 | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_LONGHELP |
105 | #define CONFIG_SYS_PROMPT "=> " | |
106 | #define CONFIG_SYS_CBSIZE 256 | |
107 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
108 | #define CONFIG_SYS_MAXARGS 16 | |
109 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
53dd6ce4 | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_MEMTEST_START 0x00400000 |
112 | #define CONFIG_SYS_MEMTEST_END 0x07C00000 | |
53dd6ce4 | 113 | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
115 | #define CONFIG_SYS_HZ 1000 | |
53dd6ce4 | 116 | |
6d0f6bcf | 117 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
53dd6ce4 | 118 | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
120 | #define CONFIG_SYS_INIT_RAM_END 0x1000 | |
121 | #define CONFIG_SYS_GBL_DATA_SIZE 128 | |
122 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
53dd6ce4 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
125 | #define CONFIG_SYS_FLASH_BASE 0x7C000000 | |
126 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 | |
127 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xFF000000 | |
128 | #define CONFIG_SYS_NS16550_COM1 0xFF080000 | |
129 | #define CONFIG_SYS_NS16550_COM2 0xFF080010 | |
130 | #define CONFIG_SYS_NS16550_COM3 0xFF080020 | |
131 | #define CONFIG_SYS_NS16550_COM4 0xFF080030 | |
132 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 | |
53dd6ce4 | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
135 | #define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024) | |
136 | #define CONFIG_SYS_NVRAM_SIZE 0x7FFF8 | |
53dd6ce4 WD |
137 | |
138 | #define CONFIG_VERY_BIG_RAM | |
139 | ||
6d0f6bcf | 140 | #define CONFIG_SYS_MONITOR_LEN 0x00040000 |
14d0a02a | 141 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 142 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) |
53dd6ce4 | 143 | |
6d0f6bcf | 144 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
53dd6ce4 | 145 | |
6d0f6bcf | 146 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 147 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
149 | #define CONFIG_SYS_FLASH_PROTECTION | |
150 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
151 | #define CONFIG_SYS_FLASH_PROTECT_CLEAR | |
53dd6ce4 | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
154 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
53dd6ce4 | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
157 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
53dd6ce4 | 158 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
160 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
53dd6ce4 | 161 | |
9314cee6 | 162 | #define CONFIG_ENV_IS_IN_NVRAM 1 |
53dd6ce4 | 163 | #define CONFIG_ENV_OVERWRITE 1 |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE |
165 | #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR | |
0e8d1586 JCPV |
166 | #define CONFIG_ENV_SIZE 0x400 |
167 | #define CONFIG_ENV_OFFSET 0 | |
53dd6ce4 | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_NS16550 |
170 | #define CONFIG_SYS_NS16550_SERIAL | |
171 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
172 | #define CONFIG_SYS_NS16550_CLK 14745600 | |
53dd6ce4 WD |
173 | |
174 | #define CONFIG_PCI | |
175 | #define CONFIG_PCI_PNP | |
176 | ||
177 | #define CONFIG_NET_MULTI | |
178 | #define CONFIG_EEPRO100 | |
179 | #define CONFIG_EEPRO100_SROM_WRITE | |
180 | ||
6d0f6bcf | 181 | #define CONFIG_SYS_RX_ETH_BUFFER 8 |
53dd6ce4 WD |
182 | |
183 | #define CONFIG_HARD_I2C 1 | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_I2C_SPEED 400000 |
185 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
53dd6ce4 | 186 | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
188 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
189 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
190 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
53dd6ce4 WD |
191 | |
192 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
193 | ||
6d0f6bcf | 194 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
bc234c12 | 195 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 196 | # define CONFIG_SYS_CACHELINE_SHIFT 5 |
53dd6ce4 WD |
197 | #endif |
198 | ||
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_DLL_EXTEND 0x00 |
200 | #define CONFIG_SYS_PCI_HOLD_DEL 0x20 | |
201 | ||
202 | #define CONFIG_SYS_ROMNAL 15 | |
203 | #define CONFIG_SYS_ROMFAL 31 | |
204 | ||
205 | #define CONFIG_SYS_REFINT 430 | |
206 | ||
207 | #define CONFIG_SYS_DBUS_SIZE2 1 | |
208 | ||
209 | #define CONFIG_SYS_BSTOPRE 121 | |
210 | #define CONFIG_SYS_REFREC 8 | |
211 | #define CONFIG_SYS_RDLAT 4 | |
212 | #define CONFIG_SYS_PRETOACT 3 | |
213 | #define CONFIG_SYS_ACTTOPRE 5 | |
214 | #define CONFIG_SYS_ACTORW 3 | |
215 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 | |
216 | #define CONFIG_SYS_SDMODE_WRAP 0 | |
217 | ||
218 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 | |
219 | #define CONFIG_SYS_EXTROM 1 | |
220 | #define CONFIG_SYS_REGDIMM 0 | |
221 | ||
222 | #define CONFIG_SYS_BANK0_START 0x00000000 | |
223 | #define CONFIG_SYS_BANK0_END (0x4000000 - 1) | |
224 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
225 | #define CONFIG_SYS_BANK1_START 0x04000000 | |
226 | #define CONFIG_SYS_BANK1_END (0x8000000 - 1) | |
227 | #define CONFIG_SYS_BANK1_ENABLE 1 | |
228 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
229 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
230 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
231 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
232 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
233 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
234 | #define CONFIG_SYS_BANK4_START 0x00000000 | |
235 | #define CONFIG_SYS_BANK4_END 0x00000000 | |
236 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
237 | #define CONFIG_SYS_BANK5_START 0x00000000 | |
238 | #define CONFIG_SYS_BANK5_END 0x00000000 | |
239 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
240 | #define CONFIG_SYS_BANK6_START 0x00000000 | |
241 | #define CONFIG_SYS_BANK6_END 0x00000000 | |
242 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
243 | #define CONFIG_SYS_BANK7_START 0x00000000 | |
244 | #define CONFIG_SYS_BANK7_END 0x00000000 | |
245 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
246 | ||
247 | #define CONFIG_SYS_BANK_ENABLE 0x03 | |
248 | ||
249 | #define CONFIG_SYS_ODCR 0x75 | |
250 | #define CONFIG_SYS_PGMAX 0x32 | |
251 | ||
252 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
253 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
254 | ||
255 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) | |
256 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
257 | ||
258 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
259 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
260 | ||
261 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
262 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
263 | ||
264 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
265 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
266 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
267 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
268 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
269 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
270 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
271 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
53dd6ce4 WD |
272 | |
273 | #define BOOTFLAG_COLD 0x01 | |
274 | #define BOOTFLAG_WARM 0x02 | |
275 | ||
276 | #endif /* __CONFIG_H */ |