[J-u-boot.git] / drivers / clk / sunxi / clk_a64.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018 Amarula Solutions.
 * Author: Jagan Teki <[email protected]>
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <clk/sunxi.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
#include <linux/bitops.h>

static const struct ccu_clk_gate a64_gates[] = {
	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),

	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),

	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),

	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
};

static const struct ccu_reset a64_resets[] = {
	[RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),

	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
	[RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
	[RST_BUS_EHCI0]         = RESET(0x2c0, BIT(24)),
	[RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),

	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
};

static const struct ccu_desc a64_ccu_desc = {
	.gates = a64_gates,
	.resets = a64_resets,
};

static int a64_clk_bind(struct udevice *dev)
{
	return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
}

static const struct udevice_id a64_ccu_ids[] = {
	{ .compatible = "allwinner,sun50i-a64-ccu",
	  .data = (ulong)&a64_ccu_desc },
	{ }
};

U_BOOT_DRIVER(clk_sun50i_a64) = {
	.name		= "sun50i_a64_ccu",
	.id		= UCLASS_CLK,
	.of_match	= a64_ccu_ids,
	.priv_auto	= sizeof(struct ccu_priv),
	.ops		= &sunxi_clk_ops,
	.probe		= sunxi_clk_probe,
	.bind		= a64_clk_bind,
};
Commit	Line	Data
0d47bc70 JT	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018 Amarula Solutions.
	4	* Author: Jagan Teki <[email protected]>
	5	*/
	6
	7	#include <common.h>
	8	#include <clk-uclass.h>
	9	#include <dm.h>
	10	#include <errno.h>
21d314a6	11	#include <clk/sunxi.h>
0d47bc70	12	#include <dt-bindings/clock/sun50i-a64-ccu.h>
99ba4308	13	#include <dt-bindings/reset/sun50i-a64-ccu.h>
cd93d625	14	#include <linux/bitops.h>
0d47bc70 JT	15
0d47bc70 JT	16	static const struct ccu_clk_gate a64_gates[] = {
bb3e5aa2 AP	17	[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
	18	[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
	19	[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
68620c96	20	[CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
82111469 JT	21	[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
82111469 JT	22	[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
0d47bc70 JT	23	[CLK_BUS_OTG] = GATE(0x060, BIT(23)),
	24	[CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
	25	[CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
	26	[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
	27	[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
	28
c61897bf SH	29	[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
	30	[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
	31	[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
4acc7119 JT	32	[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
	33	[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
	34	[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
	35	[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
	36	[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
	37
82111469 JT	38	[CLK_SPI0] = GATE(0x0a0, BIT(31)),
	39	[CLK_SPI1] = GATE(0x0a4, BIT(31)),
	40
0d47bc70 JT	41	[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
	42	[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
	43	[CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
	44	[CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
	45	[CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
	46	[CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
	47	};
	48
99ba4308 JT	49	static const struct ccu_reset a64_resets[] = {
	50	[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
	51	[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
	52	[RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
	53
bb3e5aa2 AP	54	[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
	55	[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
	56	[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
68620c96	57	[RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
82111469 JT	58	[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
82111469 JT	59	[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
99ba4308 JT	60	[RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
	61	[RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
	62	[RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
	63	[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
	64	[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
8606f960	65
c61897bf SH	66	[RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
	67	[RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
	68	[RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
8606f960 JT	69	[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
	70	[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
	71	[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
	72	[RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
	73	[RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
99ba4308 JT	74	};
99ba4308 JT	75
0d47bc70 JT	76	static const struct ccu_desc a64_ccu_desc = {
0d47bc70 JT	77	.gates = a64_gates,
99ba4308	78	.resets = a64_resets,
0d47bc70 JT	79	};
0d47bc70 JT	80
99ba4308 JT	81	static int a64_clk_bind(struct udevice *dev)
	82	{
	83	return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
	84	}
	85
0d47bc70 JT	86	static const struct udevice_id a64_ccu_ids[] = {
	87	{ .compatible = "allwinner,sun50i-a64-ccu",
	88	.data = (ulong)&a64_ccu_desc },
	89	{ }
	90	};
	91
	92	U_BOOT_DRIVER(clk_sun50i_a64) = {
	93	.name = "sun50i_a64_ccu",
	94	.id = UCLASS_CLK,
	95	.of_match = a64_ccu_ids,
41575d8e	96	.priv_auto = sizeof(struct ccu_priv),
0d47bc70 JT	97	.ops = &sunxi_clk_ops,
0d47bc70 JT	98	.probe = sunxi_clk_probe,
99ba4308	99	.bind = a64_clk_bind,
0d47bc70	100	};