[J-u-boot.git] / drivers / fpga / spartan2.c

/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>		/* core U-Boot definitions */
#include <spartan2.h>		/* Spartan-II device family */

/* Define FPGA_DEBUG to get debug printf's */
#ifdef	FPGA_DEBUG
#define PRINTF(fmt,args...)	printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif

#undef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK

/* Note: The assumption is that we cannot possibly run fast enough to
 * overrun the device (the Slave Parallel mode can free run at 50MHz).
 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
 * the board config file to slow things down.
 */
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif

#ifndef CONFIG_SYS_FPGA_WAIT
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
#endif

static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* static int spartan2_sp_info(xilinx_desc *desc ); */

static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
/* static int spartan2_ss_info(xilinx_desc *desc ); */

/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
			 bitstream_type bstype)
{
	int ret_val = FPGA_FAIL;

	switch (desc->iface) {
	case slave_serial:
		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
		ret_val = spartan2_ss_load(desc, buf, bsize);
		break;

	case slave_parallel:
		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
		ret_val = spartan2_sp_load(desc, buf, bsize);
		break;

	default:
		printf ("%s: Unsupported interface type, %d\n",
				__FUNCTION__, desc->iface);
	}

	return ret_val;
}

static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;

	switch (desc->iface) {
	case slave_serial:
		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
		ret_val = spartan2_ss_dump(desc, buf, bsize);
		break;

	case slave_parallel:
		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
		ret_val = spartan2_sp_dump(desc, buf, bsize);
		break;

	default:
		printf ("%s: Unsupported interface type, %d\n",
				__FUNCTION__, desc->iface);
	}

	return ret_val;
}

static int spartan2_info(xilinx_desc *desc)
{
	return FPGA_SUCCESS;
}


/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */

static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;	/* assume the worst */
	xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;

	PRINTF ("%s: start with interface functions @ 0x%p\n",
			__FUNCTION__, fn);

	if (fn) {
		size_t bytecount = 0;
		unsigned char *data = (unsigned char *) buf;
		int cookie = desc->cookie;	/* make a local copy */
		unsigned long ts;		/* timestamp */

		PRINTF ("%s: Function Table:\n"
				"ptr:\t0x%p\n"
				"struct: 0x%p\n"
				"pre: 0x%p\n"
				"pgm:\t0x%p\n"
				"init:\t0x%p\n"
				"err:\t0x%p\n"
				"clk:\t0x%p\n"
				"cs:\t0x%p\n"
				"wr:\t0x%p\n"
				"read data:\t0x%p\n"
				"write data:\t0x%p\n"
				"busy:\t0x%p\n"
				"abort:\t0x%p\n",
				"post:\t0x%p\n\n",
				__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
				fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
				fn->abort, fn->post);

		/*
		 * This code is designed to emulate the "Express Style"
		 * Continuous Data Loading in Slave Parallel Mode for
		 * the Spartan-II Family.
		 */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
		printf ("Loading FPGA Device %d...\n", cookie);
#endif
		/*
		 * Run the pre configuration function if there is one.
		 */
		if (*fn->pre) {
			(*fn->pre) (cookie);
		}

		/* Establish the initial state */
		(*fn->pgm) (true, true, cookie);	/* Assert the program, commit */

		/* Get ready for the burn */
		CONFIG_FPGA_DELAY ();
		(*fn->pgm) (false, true, cookie);	/* Deassert the program, commit */

		ts = get_timer (0);		/* get current time */
		/* Now wait for INIT and BUSY to go high */
		do {
			CONFIG_FPGA_DELAY ();
			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for INIT to clear.\n");
				(*fn->abort) (cookie);	/* abort the burn */
				return FPGA_FAIL;
			}
		} while ((*fn->init) (cookie) && (*fn->busy) (cookie));

		(*fn->wr) (true, true, cookie); /* Assert write, commit */
		(*fn->cs) (true, true, cookie); /* Assert chip select, commit */
		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */

		/* Load the data */
		while (bytecount < bsize) {
			/* XXX - do we check for an Ctrl-C press in here ??? */
			/* XXX - Check the error bit? */

			(*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
			CONFIG_FPGA_DELAY ();
			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
			CONFIG_FPGA_DELAY ();
			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */

#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
			ts = get_timer (0);	/* get current time */
			while ((*fn->busy) (cookie)) {
				/* XXX - we should have a check in here somewhere to
				 * make sure we aren't busy forever... */

				CONFIG_FPGA_DELAY ();
				(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
				CONFIG_FPGA_DELAY ();
				(*fn->clk) (true, true, cookie);	/* Assert the clock pin */

				if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
					puts ("** Timeout waiting for BUSY to clear.\n");
					(*fn->abort) (cookie);	/* abort the burn */
					return FPGA_FAIL;
				}
			}
#endif

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
			if (bytecount % (bsize / 40) == 0)
				putc ('.');		/* let them know we are alive */
#endif
		}

		CONFIG_FPGA_DELAY ();
		(*fn->cs) (false, true, cookie);	/* Deassert the chip select */
		(*fn->wr) (false, true, cookie);	/* Deassert the write pin */

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
		putc ('\n');			/* terminate the dotted line */
#endif

		/* now check for done signal */
		ts = get_timer (0);		/* get current time */
		ret_val = FPGA_SUCCESS;
		while ((*fn->done) (cookie) == FPGA_FAIL) {

			CONFIG_FPGA_DELAY ();
			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
			CONFIG_FPGA_DELAY ();
			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */

			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for DONE to clear.\n");
				(*fn->abort) (cookie);	/* abort the burn */
				ret_val = FPGA_FAIL;
				break;
			}
		}

		/*
		 * Run the post configuration function if there is one.
		 */
		if (*fn->post)
			(*fn->post) (cookie);

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
		if (ret_val == FPGA_SUCCESS)
			puts ("Done.\n");
		else
			puts ("Fail.\n");
#endif

	} else {
		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	}

	return ret_val;
}

static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;	/* assume the worst */
	xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;

	if (fn) {
		unsigned char *data = (unsigned char *) buf;
		size_t bytecount = 0;
		int cookie = desc->cookie;	/* make a local copy */

		printf ("Starting Dump of FPGA Device %d...\n", cookie);

		(*fn->cs) (true, true, cookie); /* Assert chip select, commit */
		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */

		/* dump the data */
		while (bytecount < bsize) {
			/* XXX - do we check for an Ctrl-C press in here ??? */

			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
			(*fn->rdata) (&(data[bytecount++]), cookie);	/* read the data */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
			if (bytecount % (bsize / 40) == 0)
				putc ('.');		/* let them know we are alive */
#endif
		}

		(*fn->cs) (false, false, cookie);	/* Deassert the chip select */
		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
		putc ('\n');			/* terminate the dotted line */
#endif
		puts ("Done.\n");

		/* XXX - checksum the data? */
	} else {
		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	}

	return ret_val;
}


/* ------------------------------------------------------------------------- */

static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;	/* assume the worst */
	xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
	int i;
	unsigned char val;

	PRINTF ("%s: start with interface functions @ 0x%p\n",
			__FUNCTION__, fn);

	if (fn) {
		size_t bytecount = 0;
		unsigned char *data = (unsigned char *) buf;
		int cookie = desc->cookie;	/* make a local copy */
		unsigned long ts;		/* timestamp */

		PRINTF ("%s: Function Table:\n"
				"ptr:\t0x%p\n"
				"struct: 0x%p\n"
				"pgm:\t0x%p\n"
				"init:\t0x%p\n"
				"clk:\t0x%p\n"
				"wr:\t0x%p\n"
				"done:\t0x%p\n\n",
				__FUNCTION__, &fn, fn, fn->pgm, fn->init,
				fn->clk, fn->wr, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
		printf ("Loading FPGA Device %d...\n", cookie);
#endif

		/*
		 * Run the pre configuration function if there is one.
		 */
		if (*fn->pre) {
			(*fn->pre) (cookie);
		}

		/* Establish the initial state */
		(*fn->pgm) (true, true, cookie);	/* Assert the program, commit */

		/* Wait for INIT state (init low)                            */
		ts = get_timer (0);		/* get current time */
		do {
			CONFIG_FPGA_DELAY ();
			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for INIT to start.\n");
				return FPGA_FAIL;
			}
		} while (!(*fn->init) (cookie));

		/* Get ready for the burn */
		CONFIG_FPGA_DELAY ();
		(*fn->pgm) (false, true, cookie);	/* Deassert the program, commit */

		ts = get_timer (0);		/* get current time */
		/* Now wait for INIT to go high */
		do {
			CONFIG_FPGA_DELAY ();
			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for INIT to clear.\n");
				return FPGA_FAIL;
			}
		} while ((*fn->init) (cookie));

		/* Load the data */
		while (bytecount < bsize) {

			/* Xilinx detects an error if INIT goes low (active)
			   while DONE is low (inactive) */
			if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
				puts ("** CRC error during FPGA load.\n");
				return (FPGA_FAIL);
			}
			val = data [bytecount ++];
			i = 8;
			do {
				/* Deassert the clock */
				(*fn->clk) (false, true, cookie);
				CONFIG_FPGA_DELAY ();
				/* Write data */
				(*fn->wr) ((val & 0x80), true, cookie);
				CONFIG_FPGA_DELAY ();
				/* Assert the clock */
				(*fn->clk) (true, true, cookie);
				CONFIG_FPGA_DELAY ();
				val <<= 1;
				i --;
			} while (i > 0);

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
			if (bytecount % (bsize / 40) == 0)
				putc ('.');		/* let them know we are alive */
#endif
		}

		CONFIG_FPGA_DELAY ();

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
		putc ('\n');			/* terminate the dotted line */
#endif

		/* now check for done signal */
		ts = get_timer (0);		/* get current time */
		ret_val = FPGA_SUCCESS;
		(*fn->wr) (true, true, cookie);

		while (! (*fn->done) (cookie)) {

			CONFIG_FPGA_DELAY ();
			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
			CONFIG_FPGA_DELAY ();
			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */

			putc ('*');

			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for DONE to clear.\n");
				ret_val = FPGA_FAIL;
				break;
			}
		}
		putc ('\n');			/* terminate the dotted line */

		/*
		 * Run the post configuration function if there is one.
		 */
		if (*fn->post)
			(*fn->post) (cookie);

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
		if (ret_val == FPGA_SUCCESS)
			puts ("Done.\n");
		else
			puts ("Fail.\n");
#endif

	} else {
		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	}

	return ret_val;
}

static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
	/* Readback is only available through the Slave Parallel and         */
	/* boundary-scan interfaces.                                         */
	printf ("%s: Slave Serial Dumping is unavailable\n",
			__FUNCTION__);
	return FPGA_FAIL;
}

struct xilinx_fpga_op spartan2_op = {
	.load = spartan2_load,
	.dump = spartan2_dump,
	.info = spartan2_info,
};
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2002
	3	* Rich Ireland, Enterasys Networks, [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
e2211743 WD	6	*/
	7
	8	#include <common.h> /* core U-Boot definitions */
	9	#include <spartan2.h> /* Spartan-II device family */
	10
e2211743 WD	11	/* Define FPGA_DEBUG to get debug printf's */
	12	#ifdef FPGA_DEBUG
	13	#define PRINTF(fmt,args...) printf (fmt ,##args)
	14	#else
	15	#define PRINTF(fmt,args...)
	16	#endif
	17
6d0f6bcf JCPV	18	#undef CONFIG_SYS_FPGA_CHECK_BUSY
6d0f6bcf JCPV	19	#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
e2211743 WD	20
	21	/* Note: The assumption is that we cannot possibly run fast enough to
	22	* overrun the device (the Slave Parallel mode can free run at 50MHz).
	23	* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
	24	* the board config file to slow things down.
	25	*/
	26	#ifndef CONFIG_FPGA_DELAY
	27	#define CONFIG_FPGA_DELAY()
	28	#endif
	29
6d0f6bcf JCPV	30	#ifndef CONFIG_SYS_FPGA_WAIT
6d0f6bcf JCPV	31	#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
e2211743 WD	32	#endif
e2211743 WD	33
f8c1be98 MS	34	static int spartan2_sp_load(xilinx_desc desc, const void buf, size_t bsize);
	35	static int spartan2_sp_dump(xilinx_desc desc, const void buf, size_t bsize);
	36	/* static int spartan2_sp_info(xilinx_desc desc ); /
e2211743	37
f8c1be98 MS	38	static int spartan2_ss_load(xilinx_desc desc, const void buf, size_t bsize);
	39	static int spartan2_ss_dump(xilinx_desc desc, const void buf, size_t bsize);
	40	/* static int spartan2_ss_info(xilinx_desc desc ); /
e2211743 WD	41
	42	/* ------------------------------------------------------------------------- */
	43	/* Spartan-II Generic Implementation */
7a78bd26 MS	44	static int spartan2_load(xilinx_desc desc, const void buf, size_t bsize,
7a78bd26 MS	45	bitstream_type bstype)
e2211743 WD	46	{
	47	int ret_val = FPGA_FAIL;
	48
	49	switch (desc->iface) {
	50	case slave_serial:
	51	PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
b625b9ae	52	ret_val = spartan2_ss_load(desc, buf, bsize);
e2211743 WD	53	break;
	54
	55	case slave_parallel:
	56	PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
b625b9ae	57	ret_val = spartan2_sp_load(desc, buf, bsize);
e2211743 WD	58	break;
	59
	60	default:
	61	printf ("%s: Unsupported interface type, %d\n",
	62	__FUNCTION__, desc->iface);
	63	}
	64
	65	return ret_val;
	66	}
	67
14cfc4f3	68	static int spartan2_dump(xilinx_desc desc, const void buf, size_t bsize)
e2211743 WD	69	{
	70	int ret_val = FPGA_FAIL;
	71
	72	switch (desc->iface) {
	73	case slave_serial:
	74	PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
b625b9ae	75	ret_val = spartan2_ss_dump(desc, buf, bsize);
e2211743 WD	76	break;
	77
	78	case slave_parallel:
	79	PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
b625b9ae	80	ret_val = spartan2_sp_dump(desc, buf, bsize);
e2211743 WD	81	break;
	82
	83	default:
	84	printf ("%s: Unsupported interface type, %d\n",
	85	__FUNCTION__, desc->iface);
	86	}
	87
	88	return ret_val;
	89	}
	90
14cfc4f3	91	static int spartan2_info(xilinx_desc *desc)
e2211743 WD	92	{
	93	return FPGA_SUCCESS;
	94	}
	95
	96
e2211743 WD	97	/* ------------------------------------------------------------------------- */
	98	/* Spartan-II Slave Parallel Generic Implementation */
	99
f8c1be98	100	static int spartan2_sp_load(xilinx_desc desc, const void buf, size_t bsize)
e2211743 WD	101	{
e2211743 WD	102	int ret_val = FPGA_FAIL; /* assume the worst */
b625b9ae	103	xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
e2211743 WD	104
	105	PRINTF ("%s: start with interface functions @ 0x%p\n",
	106	__FUNCTION__, fn);
	107
	108	if (fn) {
	109	size_t bytecount = 0;
	110	unsigned char data = (unsigned char ) buf;
	111	int cookie = desc->cookie; /* make a local copy */
	112	unsigned long ts; /* timestamp */
	113
	114	PRINTF ("%s: Function Table:\n"
	115	"ptr:\t0x%p\n"
	116	"struct: 0x%p\n"
	117	"pre: 0x%p\n"
	118	"pgm:\t0x%p\n"
	119	"init:\t0x%p\n"
	120	"err:\t0x%p\n"
	121	"clk:\t0x%p\n"
	122	"cs:\t0x%p\n"
	123	"wr:\t0x%p\n"
	124	"read data:\t0x%p\n"
	125	"write data:\t0x%p\n"
	126	"busy:\t0x%p\n"
	127	"abort:\t0x%p\n",
	128	"post:\t0x%p\n\n",
	129	__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
	130	fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
	131	fn->abort, fn->post);
	132
	133	/*
	134	* This code is designed to emulate the "Express Style"
	135	* Continuous Data Loading in Slave Parallel Mode for
	136	* the Spartan-II Family.
	137	*/
6d0f6bcf	138	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
e2211743 WD	139	printf ("Loading FPGA Device %d...\n", cookie);
	140	#endif
	141	/*
	142	* Run the pre configuration function if there is one.
	143	*/
	144	if (*fn->pre) {
	145	(*fn->pre) (cookie);
	146	}
	147
	148	/* Establish the initial state */
472d5460	149	(fn->pgm) (true, true, cookie); / Assert the program, commit */
e2211743 WD	150
	151	/* Get ready for the burn */
	152	CONFIG_FPGA_DELAY ();
472d5460	153	(fn->pgm) (false, true, cookie); / Deassert the program, commit */
e2211743 WD	154
	155	ts = get_timer (0); /* get current time */
	156	/* Now wait for INIT and BUSY to go high */
	157	do {
	158	CONFIG_FPGA_DELAY ();
6d0f6bcf	159	if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
e2211743 WD	160	puts ("** Timeout waiting for INIT to clear.\n");
	161	(fn->abort) (cookie); / abort the burn */
	162	return FPGA_FAIL;
	163	}
	164	} while ((fn->init) (cookie) && (fn->busy) (cookie));
	165
472d5460 YS	166	(fn->wr) (true, true, cookie); / Assert write, commit */
	167	(fn->cs) (true, true, cookie); / Assert chip select, commit */
	168	(fn->clk) (true, true, cookie); / Assert the clock pin */
e2211743 WD	169
	170	/* Load the data */
	171	while (bytecount < bsize) {
	172	/* XXX - do we check for an Ctrl-C press in here ??? */
	173	/* XXX - Check the error bit? */
	174
472d5460	175	(fn->wdata) (data[bytecount++], true, cookie); / write the data */
e2211743	176	CONFIG_FPGA_DELAY ();
472d5460	177	(fn->clk) (false, true, cookie); / Deassert the clock pin */
e2211743	178	CONFIG_FPGA_DELAY ();
472d5460	179	(fn->clk) (true, true, cookie); / Assert the clock pin */
e2211743	180
6d0f6bcf	181	#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
e2211743 WD	182	ts = get_timer (0); /* get current time */
	183	while ((*fn->busy) (cookie)) {
	184	/* XXX - we should have a check in here somewhere to
	185	* make sure we aren't busy forever... */
	186
	187	CONFIG_FPGA_DELAY ();
472d5460	188	(fn->clk) (false, true, cookie); / Deassert the clock pin */
e2211743	189	CONFIG_FPGA_DELAY ();
472d5460	190	(fn->clk) (true, true, cookie); / Assert the clock pin */
e2211743	191
6d0f6bcf	192	if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
e2211743 WD	193	puts ("** Timeout waiting for BUSY to clear.\n");
	194	(fn->abort) (cookie); / abort the burn */
	195	return FPGA_FAIL;
	196	}
	197	}
	198	#endif
	199
6d0f6bcf	200	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
e2211743 WD	201	if (bytecount % (bsize / 40) == 0)
	202	putc ('.'); /* let them know we are alive */
	203	#endif
	204	}
	205
	206	CONFIG_FPGA_DELAY ();
472d5460 YS	207	(fn->cs) (false, true, cookie); / Deassert the chip select */
472d5460 YS	208	(fn->wr) (false, true, cookie); / Deassert the write pin */
e2211743	209
6d0f6bcf	210	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
e2211743 WD	211	putc ('\n'); /* terminate the dotted line */
	212	#endif
	213
	214	/* now check for done signal */
	215	ts = get_timer (0); /* get current time */
	216	ret_val = FPGA_SUCCESS;
	217	while ((*fn->done) (cookie) == FPGA_FAIL) {
e2211743 WD	218
e2211743 WD	219	CONFIG_FPGA_DELAY ();
472d5460	220	(fn->clk) (false, true, cookie); / Deassert the clock pin */
e2211743	221	CONFIG_FPGA_DELAY ();
472d5460	222	(fn->clk) (true, true, cookie); / Assert the clock pin */
e2211743	223
6d0f6bcf	224	if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
e2211743 WD	225	puts ("** Timeout waiting for DONE to clear.\n");
	226	(fn->abort) (cookie); / abort the burn */
	227	ret_val = FPGA_FAIL;
	228	break;
	229	}
	230	}
	231
e2211743 WD	232	/*
	233	* Run the post configuration function if there is one.
	234	*/
3818b677	235	if (*fn->post)
e2211743	236	(*fn->post) (cookie);
e2211743	237
6d0f6bcf	238	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
3818b677 MF	239	if (ret_val == FPGA_SUCCESS)
	240	puts ("Done.\n");
	241	else
e2211743 WD	242	puts ("Fail.\n");
e2211743 WD	243	#endif
e2211743 WD	244
	245	} else {
	246	printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	247	}
	248
	249	return ret_val;
	250	}
	251
f8c1be98	252	static int spartan2_sp_dump(xilinx_desc desc, const void buf, size_t bsize)
e2211743 WD	253	{
e2211743 WD	254	int ret_val = FPGA_FAIL; /* assume the worst */
b625b9ae	255	xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
e2211743 WD	256
	257	if (fn) {
	258	unsigned char data = (unsigned char ) buf;
	259	size_t bytecount = 0;
	260	int cookie = desc->cookie; /* make a local copy */
	261
	262	printf ("Starting Dump of FPGA Device %d...\n", cookie);
	263
472d5460 YS	264	(fn->cs) (true, true, cookie); / Assert chip select, commit */
472d5460 YS	265	(fn->clk) (true, true, cookie); / Assert the clock pin */
e2211743 WD	266
	267	/* dump the data */
	268	while (bytecount < bsize) {
	269	/* XXX - do we check for an Ctrl-C press in here ??? */
	270
472d5460 YS	271	(fn->clk) (false, true, cookie); / Deassert the clock pin */
472d5460 YS	272	(fn->clk) (true, true, cookie); / Assert the clock pin */
e2211743	273	(fn->rdata) (&(data[bytecount++]), cookie); / read the data */
6d0f6bcf	274	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
e2211743 WD	275	if (bytecount % (bsize / 40) == 0)
	276	putc ('.'); /* let them know we are alive */
	277	#endif
	278	}
	279
472d5460 YS	280	(fn->cs) (false, false, cookie); / Deassert the chip select */
	281	(fn->clk) (false, true, cookie); / Deassert the clock pin */
	282	(fn->clk) (true, true, cookie); / Assert the clock pin */
e2211743	283
6d0f6bcf	284	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
e2211743 WD	285	putc ('\n'); /* terminate the dotted line */
	286	#endif
	287	puts ("Done.\n");
	288
	289	/* XXX - checksum the data? */
	290	} else {
	291	printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	292	}
	293
	294	return ret_val;
	295	}
	296
	297
e2211743 WD	298	/* ------------------------------------------------------------------------- */
e2211743 WD	299
f8c1be98	300	static int spartan2_ss_load(xilinx_desc desc, const void buf, size_t bsize)
e2211743	301	{
8bde7f77	302	int ret_val = FPGA_FAIL; /* assume the worst */
b625b9ae	303	xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
8bde7f77	304	int i;
437fc732	305	unsigned char val;
8bde7f77	306
7f6c2cbc WD	307	PRINTF ("%s: start with interface functions @ 0x%p\n",
	308	__FUNCTION__, fn);
	309
	310	if (fn) {
	311	size_t bytecount = 0;
	312	unsigned char data = (unsigned char ) buf;
	313	int cookie = desc->cookie; /* make a local copy */
	314	unsigned long ts; /* timestamp */
	315
	316	PRINTF ("%s: Function Table:\n"
	317	"ptr:\t0x%p\n"
	318	"struct: 0x%p\n"
	319	"pgm:\t0x%p\n"
	320	"init:\t0x%p\n"
	321	"clk:\t0x%p\n"
	322	"wr:\t0x%p\n"
	323	"done:\t0x%p\n\n",
8bde7f77 WD	324	__FUNCTION__, &fn, fn, fn->pgm, fn->init,
8bde7f77 WD	325	fn->clk, fn->wr, fn->done);
6d0f6bcf	326	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
7f6c2cbc WD	327	printf ("Loading FPGA Device %d...\n", cookie);
	328	#endif
	329
	330	/*
	331	* Run the pre configuration function if there is one.
	332	*/
	333	if (*fn->pre) {
	334	(*fn->pre) (cookie);
	335	}
	336
	337	/* Establish the initial state */
472d5460	338	(fn->pgm) (true, true, cookie); / Assert the program, commit */
7f6c2cbc	339
8bde7f77	340	/* Wait for INIT state (init low) */
7f6c2cbc WD	341	ts = get_timer (0); /* get current time */
	342	do {
	343	CONFIG_FPGA_DELAY ();
6d0f6bcf	344	if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
7f6c2cbc WD	345	puts ("** Timeout waiting for INIT to start.\n");
	346	return FPGA_FAIL;
	347	}
	348	} while (!(*fn->init) (cookie));
8bde7f77	349
7f6c2cbc WD	350	/* Get ready for the burn */
7f6c2cbc WD	351	CONFIG_FPGA_DELAY ();
472d5460	352	(fn->pgm) (false, true, cookie); / Deassert the program, commit */
7f6c2cbc WD	353
	354	ts = get_timer (0); /* get current time */
	355	/* Now wait for INIT to go high */
	356	do {
	357	CONFIG_FPGA_DELAY ();
6d0f6bcf	358	if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
7f6c2cbc WD	359	puts ("** Timeout waiting for INIT to clear.\n");
	360	return FPGA_FAIL;
	361	}
	362	} while ((*fn->init) (cookie));
	363
	364	/* Load the data */
	365	while (bytecount < bsize) {
8bde7f77 WD	366
	367	/* Xilinx detects an error if INIT goes low (active)
	368	while DONE is low (inactive) */
	369	if ((fn->done) (cookie) == 0 && (fn->init) (cookie)) {
	370	puts ("** CRC error during FPGA load.\n");
	371	return (FPGA_FAIL);
	372	}
	373	val = data [bytecount ++];
	374	i = 8;
	375	do {
	376	/* Deassert the clock */
472d5460	377	(*fn->clk) (false, true, cookie);
8bde7f77 WD	378	CONFIG_FPGA_DELAY ();
8bde7f77 WD	379	/* Write data */
472d5460	380	(*fn->wr) ((val & 0x80), true, cookie);
8bde7f77 WD	381	CONFIG_FPGA_DELAY ();
8bde7f77 WD	382	/* Assert the clock */
472d5460	383	(*fn->clk) (true, true, cookie);
8bde7f77 WD	384	CONFIG_FPGA_DELAY ();
	385	val <<= 1;
	386	i --;
	387	} while (i > 0);
	388
6d0f6bcf	389	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
7f6c2cbc WD	390	if (bytecount % (bsize / 40) == 0)
	391	putc ('.'); /* let them know we are alive */
	392	#endif
	393	}
	394
	395	CONFIG_FPGA_DELAY ();
	396
6d0f6bcf	397	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
7f6c2cbc WD	398	putc ('\n'); /* terminate the dotted line */
	399	#endif
	400
	401	/* now check for done signal */
	402	ts = get_timer (0); /* get current time */
	403	ret_val = FPGA_SUCCESS;
472d5460	404	(*fn->wr) (true, true, cookie);
7f6c2cbc WD	405
7f6c2cbc WD	406	while (! (*fn->done) (cookie)) {
7f6c2cbc WD	407
7f6c2cbc WD	408	CONFIG_FPGA_DELAY ();
472d5460	409	(fn->clk) (false, true, cookie); / Deassert the clock pin */
7f6c2cbc	410	CONFIG_FPGA_DELAY ();
472d5460	411	(fn->clk) (true, true, cookie); / Assert the clock pin */
7f6c2cbc	412
8bde7f77 WD	413	putc ('*');
8bde7f77 WD	414
6d0f6bcf	415	if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
7f6c2cbc WD	416	puts ("** Timeout waiting for DONE to clear.\n");
	417	ret_val = FPGA_FAIL;
	418	break;
	419	}
	420	}
	421	putc ('\n'); /* terminate the dotted line */
	422
21d39d59 MF	423	/*
	424	* Run the post configuration function if there is one.
	425	*/
3818b677	426	if (*fn->post)
21d39d59	427	(*fn->post) (cookie);
21d39d59	428
6d0f6bcf	429	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
3818b677	430	if (ret_val == FPGA_SUCCESS)
7f6c2cbc	431	puts ("Done.\n");
3818b677	432	else
7f6c2cbc	433	puts ("Fail.\n");
7f6c2cbc WD	434	#endif
	435
	436	} else {
	437	printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	438	}
	439
	440	return ret_val;
e2211743 WD	441	}
e2211743 WD	442
f8c1be98	443	static int spartan2_ss_dump(xilinx_desc desc, const void buf, size_t bsize)
e2211743	444	{
8bde7f77 WD	445	/* Readback is only available through the Slave Parallel and */
8bde7f77 WD	446	/* boundary-scan interfaces. */
7f6c2cbc	447	printf ("%s: Slave Serial Dumping is unavailable\n",
e2211743 WD	448	__FUNCTION__);
	449	return FPGA_FAIL;
	450	}
14cfc4f3 MS	451
	452	struct xilinx_fpga_op spartan2_op = {
	453	.load = spartan2_load,
	454	.dump = spartan2_dump,
	455	.info = spartan2_info,
	456	};