[J-u-boot.git] / cpu / mpc85xx / tlb.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

void set_tlb(u8 tlb, u32 epn, u64 rpn,
	     u8 perms, u8 wimge,
	     u8 ts, u8 esel, u8 tsize, u8 iprot)
{
	u32 _mas0, _mas1, _mas2, _mas3, _mas7;

	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
	_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
	_mas7 = rpn >> 32;

	mtspr(MAS0, _mas0);
	mtspr(MAS1, _mas1);
	mtspr(MAS2, _mas2);
	mtspr(MAS3, _mas3);
#ifdef CONFIG_ENABLE_36BIT_PHYS
	mtspr(MAS7, _mas7);
#endif
	asm volatile("isync;msync;tlbwe;isync");

#ifdef CONFIG_ADDR_MAP
	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
#endif
}

void disable_tlb(u8 esel)
{
	u32 _mas0, _mas1, _mas2, _mas3, _mas7;

	_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
	_mas1 = 0;
	_mas2 = 0;
	_mas3 = 0;
	_mas7 = 0;

	mtspr(MAS0, _mas0);
	mtspr(MAS1, _mas1);
	mtspr(MAS2, _mas2);
	mtspr(MAS3, _mas3);
#ifdef CONFIG_ENABLE_36BIT_PHYS
	mtspr(MAS7, _mas7);
#endif
	asm volatile("isync;msync;tlbwe;isync");

#ifdef CONFIG_ADDR_MAP
	if (gd->flags & GD_FLG_RELOC)
		addrmap_set_entry(0, 0, 0, esel);
#endif
}

void invalidate_tlb(u8 tlb)
{
	if (tlb == 0)
		mtspr(MMUCSR0, 0x4);
	if (tlb == 1)
		mtspr(MMUCSR0, 0x2);
}

void init_tlbs(void)
{
	int i;

	for (i = 0; i < num_tlb_entries; i++) {
		set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
			tlb_table[i].perms, tlb_table[i].wimge,
			tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
			tlb_table[i].iprot);
	}

	return ;
}

#ifdef CONFIG_ADDR_MAP
void init_addr_map(void)
{
	int i;
	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;

	/* walk all the entries */
	for (i = 0; i < max_cam; i++) {
		unsigned long epn;
		u32 tsize, _mas1;
		phys_addr_t rpn;

		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));

		asm volatile("tlbre;isync");
		_mas1 = mfspr(MAS1);

		/* if the entry isn't valid skip it */
		if (!(_mas1 & MAS1_VALID))
			continue;

		tsize = (_mas1 >> 8) & 0xf;
		epn = mfspr(MAS2) & MAS2_EPN;
		rpn = mfspr(MAS3) & MAS3_RPN;
#ifdef CONFIG_ENABLE_36BIT_PHYS
		rpn |= ((phys_addr_t)mfspr(MAS7)) << 32;
#endif

		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
	}

	return ;
}
#endif

#ifndef CONFIG_SYS_DDR_TLB_START
#define CONFIG_SYS_DDR_TLB_START 8
#endif

unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
	unsigned int tlb_size;
	unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
	u64 size, memsize = (u64)memsize_in_meg << 20;

	size = min(memsize, CONFIG_MAX_MEM_MAPPED);

	/* Convert (4^max) kB to (2^max) bytes */
	max_cam = max_cam * 2 + 10;

	for (; size && ram_tlb_index < 16; ram_tlb_index++) {
		u32 camsize = __ilog2_u64(size) & ~1U;
		u32 align = __ilog2(ram_tlb_address) & ~1U;

		if (align == -2) align = max_cam;
		if (camsize > align)
			camsize = align;

		if (camsize > max_cam)
			camsize = max_cam;

		tlb_size = (camsize - 10) / 2;

		set_tlb(1, ram_tlb_address, ram_tlb_address,
			MAS3_SX|MAS3_SW|MAS3_SR, 0,
			0, ram_tlb_index, tlb_size, 1);

		size -= 1ULL << camsize;
		memsize -= 1ULL << camsize;
		ram_tlb_address += 1UL << camsize;
	}

	if (memsize)
		print_size(memsize, " left unmapped\n");

	/*
	 * Confirm that the requested amount of memory was mapped.
	 */
	return memsize_in_meg;
}
Commit	Line	Data
44a23cfd KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, [email protected].
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/processor.h>
	28	#include <asm/mmu.h>
ecf5b98c KG	29	#ifdef CONFIG_ADDR_MAP
	30	#include <addr_map.h>
	31	#endif
	32
	33	DECLARE_GLOBAL_DATA_PTR;
44a23cfd KG	34
	35	void set_tlb(u8 tlb, u32 epn, u64 rpn,
	36	u8 perms, u8 wimge,
	37	u8 ts, u8 esel, u8 tsize, u8 iprot)
	38	{
	39	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
	40
	41	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
	42	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
	43	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
	44	_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
	45	_mas7 = rpn >> 32;
	46
	47	mtspr(MAS0, _mas0);
	48	mtspr(MAS1, _mas1);
	49	mtspr(MAS2, _mas2);
	50	mtspr(MAS3, _mas3);
	51	#ifdef CONFIG_ENABLE_36BIT_PHYS
	52	mtspr(MAS7, _mas7);
	53	#endif
	54	asm volatile("isync;msync;tlbwe;isync");
ecf5b98c KG	55
	56	#ifdef CONFIG_ADDR_MAP
	57	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
	58	addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
	59	#endif
44a23cfd KG	60	}
	61
	62	void disable_tlb(u8 esel)
	63	{
	64	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
	65
	66	_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
	67	_mas1 = 0;
	68	_mas2 = 0;
	69	_mas3 = 0;
	70	_mas7 = 0;
	71
	72	mtspr(MAS0, _mas0);
	73	mtspr(MAS1, _mas1);
	74	mtspr(MAS2, _mas2);
	75	mtspr(MAS3, _mas3);
	76	#ifdef CONFIG_ENABLE_36BIT_PHYS
	77	mtspr(MAS7, _mas7);
	78	#endif
	79	asm volatile("isync;msync;tlbwe;isync");
ecf5b98c KG	80
	81	#ifdef CONFIG_ADDR_MAP
	82	if (gd->flags & GD_FLG_RELOC)
	83	addrmap_set_entry(0, 0, 0, esel);
	84	#endif
44a23cfd KG	85	}
	86
	87	void invalidate_tlb(u8 tlb)
	88	{
	89	if (tlb == 0)
	90	mtspr(MMUCSR0, 0x4);
	91	if (tlb == 1)
	92	mtspr(MMUCSR0, 0x2);
	93	}
	94
	95	void init_tlbs(void)
	96	{
44a23cfd KG	97	int i;
	98
	99	for (i = 0; i < num_tlb_entries; i++) {
	100	set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
	101	tlb_table[i].perms, tlb_table[i].wimge,
	102	tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
	103	tlb_table[i].iprot);
	104	}
44a23cfd KG	105
	106	return ;
	107	}
6fb1b734	108
ecf5b98c KG	109	#ifdef CONFIG_ADDR_MAP
	110	void init_addr_map(void)
	111	{
	112	int i;
e393e2e9	113	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
ecf5b98c	114
e393e2e9 KG	115	/* walk all the entries */
	116	for (i = 0; i < max_cam; i++) {
	117	unsigned long epn;
963f2f61	118	u32 tsize, _mas1;
e393e2e9 KG	119	phys_addr_t rpn;
	120
	121	mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
	122
	123	asm volatile("tlbre;isync");
	124	_mas1 = mfspr(MAS1);
	125
	126	/* if the entry isn't valid skip it */
	127	if (!(_mas1 & MAS1_VALID))
ecf5b98c KG	128	continue;
ecf5b98c KG	129
e393e2e9 KG	130	tsize = (_mas1 >> 8) & 0xf;
	131	epn = mfspr(MAS2) & MAS2_EPN;
	132	rpn = mfspr(MAS3) & MAS3_RPN;
	133	#ifdef CONFIG_ENABLE_36BIT_PHYS
	134	rpn \|= ((phys_addr_t)mfspr(MAS7)) << 32;
	135	#endif
	136
	137	addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
ecf5b98c KG	138	}
	139
	140	return ;
	141	}
	142	#endif
	143
95026431 HW	144	#ifndef CONFIG_SYS_DDR_TLB_START
	145	#define CONFIG_SYS_DDR_TLB_START 8
	146	#endif
	147
6fb1b734 KG	148	unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
	149	{
	150	unsigned int tlb_size;
f8523cb0 KG	151	unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
f8523cb0 KG	152	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
90d13b8a	153	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
f8523cb0	154	u64 size, memsize = (u64)memsize_in_meg << 20;
6fb1b734	155
f8523cb0 KG	156	size = min(memsize, CONFIG_MAX_MEM_MAPPED);
	157
	158	/* Convert (4^max) kB to (2^max) bytes */
	159	max_cam = max_cam * 2 + 10;
	160
	161	for (; size && ram_tlb_index < 16; ram_tlb_index++) {
	162	u32 camsize = __ilog2_u64(size) & ~1U;
	163	u32 align = __ilog2(ram_tlb_address) & ~1U;
	164
	165	if (align == -2) align = max_cam;
	166	if (camsize > align)
	167	camsize = align;
	168
	169	if (camsize > max_cam)
	170	camsize = max_cam;
	171
	172	tlb_size = (camsize - 10) / 2;
6fb1b734	173
6fb1b734 KG	174	set_tlb(1, ram_tlb_address, ram_tlb_address,
	175	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	176	0, ram_tlb_index, tlb_size, 1);
	177
f8523cb0 KG	178	size -= 1ULL << camsize;
	179	memsize -= 1ULL << camsize;
	180	ram_tlb_address += 1UL << camsize;
6fb1b734 KG	181	}
6fb1b734 KG	182
f8523cb0	183	if (memsize)
d4b130dc	184	print_size(memsize, " left unmapped\n");
f8523cb0	185
6fb1b734 KG	186	/*
	187	* Confirm that the requested amount of memory was mapped.
	188	*/
	189	return memsize_in_meg;
	190	}