[J-u-boot.git] / drivers / i2c / fsl_i2c.c

/*
 * Copyright 2006,2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#ifdef CONFIG_HARD_I2C

#include <command.h>
#include <i2c.h>		/* Functional interface */

#include <asm/io.h>
#include <asm/fsl_i2c.h>	/* HW definitions */

/* The maximum number of microseconds we will wait until another master has
 * released the bus.  If not defined in the board header file, then use a
 * generic value.
 */
#ifndef CONFIG_I2C_MBB_TIMEOUT
#define CONFIG_I2C_MBB_TIMEOUT	100000
#endif

/* The maximum number of microseconds we will wait for a read or write
 * operation to complete.  If not defined in the board header file, then use a
 * generic value.
 */
#ifndef CONFIG_I2C_TIMEOUT
#define CONFIG_I2C_TIMEOUT	10000
#endif

#define I2C_READ_BIT  1
#define I2C_WRITE_BIT 0

DECLARE_GLOBAL_DATA_PTR;

/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
 * Default is bus 0.  This is necessary because the DDR initialization
 * runs from ROM, and we can't switch buses because we can't modify
 * the global variables.
 */
#ifndef CONFIG_SYS_SPD_BUS_NUM
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
#if defined(CONFIG_I2C_MUX)
static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
#endif

static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};

static const struct fsl_i2c *i2c_dev[2] = {
	(struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
#ifdef CONFIG_SYS_I2C2_OFFSET
	(struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
#endif
};

/* I2C speed map for a DFSR value of 1 */

/*
 * Map I2C frequency dividers to FDR and DFSR values
 *
 * This structure is used to define the elements of a table that maps I2C
 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
 * Sampling Rate (DFSR) registers.
 *
 * The actual table should be defined in the board file, and it must be called
 * fsl_i2c_speed_map[].
 *
 * The last entry of the table must have a value of {-1, X}, where X is same
 * FDR/DFSR values as the second-to-last entry.  This guarantees that any
 * search through the array will always find a match.
 *
 * The values of the divider must be in increasing numerical order, i.e.
 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
 *
 * For this table, the values are based on a value of 1 for the DFSR
 * register.  See the application note AN2919 "Determining the I2C Frequency
 * Divider Ratio for SCL"
 *
 * ColdFire I2C frequency dividers for FDR values are different from
 * PowerPC. The protocol to use the I2C module is still the same.
 * A different table is defined and are based on MCF5xxx user manual.
 *
 */
static const struct {
	unsigned short divider;
	u8 fdr;
} fsl_i2c_speed_map[] = {
#ifdef __M68K__
	{20, 32}, {22, 33}, {24, 34}, {26, 35},
	{28, 0}, {28, 36}, {30, 1}, {32, 37},
	{34, 2}, {36, 38}, {40, 3}, {40, 39},
	{44, 4}, {48, 5}, {48, 40}, {56, 6},
	{56, 41}, {64, 42}, {68, 7}, {72, 43},
	{80, 8}, {80, 44}, {88, 9}, {96, 41},
	{104, 10}, {112, 42}, {128, 11}, {128, 43},
	{144, 12}, {160, 13}, {160, 48}, {192, 14},
	{192, 49}, {224, 50}, {240, 15}, {256, 51},
	{288, 16}, {320, 17}, {320, 52}, {384, 18},
	{384, 53}, {448, 54}, {480, 19}, {512, 55},
	{576, 20}, {640, 21}, {640, 56}, {768, 22},
	{768, 57}, {960, 23}, {896, 58}, {1024, 59},
	{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
	{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
	{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
	{-1, 31}
#endif
};

/**
 * Set the I2C bus speed for a given I2C device
 *
 * @param dev: the I2C device
 * @i2c_clk: I2C bus clock frequency
 * @speed: the desired speed of the bus
 *
 * The I2C device must be stopped before calling this function.
 *
 * The return value is the actual bus speed that is set.
 */
static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
	unsigned int i2c_clk, unsigned int speed)
{
	unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);

	/*
	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
	 * is equal to or lower than the requested speed.  That means that we
	 * want the first divider that is equal to or greater than the
	 * calculated divider.
	 */
#ifdef __PPC__
	u8 dfsr, fdr = 0x31; /* Default if no FDR found */
	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
	unsigned short a, b, ga, gb;
	unsigned long c_div, est_div;

#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
	dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
#else
	/* Condition 1: dfsr <= 50/T */
	dfsr = (5 * (i2c_clk / 1000)) / 100000;
#endif
#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
	fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
	speed = i2c_clk / divider; /* Fake something */
#else
	debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
	if (!dfsr)
		dfsr = 1;

	est_div = ~0;
	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
		for (gb = 0; gb < 8; gb++) {
			b = 16 << gb;
			c_div = b * (a + ((3*dfsr)/b)*2);
			if ((c_div > divider) && (c_div < est_div)) {
				unsigned short bin_gb, bin_ga;

				est_div = c_div;
				bin_gb = gb << 2;
				bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
				fdr = bin_gb | bin_ga;
				speed = i2c_clk / est_div;
				debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
				      "a:%d, b:%d, speed:%d\n",
				      fdr, est_div, ga, gb, a, b, speed);
				/* Condition 2 not accounted for */
				debug("Tr <= %d ns\n",
				      (b - 3 * dfsr) * 1000000 /
				      (i2c_clk / 1000));
			}
		}
		if (a == 20)
			a += 2;
		if (a == 24)
			a += 4;
	}
	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
#endif
	writeb(dfsr, &dev->dfsrr);	/* set default filter */
	writeb(fdr, &dev->fdr);		/* set bus speed */
#else
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
		if (fsl_i2c_speed_map[i].divider >= divider) {
			u8 fdr;

			fdr = fsl_i2c_speed_map[i].fdr;
			speed = i2c_clk / fsl_i2c_speed_map[i].divider;
			writeb(fdr, &dev->fdr);		/* set bus speed */

			break;
		}
#endif
	return speed;
}

void
i2c_init(int speed, int slaveadd)
{
	struct fsl_i2c *dev;
	unsigned int temp;

#ifdef CONFIG_SYS_I2C_INIT_BOARD
	/* Call board specific i2c bus reset routine before accessing the
	 * environment, which might be in a chip on that bus. For details
	 * about this problem see doc/I2C_Edge_Conditions.
	*/
	i2c_init_board();
#endif
	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);

	writeb(0, &dev->cr);			/* stop I2C controller */
	udelay(5);				/* let it shutdown in peace */
	temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
	if (gd->flags & GD_FLG_RELOC)
		i2c_bus_speed[0] = temp;
	writeb(slaveadd << 1, &dev->adr);	/* write slave address */
	writeb(0x0, &dev->sr);			/* clear status register */
	writeb(I2C_CR_MEN, &dev->cr);		/* start I2C controller */

#ifdef	CONFIG_SYS_I2C2_OFFSET
	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET);

	writeb(0, &dev->cr);			/* stop I2C controller */
	udelay(5);				/* let it shutdown in peace */
	temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
	if (gd->flags & GD_FLG_RELOC)
		i2c_bus_speed[1] = temp;
	writeb(slaveadd << 1, &dev->adr);	/* write slave address */
	writeb(0x0, &dev->sr);			/* clear status register */
	writeb(I2C_CR_MEN, &dev->cr);		/* start I2C controller */
#endif

#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
	/* Call board specific i2c bus reset routine AFTER the bus has been
	 * initialized. Use either this callpoint or i2c_init_board;
	 * which is called before i2c_init operations.
	 * For details about this problem see doc/I2C_Edge_Conditions.
	*/
	i2c_board_late_init();
#endif
}

static int
i2c_wait4bus(void)
{
	unsigned long long timeval = get_ticks();
	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

	while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
		if ((get_ticks() - timeval) > timeout)
			return -1;
	}

	return 0;
}

static __inline__ int
i2c_wait(int write)
{
	u32 csr;
	unsigned long long timeval = get_ticks();
	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);

	do {
		csr = readb(&i2c_dev[i2c_bus_num]->sr);
		if (!(csr & I2C_SR_MIF))
			continue;
		/* Read again to allow register to stabilise */
		csr = readb(&i2c_dev[i2c_bus_num]->sr);

		writeb(0x0, &i2c_dev[i2c_bus_num]->sr);

		if (csr & I2C_SR_MAL) {
			debug("i2c_wait: MAL\n");
			return -1;
		}

		if (!(csr & I2C_SR_MCF))	{
			debug("i2c_wait: unfinished\n");
			return -1;
		}

		if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
			debug("i2c_wait: No RXACK\n");
			return -1;
		}

		return 0;
	} while ((get_ticks() - timeval) < timeout);

	debug("i2c_wait: timed out\n");
	return -1;
}

static __inline__ int
i2c_write_addr (u8 dev, u8 dir, int rsta)
{
	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
	       | (rsta ? I2C_CR_RSTA : 0),
	       &i2c_dev[i2c_bus_num]->cr);

	writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);

	if (i2c_wait(I2C_WRITE_BIT) < 0)
		return 0;

	return 1;
}

static __inline__ int
__i2c_write(u8 *data, int length)
{
	int i;

	for (i = 0; i < length; i++) {
		writeb(data[i], &i2c_dev[i2c_bus_num]->dr);

		if (i2c_wait(I2C_WRITE_BIT) < 0)
			break;
	}

	return i;
}

static __inline__ int
__i2c_read(u8 *data, int length)
{
	int i;

	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
	       &i2c_dev[i2c_bus_num]->cr);

	/* dummy read */
	readb(&i2c_dev[i2c_bus_num]->dr);

	for (i = 0; i < length; i++) {
		if (i2c_wait(I2C_READ_BIT) < 0)
			break;

		/* Generate ack on last next to last byte */
		if (i == length - 2)
			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
			       &i2c_dev[i2c_bus_num]->cr);

		/* Do not generate stop on last byte */
		if (i == length - 1)
			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
			       &i2c_dev[i2c_bus_num]->cr);

		data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
	}

	return i;
}

int
i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
{
	int i = -1; /* signal error */
	u8 *a = (u8*)&addr;

	if (i2c_wait4bus() >= 0
	    && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
	    && __i2c_write(&a[4 - alen], alen) == alen)
		i = 0; /* No error so far */

	if (length
	    && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
		i = __i2c_read(data, length);

	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);

	if (i2c_wait4bus()) /* Wait until STOP */
		debug("i2c_read: wait4bus timed out\n");

	if (i == length)
	    return 0;

	return -1;
}

int
i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
{
	int i = -1; /* signal error */
	u8 *a = (u8*)&addr;

	if (i2c_wait4bus() >= 0
	    && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
	    && __i2c_write(&a[4 - alen], alen) == alen) {
		i = __i2c_write(data, length);
	}

	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
	if (i2c_wait4bus()) /* Wait until STOP */
		debug("i2c_write: wait4bus timed out\n");

	if (i == length)
	    return 0;

	return -1;
}

int
i2c_probe(uchar chip)
{
	/* For unknow reason the controller will ACK when
	 * probing for a slave with the same address, so skip
	 * it.
	 */
	if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
		return -1;

	return i2c_read(chip, 0, 0, NULL, 0);
}

int i2c_set_bus_num(unsigned int bus)
{
#if defined(CONFIG_I2C_MUX)
	if (bus < CONFIG_SYS_MAX_I2C_BUS) {
		i2c_bus_num = bus;
	} else {
		int	ret;

		ret = i2x_mux_select_mux(bus);
		if (ret)
			return ret;
		i2c_bus_num = 0;
	}
	i2c_bus_num_mux = bus;
#else
#ifdef CONFIG_SYS_I2C2_OFFSET
	if (bus > 1) {
#else
	if (bus > 0) {
#endif
		return -1;
	}

	i2c_bus_num = bus;
#endif
	return 0;
}

int i2c_set_bus_speed(unsigned int speed)
{
	unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;

	writeb(0, &i2c_dev[i2c_bus_num]->cr);		/* stop controller */
	i2c_bus_speed[i2c_bus_num] =
		set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);	/* start controller */

	return 0;
}

unsigned int i2c_get_bus_num(void)
{
#if defined(CONFIG_I2C_MUX)
	return i2c_bus_num_mux;
#else
	return i2c_bus_num;
#endif
}

unsigned int i2c_get_bus_speed(void)
{
	return i2c_bus_speed[i2c_bus_num];
}

#endif /* CONFIG_HARD_I2C */
Commit	Line	Data
debb7354	1	/*
92477a63	2	* Copyright 2006,2009 Freescale Semiconductor, Inc.
debb7354 JL	3	*
debb7354 JL	4	* This program is free software; you can redistribute it and/or
7237c033 JL	5	* modify it under the terms of the GNU General Public License
7237c033 JL	6	* Version 2 as published by the Free Software Foundation.
debb7354 JL	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	16	* MA 02111-1307 USA
	17	*/
	18
	19	#include <common.h>
debb7354 JL	20
debb7354 JL	21	#ifdef CONFIG_HARD_I2C
debb7354	22
4d45f69e	23	#include <command.h>
20476726 JL	24	#include <i2c.h> /* Functional interface */
20476726 JL	25
7237c033	26	#include <asm/io.h>
20476726	27	#include <asm/fsl_i2c.h> /* HW definitions */
debb7354	28
92477a63 TT	29	/* The maximum number of microseconds we will wait until another master has
	30	* released the bus. If not defined in the board header file, then use a
	31	* generic value.
	32	*/
	33	#ifndef CONFIG_I2C_MBB_TIMEOUT
	34	#define CONFIG_I2C_MBB_TIMEOUT 100000
	35	#endif
	36
	37	/* The maximum number of microseconds we will wait for a read or write
	38	* operation to complete. If not defined in the board header file, then use a
	39	* generic value.
	40	*/
	41	#ifndef CONFIG_I2C_TIMEOUT
	42	#define CONFIG_I2C_TIMEOUT 10000
	43	#endif
debb7354	44
1939d969 JT	45	#define I2C_READ_BIT 1
	46	#define I2C_WRITE_BIT 0
	47
d8c82db4 TT	48	DECLARE_GLOBAL_DATA_PTR;
d8c82db4 TT	49
be5e6181 TT	50	/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
	51	* Default is bus 0. This is necessary because the DDR initialization
	52	* runs from ROM, and we can't switch buses because we can't modify
	53	* the global variables.
	54	*/
5e3ab68e TP	55	#ifndef CONFIG_SYS_SPD_BUS_NUM
5e3ab68e TP	56	#define CONFIG_SYS_SPD_BUS_NUM 0
be5e6181	57	#endif
5e3ab68e	58	static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
c1bce4ff HS	59	#if defined(CONFIG_I2C_MUX)
	60	static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
	61	#endif
be5e6181	62
6d0f6bcf	63	static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
d8c82db4 TT	64
d8c82db4 TT	65	static const struct fsl_i2c *i2c_dev[2] = {
6d0f6bcf JCPV	66	(struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
	67	#ifdef CONFIG_SYS_I2C2_OFFSET
	68	(struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
be5e6181 TT	69	#endif
be5e6181 TT	70	};
debb7354	71
d8c82db4 TT	72	/* I2C speed map for a DFSR value of 1 */
	73
	74	/*
	75	* Map I2C frequency dividers to FDR and DFSR values
	76	*
	77	* This structure is used to define the elements of a table that maps I2C
	78	* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
	79	* programmed into the Frequency Divider Ratio (FDR) and Digital Filter
	80	* Sampling Rate (DFSR) registers.
	81	*
	82	* The actual table should be defined in the board file, and it must be called
	83	* fsl_i2c_speed_map[].
	84	*
	85	* The last entry of the table must have a value of {-1, X}, where X is same
	86	* FDR/DFSR values as the second-to-last entry. This guarantees that any
	87	* search through the array will always find a match.
	88	*
	89	* The values of the divider must be in increasing numerical order, i.e.
	90	* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
	91	*
	92	* For this table, the values are based on a value of 1 for the DFSR
	93	* register. See the application note AN2919 "Determining the I2C Frequency
	94	* Divider Ratio for SCL"
5d9a5efa TL	95	*
	96	* ColdFire I2C frequency dividers for FDR values are different from
	97	* PowerPC. The protocol to use the I2C module is still the same.
	98	* A different table is defined and are based on MCF5xxx user manual.
	99	*
d8c82db4 TT	100	*/
	101	static const struct {
	102	unsigned short divider;
d8c82db4 TT	103	u8 fdr;
d8c82db4 TT	104	} fsl_i2c_speed_map[] = {
99404202	105	#ifdef __M68K__
5d9a5efa TL	106	{20, 32}, {22, 33}, {24, 34}, {26, 35},
	107	{28, 0}, {28, 36}, {30, 1}, {32, 37},
	108	{34, 2}, {36, 38}, {40, 3}, {40, 39},
	109	{44, 4}, {48, 5}, {48, 40}, {56, 6},
	110	{56, 41}, {64, 42}, {68, 7}, {72, 43},
	111	{80, 8}, {80, 44}, {88, 9}, {96, 41},
	112	{104, 10}, {112, 42}, {128, 11}, {128, 43},
	113	{144, 12}, {160, 13}, {160, 48}, {192, 14},
	114	{192, 49}, {224, 50}, {240, 15}, {256, 51},
	115	{288, 16}, {320, 17}, {320, 52}, {384, 18},
	116	{384, 53}, {448, 54}, {480, 19}, {512, 55},
	117	{576, 20}, {640, 21}, {640, 56}, {768, 22},
	118	{768, 57}, {960, 23}, {896, 58}, {1024, 59},
	119	{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
	120	{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
	121	{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
	122	{-1, 31}
	123	#endif
d8c82db4 TT	124	};
	125
	126	/**
	127	* Set the I2C bus speed for a given I2C device
	128	*
	129	* @param dev: the I2C device
	130	* @i2c_clk: I2C bus clock frequency
	131	* @speed: the desired speed of the bus
	132	*
	133	* The I2C device must be stopped before calling this function.
	134	*
	135	* The return value is the actual bus speed that is set.
	136	*/
	137	static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
	138	unsigned int i2c_clk, unsigned int speed)
	139	{
	140	unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
d8c82db4 TT	141
	142	/*
	143	* We want to choose an FDR/DFSR that generates an I2C bus speed that
	144	* is equal to or lower than the requested speed. That means that we
	145	* want the first divider that is equal to or greater than the
	146	* calculated divider.
	147	*/
5d9a5efa	148	#ifdef __PPC__
99404202 JT	149	u8 dfsr, fdr = 0x31; /* Default if no FDR found */
	150	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
	151	unsigned short a, b, ga, gb;
	152	unsigned long c_div, est_div;
	153
d01ee4db	154	#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
99404202	155	dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
d01ee4db	156	#else
99404202 JT	157	/* Condition 1: dfsr <= 50/T */
99404202 JT	158	dfsr = (5 * (i2c_clk / 1000)) / 100000;
d01ee4db JT	159	#endif
d01ee4db JT	160	#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
99404202 JT	161	fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
	162	speed = i2c_clk / divider; /* Fake something */
	163	#else
	164	debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
	165	if (!dfsr)
	166	dfsr = 1;
	167
	168	est_div = ~0;
	169	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
	170	for (gb = 0; gb < 8; gb++) {
	171	b = 16 << gb;
	172	c_div = b * (a + ((3dfsr)/b)2);
	173	if ((c_div > divider) && (c_div < est_div)) {
	174	unsigned short bin_gb, bin_ga;
	175
	176	est_div = c_div;
	177	bin_gb = gb << 2;
	178	bin_ga = (ga & 0x3) \| ((ga & 0x4) << 3);
	179	fdr = bin_gb \| bin_ga;
	180	speed = i2c_clk / est_div;
	181	debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
	182	"a:%d, b:%d, speed:%d\n",
	183	fdr, est_div, ga, gb, a, b, speed);
	184	/* Condition 2 not accounted for */
	185	debug("Tr <= %d ns\n",
	186	(b - 3 * dfsr) * 1000000 /
	187	(i2c_clk / 1000));
	188	}
	189	}
	190	if (a == 20)
	191	a += 2;
	192	if (a == 24)
	193	a += 4;
	194	}
	195	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
	196	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
	197	#endif
	198	writeb(dfsr, &dev->dfsrr); /* set default filter */
	199	writeb(fdr, &dev->fdr); /* set bus speed */
d01ee4db	200	#else
99404202 JT	201	unsigned int i;
	202
	203	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
	204	if (fsl_i2c_speed_map[i].divider >= divider) {
	205	u8 fdr;
	206
d8c82db4 TT	207	fdr = fsl_i2c_speed_map[i].fdr;
d8c82db4 TT	208	speed = i2c_clk / fsl_i2c_speed_map[i].divider;
d01ee4db JT	209	writeb(fdr, &dev->fdr); /* set bus speed */
d01ee4db JT	210
d8c82db4 TT	211	break;
d8c82db4 TT	212	}
99404202	213	#endif
d8c82db4 TT	214	return speed;
	215	}
	216
debb7354 JL	217	void
	218	i2c_init(int speed, int slaveadd)
	219	{
d8c82db4	220	struct fsl_i2c *dev;
f2302d44	221	unsigned int temp;
be5e6181	222
39df00d9	223	#ifdef CONFIG_SYS_I2C_INIT_BOARD
26a33504 RR	224	/* Call board specific i2c bus reset routine before accessing the
	225	* environment, which might be in a chip on that bus. For details
	226	* about this problem see doc/I2C_Edge_Conditions.
	227	*/
39df00d9 HS	228	i2c_init_board();
39df00d9 HS	229	#endif
6d0f6bcf	230	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
be5e6181 TT	231
be5e6181 TT	232	writeb(0, &dev->cr); /* stop I2C controller */
f6f5f709	233	udelay(5); /* let it shutdown in peace */
f2302d44 SR	234	temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
	235	if (gd->flags & GD_FLG_RELOC)
	236	i2c_bus_speed[0] = temp;
14198bf7	237	writeb(slaveadd << 1, &dev->adr); /* write slave address */
be5e6181 TT	238	writeb(0x0, &dev->sr); /* clear status register */
	239	writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
	240
6d0f6bcf JCPV	241	#ifdef CONFIG_SYS_I2C2_OFFSET
6d0f6bcf JCPV	242	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET);
be5e6181 TT	243
be5e6181 TT	244	writeb(0, &dev->cr); /* stop I2C controller */
e739bc95	245	udelay(5); /* let it shutdown in peace */
f2302d44 SR	246	temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
	247	if (gd->flags & GD_FLG_RELOC)
	248	i2c_bus_speed[1] = temp;
e739bc95	249	writeb(slaveadd << 1, &dev->adr); /* write slave address */
be5e6181 TT	250	writeb(0x0, &dev->sr); /* clear status register */
be5e6181 TT	251	writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
d8c82db4	252	#endif
26a33504 RR	253
	254	#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
	255	/* Call board specific i2c bus reset routine AFTER the bus has been
	256	* initialized. Use either this callpoint or i2c_init_board;
	257	* which is called before i2c_init operations.
	258	* For details about this problem see doc/I2C_Edge_Conditions.
	259	*/
	260	i2c_board_late_init();
	261	#endif
debb7354 JL	262	}
debb7354 JL	263
21f4cbb7	264	static int
5c9efb36	265	i2c_wait4bus(void)
debb7354	266	{
f2302d44	267	unsigned long long timeval = get_ticks();
92477a63	268	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
debb7354	269
be5e6181	270	while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
92477a63	271	if ((get_ticks() - timeval) > timeout)
debb7354	272	return -1;
debb7354 JL	273	}
debb7354 JL	274
5c9efb36	275	return 0;
debb7354 JL	276	}
	277
	278	static __inline__ int
5c9efb36	279	i2c_wait(int write)
debb7354 JL	280	{
debb7354 JL	281	u32 csr;
f2302d44	282	unsigned long long timeval = get_ticks();
92477a63	283	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
debb7354 JL	284
debb7354 JL	285	do {
be5e6181	286	csr = readb(&i2c_dev[i2c_bus_num]->sr);
7237c033	287	if (!(csr & I2C_SR_MIF))
debb7354	288	continue;
21f4cbb7 JT	289	/* Read again to allow register to stabilise */
21f4cbb7 JT	290	csr = readb(&i2c_dev[i2c_bus_num]->sr);
debb7354	291
be5e6181	292	writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
debb7354	293
7237c033	294	if (csr & I2C_SR_MAL) {
debb7354 JL	295	debug("i2c_wait: MAL\n");
	296	return -1;
	297	}
	298
7237c033	299	if (!(csr & I2C_SR_MCF)) {
debb7354 JL	300	debug("i2c_wait: unfinished\n");
	301	return -1;
	302	}
	303
1939d969	304	if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
debb7354 JL	305	debug("i2c_wait: No RXACK\n");
	306	return -1;
	307	}
	308
	309	return 0;
92477a63	310	} while ((get_ticks() - timeval) < timeout);
debb7354 JL	311
	312	debug("i2c_wait: timed out\n");
	313	return -1;
	314	}
	315
	316	static __inline__ int
7237c033	317	i2c_write_addr (u8 dev, u8 dir, int rsta)
debb7354	318	{
7237c033 JL	319	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_MTX
7237c033 JL	320	\| (rsta ? I2C_CR_RSTA : 0),
be5e6181	321	&i2c_dev[i2c_bus_num]->cr);
debb7354	322
be5e6181	323	writeb((dev << 1) \| dir, &i2c_dev[i2c_bus_num]->dr);
debb7354	324
1939d969	325	if (i2c_wait(I2C_WRITE_BIT) < 0)
debb7354 JL	326	return 0;
	327
	328	return 1;
	329	}
	330
	331	static __inline__ int
ffff3ae5	332	__i2c_write(u8 *data, int length)
debb7354 JL	333	{
debb7354 JL	334	int i;
5c9efb36	335
5c9efb36	336	for (i = 0; i < length; i++) {
be5e6181	337	writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
debb7354	338
1939d969	339	if (i2c_wait(I2C_WRITE_BIT) < 0)
debb7354 JL	340	break;
	341	}
	342
	343	return i;
	344	}
	345
	346	static __inline__ int
ffff3ae5	347	__i2c_read(u8 *data, int length)
debb7354 JL	348	{
	349	int i;
	350
7237c033	351	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| ((length == 1) ? I2C_CR_TXAK : 0),
be5e6181	352	&i2c_dev[i2c_bus_num]->cr);
debb7354 JL	353
debb7354 JL	354	/* dummy read */
be5e6181	355	readb(&i2c_dev[i2c_bus_num]->dr);
debb7354	356
5c9efb36	357	for (i = 0; i < length; i++) {
1939d969	358	if (i2c_wait(I2C_READ_BIT) < 0)
debb7354 JL	359	break;
	360
	361	/* Generate ack on last next to last byte */
	362	if (i == length - 2)
7237c033	363	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_TXAK,
be5e6181	364	&i2c_dev[i2c_bus_num]->cr);
debb7354	365
d1c9e5b3	366	/* Do not generate stop on last byte */
debb7354	367	if (i == length - 1)
d1c9e5b3 JT	368	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_MTX,
d1c9e5b3 JT	369	&i2c_dev[i2c_bus_num]->cr);
debb7354	370
be5e6181	371	data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
debb7354	372	}
5c9efb36	373
debb7354 JL	374	return i;
	375	}
	376
	377	int
ffff3ae5	378	i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
debb7354	379	{
f6f5f709	380	int i = -1; /* signal error */
7237c033	381	u8 a = (u8)&addr;
debb7354	382
4d45f69e	383	if (i2c_wait4bus() >= 0
1939d969	384	&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
f6f5f709 JT	385	&& __i2c_write(&a[4 - alen], alen) == alen)
	386	i = 0; /* No error so far */
	387
	388	if (length
	389	&& i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
4d45f69e	390	i = __i2c_read(data, length);
debb7354	391
be5e6181	392	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
debb7354	393
d1c9e5b3 JT	394	if (i2c_wait4bus()) /* Wait until STOP */
	395	debug("i2c_read: wait4bus timed out\n");
	396
4d45f69e JL	397	if (i == length)
	398	return 0;
	399
	400	return -1;
debb7354 JL	401	}
	402
	403	int
ffff3ae5	404	i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
debb7354	405	{
f6f5f709	406	int i = -1; /* signal error */
7237c033	407	u8 a = (u8)&addr;
debb7354	408
4d45f69e	409	if (i2c_wait4bus() >= 0
1939d969	410	&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
4d45f69e JL	411	&& __i2c_write(&a[4 - alen], alen) == alen) {
	412	i = __i2c_write(data, length);
	413	}
debb7354	414
be5e6181	415	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
21f4cbb7 JT	416	if (i2c_wait4bus()) /* Wait until STOP */
21f4cbb7 JT	417	debug("i2c_write: wait4bus timed out\n");
debb7354	418
4d45f69e JL	419	if (i == length)
	420	return 0;
	421
	422	return -1;
debb7354 JL	423	}
debb7354 JL	424
ffff3ae5 JL	425	int
ffff3ae5 JL	426	i2c_probe(uchar chip)
debb7354	427	{
f6f5f709 JT	428	/* For unknow reason the controller will ACK when
	429	* probing for a slave with the same address, so skip
	430	* it.
debb7354	431	*/
f6f5f709 JT	432	if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
f6f5f709 JT	433	return -1;
debb7354	434
f6f5f709	435	return i2c_read(chip, 0, 0, NULL, 0);
debb7354 JL	436	}
debb7354 JL	437
be5e6181 TT	438	int i2c_set_bus_num(unsigned int bus)
be5e6181 TT	439	{
c1bce4ff HS	440	#if defined(CONFIG_I2C_MUX)
	441	if (bus < CONFIG_SYS_MAX_I2C_BUS) {
	442	i2c_bus_num = bus;
	443	} else {
	444	int ret;
	445
	446	ret = i2x_mux_select_mux(bus);
	447	if (ret)
	448	return ret;
	449	i2c_bus_num = 0;
	450	}
	451	i2c_bus_num_mux = bus;
	452	#else
6d0f6bcf	453	#ifdef CONFIG_SYS_I2C2_OFFSET
be5e6181 TT	454	if (bus > 1) {
	455	#else
	456	if (bus > 0) {
	457	#endif
	458	return -1;
	459	}
	460
	461	i2c_bus_num = bus;
c1bce4ff	462	#endif
be5e6181 TT	463	return 0;
	464	}
	465
	466	int i2c_set_bus_speed(unsigned int speed)
	467	{
d8c82db4 TT	468	unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
	469
	470	writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
	471	i2c_bus_speed[i2c_bus_num] =
	472	set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
	473	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
	474
	475	return 0;
be5e6181 TT	476	}
	477
	478	unsigned int i2c_get_bus_num(void)
	479	{
c1bce4ff HS	480	#if defined(CONFIG_I2C_MUX)
	481	return i2c_bus_num_mux;
	482	#else
be5e6181	483	return i2c_bus_num;
c1bce4ff	484	#endif
be5e6181 TT	485	}
	486
	487	unsigned int i2c_get_bus_speed(void)
	488	{
d8c82db4	489	return i2c_bus_speed[i2c_bus_num];
be5e6181	490	}
d8c82db4	491
debb7354	492	#endif /* CONFIG_HARD_I2C */