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Commit | Line | Data |
---|---|---|
0b11dbf7 MY |
1 | # |
2 | # I2C subsystem configuration | |
3 | # | |
4 | ||
59e11ebf SG |
5 | menuconfig I2C |
6 | bool "I2C support" | |
7 | default y | |
8 | help | |
9 | Note: | |
10 | This is a stand-in for an option to enable I2C support. In fact this | |
11 | simply enables building of the I2C directory for U-Boot. The actual | |
12 | I2C feature is enabled by DM_I2C (for driver model) and | |
13 | the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack). | |
14 | ||
15 | So at present there is no need to ever disable this option. | |
16 | ||
17 | Eventually it will: | |
18 | ||
19 | Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot. | |
20 | I2C works with a clock and data line which can be driven by a | |
21 | one or more masters or slaves. It is a fairly complex bus but is | |
22 | widely used as it only needs two lines for communication. Speeds of | |
23 | 400kbps are typical but up to 3.4Mbps is supported by some | |
24 | hardware. Enable this option to build the drivers in drivers/i2c as | |
25 | part of a U-Boot build. | |
26 | ||
27 | if I2C | |
0b11dbf7 | 28 | |
b6036bcd MY |
29 | config DM_I2C |
30 | bool "Enable Driver Model for I2C drivers" | |
31 | depends on DM | |
32 | help | |
705fcf4d PM |
33 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
34 | write and speed, is implemented with the bus drivers operations, | |
35 | which provide methods for bus setting and data transfer. Each chip | |
caa4daa2 | 36 | device (bus child) info is kept as parent plat. The interface |
e3114824 | 37 | is defined in include/i2c.h. |
4bba9d3f | 38 | |
d1f3abe1 IO |
39 | config SPL_DM_I2C |
40 | bool "Enable Driver Model for I2C drivers in SPL" | |
41 | depends on SPL_DM && DM_I2C | |
42 | default y | |
43 | help | |
44 | Enable driver model for I2C. The I2C uclass interface: probe, read, | |
45 | write and speed, is implemented with the bus drivers operations, | |
46 | which provide methods for bus setting and data transfer. Each chip | |
47 | device (bus child) info is kept as parent platdata. The interface | |
48 | is defined in include/i2c.h. | |
49 | ||
cc456bd7 SG |
50 | config I2C_CROS_EC_TUNNEL |
51 | tristate "Chrome OS EC tunnel I2C bus" | |
52 | depends on CROS_EC | |
53 | help | |
54 | This provides an I2C bus that will tunnel i2c commands through to | |
55 | the other side of the Chrome OS EC to the I2C bus connected there. | |
56 | This will work whatever the interface used to talk to the EC (SPI, | |
57 | I2C or LPC). Some Chromebooks use this when the hardware design | |
58 | does not allow direct access to the main PMIC from the AP. | |
59 | ||
f48eaf01 SG |
60 | config I2C_CROS_EC_LDO |
61 | bool "Provide access to LDOs on the Chrome OS EC" | |
62 | depends on CROS_EC | |
63 | ---help--- | |
64 | On many Chromebooks the main PMIC is inaccessible to the AP. This is | |
65 | often dealt with by using an I2C pass-through interface provided by | |
66 | the EC. On some unfortunate models (e.g. Spring) the pass-through | |
67 | is not available, and an LDO message is available instead. This | |
68 | option enables a driver which provides very basic access to those | |
69 | regulators, via the EC. We implement this as an I2C bus which | |
70 | emulates just the TPS65090 messages we know about. This is done to | |
71 | avoid duplicating the logic in the TPS65090 regulator driver for | |
72 | enabling/disabling an LDO. | |
cc456bd7 | 73 | |
e46f8a33 LM |
74 | config I2C_SET_DEFAULT_BUS_NUM |
75 | bool "Set default I2C bus number" | |
76 | depends on DM_I2C | |
77 | help | |
78 | Set default number of I2C bus to be accessed. This option provides | |
79 | behaviour similar to old (i.e. pre DM) I2C bus driver. | |
80 | ||
81 | config I2C_DEFAULT_BUS_NUMBER | |
82 | hex "I2C default bus number" | |
83 | depends on I2C_SET_DEFAULT_BUS_NUM | |
84 | default 0x0 | |
85 | help | |
86 | Number of default I2C bus to use | |
87 | ||
c54473cb PM |
88 | config DM_I2C_GPIO |
89 | bool "Enable Driver Model for software emulated I2C bus driver" | |
90 | depends on DM_I2C && DM_GPIO | |
91 | help | |
92 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO | |
93 | configuration is given by the device tree. Kernel-style device tree | |
94 | bindings are supported. | |
95 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt | |
96 | ||
d1f3abe1 IO |
97 | config SPL_DM_I2C_GPIO |
98 | bool "Enable Driver Model for software emulated I2C bus driver in SPL" | |
83061dbd | 99 | depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO |
d1f3abe1 IO |
100 | default y |
101 | help | |
102 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO | |
103 | configuration is given by the device tree. Kernel-style device tree | |
104 | bindings are supported. | |
105 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt | |
106 | ||
8800e0fa SW |
107 | config SYS_I2C_AT91 |
108 | bool "Atmel I2C driver" | |
109 | depends on DM_I2C && ARCH_AT91 | |
110 | help | |
111 | Add support for the Atmel I2C driver. A serious problem is that there | |
112 | is no documented way to issue repeated START conditions for more than | |
113 | two messages, as needed to support combined I2C messages. Use the | |
114 | i2c-gpio driver unless your system can cope with this limitation. | |
115 | Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt | |
116 | ||
956d57a8 RK |
117 | config SYS_I2C_IPROC |
118 | bool "Broadcom I2C driver" | |
119 | depends on DM_I2C | |
120 | help | |
121 | Broadcom I2C driver. | |
122 | Add support for Broadcom I2C driver. | |
123 | Say yes here to to enable the Broadco I2C driver. | |
124 | ||
dbc82ce3 | 125 | config SYS_I2C_FSL |
126 | bool "Freescale I2C bus driver" | |
127 | depends on DM_I2C | |
128 | help | |
129 | Add support for Freescale I2C busses as used on MPC8240, MPC8245, and | |
130 | MPC85xx processors. | |
131 | ||
fdec2d21 MF |
132 | config SYS_I2C_CADENCE |
133 | tristate "Cadence I2C Controller" | |
664e16ce | 134 | depends on DM_I2C |
fdec2d21 MF |
135 | help |
136 | Say yes here to select Cadence I2C Host Controller. This controller is | |
137 | e.g. used by Xilinx Zynq. | |
138 | ||
7f5ea250 AL |
139 | config SYS_I2C_CA |
140 | tristate "Cortina-Access I2C Controller" | |
141 | depends on DM_I2C && CORTINA_PLATFORM | |
142 | default n | |
143 | help | |
144 | Add support for the Cortina Access I2C host controller. | |
145 | Say yes here to select Cortina-Access I2C Host Controller. | |
146 | ||
9f8cf76b AF |
147 | config SYS_I2C_DAVINCI |
148 | bool "Davinci I2C Controller" | |
149 | depends on (ARCH_KEYSTONE || ARCH_DAVINCI) | |
150 | help | |
151 | Say yes here to add support for Davinci and Keystone I2C controller | |
152 | ||
e32d0db7 SR |
153 | config SYS_I2C_DW |
154 | bool "Designware I2C Controller" | |
155 | default n | |
156 | help | |
157 | Say yes here to select the Designware I2C Host Controller. This | |
158 | controller is used in various SoCs, e.g. the ST SPEAr, Altera | |
159 | SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. | |
160 | ||
4dc038f3 | 161 | config SYS_I2C_ASPEED |
162 | bool "Aspeed I2C Controller" | |
163 | depends on DM_I2C && ARCH_ASPEED | |
164 | help | |
165 | Say yes here to select Aspeed I2C Host Controller. The driver | |
166 | supports AST2500 and AST2400 controllers, but is very limited. | |
167 | Only single master mode is supported and only byte-by-byte | |
168 | synchronous reads and writes are supported, no Pool Buffers or DMA. | |
169 | ||
abb0b01e SG |
170 | config SYS_I2C_INTEL |
171 | bool "Intel I2C/SMBUS driver" | |
172 | depends on DM_I2C | |
173 | help | |
174 | Add support for the Intel SMBUS driver. So far this driver is just | |
175 | a stub which perhaps some basic init. There is no implementation of | |
176 | the I2C API meaning that any I2C operations will immediately fail | |
177 | for now. | |
178 | ||
7ee3f149 PF |
179 | config SYS_I2C_IMX_LPI2C |
180 | bool "NXP i.MX LPI2C driver" | |
7ee3f149 PF |
181 | help |
182 | Add support for the NXP i.MX LPI2C driver. | |
183 | ||
0705556b TW |
184 | config SYS_I2C_LPC32XX |
185 | bool "LPC32XX I2C driver" | |
186 | depends on ARCH_LPC32XX | |
187 | help | |
188 | Enable support for the LPC32xx I2C driver. | |
189 | ||
f8d9ca18 BG |
190 | config SYS_I2C_MESON |
191 | bool "Amlogic Meson I2C driver" | |
192 | depends on DM_I2C && ARCH_MESON | |
193 | help | |
4ecbb8b6 BG |
194 | Add support for the I2C controller available in Amlogic Meson |
195 | SoCs. The controller supports programmable bus speed including | |
196 | standard (100kbits/s) and fast (400kbit/s) speed and allows the | |
197 | software to define a flexible format of the bit streams. It has an | |
198 | internal buffer holding up to 8 bytes for transfers and supports | |
199 | both 7-bit and 10-bit addresses. | |
f8d9ca18 | 200 | |
72c8c10b | 201 | config SYS_I2C_MXC |
942ecc8b | 202 | bool "NXP MXC I2C driver" |
72c8c10b | 203 | help |
74751454 CP |
204 | Add support for the NXP I2C driver. This supports up to four bus |
205 | channels and operating on standard mode up to 100 kbits/s and fast | |
206 | mode up to 400 kbits/s. | |
72c8c10b | 207 | |
ca0a8f3e TP |
208 | # These settings are not used with DM_I2C, however SPL doesn't use |
209 | # DM_I2C even if DM_I2C is enabled, and so might use these settings even | |
210 | # when main u-boot does not! | |
211 | if SYS_I2C_MXC && (!DM_I2C || SPL) | |
942ecc8b SD |
212 | config SYS_I2C_MXC_I2C1 |
213 | bool "NXP MXC I2C1" | |
214 | help | |
215 | Add support for NXP MXC I2C Controller 1. | |
216 | Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A | |
217 | ||
218 | config SYS_I2C_MXC_I2C2 | |
219 | bool "NXP MXC I2C2" | |
220 | help | |
221 | Add support for NXP MXC I2C Controller 2. | |
222 | Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A | |
223 | ||
224 | config SYS_I2C_MXC_I2C3 | |
225 | bool "NXP MXC I2C3" | |
226 | help | |
227 | Add support for NXP MXC I2C Controller 3. | |
228 | Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A | |
229 | ||
230 | config SYS_I2C_MXC_I2C4 | |
231 | bool "NXP MXC I2C4" | |
232 | help | |
233 | Add support for NXP MXC I2C Controller 4. | |
234 | Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A | |
fa452192 SD |
235 | |
236 | config SYS_I2C_MXC_I2C5 | |
237 | bool "NXP MXC I2C5" | |
238 | help | |
239 | Add support for NXP MXC I2C Controller 5. | |
240 | Required for SoCs which have I2C MXC controller 5 eg LX2160A | |
241 | ||
242 | config SYS_I2C_MXC_I2C6 | |
243 | bool "NXP MXC I2C6" | |
244 | help | |
245 | Add support for NXP MXC I2C Controller 6. | |
246 | Required for SoCs which have I2C MXC controller 6 eg LX2160A | |
247 | ||
248 | config SYS_I2C_MXC_I2C7 | |
249 | bool "NXP MXC I2C7" | |
250 | help | |
251 | Add support for NXP MXC I2C Controller 7. | |
252 | Required for SoCs which have I2C MXC controller 7 eg LX2160A | |
253 | ||
254 | config SYS_I2C_MXC_I2C8 | |
255 | bool "NXP MXC I2C8" | |
256 | help | |
257 | Add support for NXP MXC I2C Controller 8. | |
258 | Required for SoCs which have I2C MXC controller 8 eg LX2160A | |
942ecc8b SD |
259 | endif |
260 | ||
261 | if SYS_I2C_MXC_I2C1 | |
262 | config SYS_MXC_I2C1_SPEED | |
263 | int "I2C Channel 1 speed" | |
2ce7b65d | 264 | default 40000000 if TARGET_LS2080A_EMU |
942ecc8b SD |
265 | default 100000 |
266 | help | |
267 | MXC I2C Channel 1 speed | |
268 | ||
269 | config SYS_MXC_I2C1_SLAVE | |
270 | int "I2C1 Slave" | |
271 | default 0 | |
272 | help | |
273 | MXC I2C1 Slave | |
274 | endif | |
275 | ||
276 | if SYS_I2C_MXC_I2C2 | |
277 | config SYS_MXC_I2C2_SPEED | |
278 | int "I2C Channel 2 speed" | |
2ce7b65d | 279 | default 40000000 if TARGET_LS2080A_EMU |
942ecc8b SD |
280 | default 100000 |
281 | help | |
282 | MXC I2C Channel 2 speed | |
283 | ||
284 | config SYS_MXC_I2C2_SLAVE | |
285 | int "I2C2 Slave" | |
286 | default 0 | |
287 | help | |
288 | MXC I2C2 Slave | |
289 | endif | |
290 | ||
291 | if SYS_I2C_MXC_I2C3 | |
292 | config SYS_MXC_I2C3_SPEED | |
293 | int "I2C Channel 3 speed" | |
294 | default 100000 | |
295 | help | |
296 | MXC I2C Channel 3 speed | |
297 | ||
298 | config SYS_MXC_I2C3_SLAVE | |
299 | int "I2C3 Slave" | |
300 | default 0 | |
301 | help | |
302 | MXC I2C3 Slave | |
303 | endif | |
304 | ||
305 | if SYS_I2C_MXC_I2C4 | |
306 | config SYS_MXC_I2C4_SPEED | |
307 | int "I2C Channel 4 speed" | |
308 | default 100000 | |
309 | help | |
310 | MXC I2C Channel 4 speed | |
311 | ||
312 | config SYS_MXC_I2C4_SLAVE | |
313 | int "I2C4 Slave" | |
314 | default 0 | |
315 | help | |
316 | MXC I2C4 Slave | |
317 | endif | |
318 | ||
fa452192 SD |
319 | if SYS_I2C_MXC_I2C5 |
320 | config SYS_MXC_I2C5_SPEED | |
321 | int "I2C Channel 5 speed" | |
322 | default 100000 | |
323 | help | |
324 | MXC I2C Channel 5 speed | |
325 | ||
326 | config SYS_MXC_I2C5_SLAVE | |
327 | int "I2C5 Slave" | |
328 | default 0 | |
329 | help | |
330 | MXC I2C5 Slave | |
331 | endif | |
332 | ||
333 | if SYS_I2C_MXC_I2C6 | |
334 | config SYS_MXC_I2C6_SPEED | |
335 | int "I2C Channel 6 speed" | |
336 | default 100000 | |
337 | help | |
338 | MXC I2C Channel 6 speed | |
339 | ||
340 | config SYS_MXC_I2C6_SLAVE | |
341 | int "I2C6 Slave" | |
342 | default 0 | |
343 | help | |
344 | MXC I2C6 Slave | |
345 | endif | |
346 | ||
347 | if SYS_I2C_MXC_I2C7 | |
348 | config SYS_MXC_I2C7_SPEED | |
349 | int "I2C Channel 7 speed" | |
350 | default 100000 | |
351 | help | |
352 | MXC I2C Channel 7 speed | |
353 | ||
354 | config SYS_MXC_I2C7_SLAVE | |
355 | int "I2C7 Slave" | |
356 | default 0 | |
357 | help | |
358 | MXC I2C7 Slave | |
359 | endif | |
360 | ||
361 | if SYS_I2C_MXC_I2C8 | |
362 | config SYS_MXC_I2C8_SPEED | |
363 | int "I2C Channel 8 speed" | |
364 | default 100000 | |
365 | help | |
366 | MXC I2C Channel 8 speed | |
367 | ||
368 | config SYS_MXC_I2C8_SLAVE | |
369 | int "I2C8 Slave" | |
370 | default 0 | |
371 | help | |
372 | MXC I2C8 Slave | |
373 | endif | |
374 | ||
c25e9e04 SB |
375 | config SYS_I2C_NEXELL |
376 | bool "Nexell I2C driver" | |
377 | depends on DM_I2C | |
378 | help | |
379 | Add support for the Nexell I2C driver. This is used with various | |
380 | Nexell parts such as S5Pxx18 series SoCs. All chips | |
381 | have several I2C ports and all are provided, controlled by the | |
382 | device tree. | |
383 | ||
b2d4cbe6 PP |
384 | config SYS_I2C_OCORES |
385 | bool "ocores I2C driver" | |
386 | depends on DM_I2C | |
387 | help | |
388 | Add support for ocores I2C controller. For details see | |
389 | https://opencores.org/projects/i2c | |
390 | ||
daa0f050 AF |
391 | config SYS_I2C_OMAP24XX |
392 | bool "TI OMAP2+ I2C driver" | |
14106bca | 393 | depends on ARCH_OMAP2PLUS || ARCH_K3 |
daa0f050 AF |
394 | help |
395 | Add support for the OMAP2+ I2C driver. | |
396 | ||
11d2e98d AF |
397 | if SYS_I2C_OMAP24XX |
398 | config SYS_OMAP24_I2C_SLAVE | |
399 | int "I2C Slave addr channel 0" | |
400 | default 1 | |
401 | help | |
402 | OMAP24xx I2C Slave address channel 0 | |
403 | ||
404 | config SYS_OMAP24_I2C_SPEED | |
405 | int "I2C Slave channel 0 speed" | |
406 | default 100000 | |
407 | help | |
408 | OMAP24xx Slave speed channel 0 | |
409 | endif | |
410 | ||
a06a0ac3 MV |
411 | config SYS_I2C_RCAR_I2C |
412 | bool "Renesas RCar I2C driver" | |
413 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C | |
414 | help | |
415 | Support for Renesas RCar I2C controller. | |
416 | ||
9e75ea46 MV |
417 | config SYS_I2C_RCAR_IIC |
418 | bool "Renesas RCar Gen3 IIC driver" | |
f51155ec | 419 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C |
9e75ea46 MV |
420 | help |
421 | Support for Renesas RCar Gen3 IIC controller. | |
422 | ||
34374699 SG |
423 | config SYS_I2C_ROCKCHIP |
424 | bool "Rockchip I2C driver" | |
425 | depends on DM_I2C | |
426 | help | |
427 | Add support for the Rockchip I2C driver. This is used with various | |
428 | Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips | |
74751454 | 429 | have several I2C ports and all are provided, controlled by the |
34374699 SG |
430 | device tree. |
431 | ||
1174aada SG |
432 | config SYS_I2C_SANDBOX |
433 | bool "Sandbox I2C driver" | |
434 | depends on SANDBOX && DM_I2C | |
435 | help | |
436 | Enable I2C support for sandbox. This is an emulation of a real I2C | |
437 | bus. Devices can be attached to the bus using the device tree | |
c77c7db5 | 438 | which specifies the driver to use. See sandbox.dts as an example. |
1174aada | 439 | |
de695725 TR |
440 | config SYS_I2C_SOFT |
441 | bool "Legacy software I2C interface" | |
442 | help | |
443 | Enable the legacy software defined I2C interface | |
444 | ||
445 | config SYS_I2C_SOFT_SPEED | |
446 | int "Software I2C bus speed" | |
447 | depends on SYS_I2C_SOFT | |
448 | default 100000 | |
449 | help | |
450 | Speed of the software I2C bus | |
451 | ||
452 | config SYS_I2C_SOFT_SLAVE | |
453 | hex "Software I2C slave address" | |
454 | depends on SYS_I2C_SOFT | |
455 | default 0xfe | |
456 | help | |
457 | Slave address of the software I2C bus | |
458 | ||
5c2c3e8b SG |
459 | config SYS_I2C_OCTEON |
460 | bool "Octeon II/III/TX/TX2 I2C driver" | |
461 | depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C | |
462 | default y | |
463 | help | |
464 | Add support for the Marvell Octeon I2C driver. This is used with | |
465 | various Octeon parts such as Octeon II/III and OcteonTX/TX2. All | |
466 | chips have several I2C ports and all are provided, controlled by | |
467 | the device tree. | |
468 | ||
1d61ad95 JC |
469 | config SYS_I2C_S3C24X0 |
470 | bool "Samsung I2C driver" | |
0283da44 | 471 | depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C |
1d61ad95 JC |
472 | help |
473 | Support for Samsung I2C controller as Samsung SoCs. | |
1174aada | 474 | |
4fadcaf0 PC |
475 | config SYS_I2C_STM32F7 |
476 | bool "STMicroelectronics STM32F7 I2C support" | |
2514c2d0 | 477 | depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C |
4fadcaf0 PC |
478 | help |
479 | Enable this option to add support for STM32 I2C controller | |
480 | introduced with STM32F7/H7 SoCs. This I2C controller supports : | |
481 | _ Slave and master modes | |
482 | _ Multimaster capability | |
483 | _ Standard-mode (up to 100 kHz) | |
484 | _ Fast-mode (up to 400 kHz) | |
485 | _ Fast-mode Plus (up to 1 MHz) | |
486 | _ 7-bit and 10-bit addressing mode | |
487 | _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) | |
488 | _ All 7-bit addresses acknowledge mode | |
489 | _ General call | |
490 | _ Programmable setup and hold times | |
491 | _ Easy to use event management | |
492 | _ Optional clock stretching | |
493 | _ Software reset | |
494 | ||
4483fbab JB |
495 | config SYS_I2C_SYNQUACER |
496 | bool "Socionext SynQuacer I2C controller" | |
497 | depends on ARCH_SYNQUACER && DM_I2C | |
498 | help | |
499 | Support for Socionext Synquacer I2C controller. This I2C controller | |
500 | will be used for RTC and LS-connector on DeveloperBox. | |
501 | ||
02253d4d PR |
502 | config SYS_I2C_TEGRA |
503 | bool "NVIDIA Tegra internal I2C controller" | |
18138ab2 | 504 | depends on ARCH_TEGRA |
02253d4d PR |
505 | help |
506 | Support for NVIDIA I2C controller available in Tegra SoCs. | |
507 | ||
26f820f3 MY |
508 | config SYS_I2C_UNIPHIER |
509 | bool "UniPhier I2C driver" | |
510 | depends on ARCH_UNIPHIER && DM_I2C | |
511 | default y | |
512 | help | |
b6ef3a3f MY |
513 | Support for UniPhier I2C controller driver. This I2C controller |
514 | is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. | |
238bd0b8 MY |
515 | |
516 | config SYS_I2C_UNIPHIER_F | |
517 | bool "UniPhier FIFO-builtin I2C driver" | |
518 | depends on ARCH_UNIPHIER && DM_I2C | |
519 | default y | |
520 | help | |
b6ef3a3f | 521 | Support for UniPhier FIFO-builtin I2C controller driver. |
238bd0b8 | 522 | This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. |
3d1957f0 | 523 | |
e3bc4bb8 HS |
524 | config SYS_I2C_VERSATILE |
525 | bool "Arm Ltd Versatile I2C bus driver" | |
c6c26a05 | 526 | depends on DM_I2C && TARGET_VEXPRESS64_JUNO |
e3bc4bb8 HS |
527 | help |
528 | Add support for the Arm Ltd Versatile Express I2C driver. The I2C host | |
529 | controller is present in the development boards manufactured by Arm Ltd. | |
530 | ||
14a6ff2c | 531 | config SYS_I2C_MVTWSI |
532 | bool "Marvell I2C driver" | |
14a6ff2c | 533 | help |
534 | Support for Marvell I2C controllers as used on the orion5x and | |
535 | kirkwood SoC families. | |
536 | ||
34f1c9fe SW |
537 | config TEGRA186_BPMP_I2C |
538 | bool "Enable Tegra186 BPMP-based I2C driver" | |
539 | depends on TEGRA186_BPMP | |
540 | help | |
541 | Support for Tegra I2C controllers managed by the BPMP (Boot and | |
542 | Power Management Processor). On Tegra186, some I2C controllers are | |
543 | directly controlled by the main CPU, whereas others are controlled | |
544 | by the BPMP, and can only be accessed by the main CPU via IPC | |
545 | requests to the BPMP. This driver covers the latter case. | |
546 | ||
fc760cc6 AF |
547 | config SYS_I2C_BUS_MAX |
548 | int "Max I2C busses" | |
549 | depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA | |
550 | default 2 if TI816X | |
551 | default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE | |
552 | default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X | |
553 | default 5 if OMAP54XX | |
554 | help | |
555 | Define the maximum number of available I2C buses. | |
556 | ||
ad827a50 MV |
557 | config SYS_I2C_XILINX_XIIC |
558 | bool "Xilinx AXI I2C driver" | |
559 | depends on DM_I2C | |
560 | help | |
561 | Support for Xilinx AXI I2C controller. | |
562 | ||
92164216 MS |
563 | config SYS_I2C_IHS |
564 | bool "gdsys IHS I2C driver" | |
565 | depends on DM_I2C | |
566 | help | |
567 | Support for gdsys IHS I2C driver on FPGA bus. | |
568 | ||
3d1957f0 | 569 | source "drivers/i2c/muxes/Kconfig" |
0b11dbf7 | 570 | |
59e11ebf | 571 | endif |