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powerpc/tool/pbl: fix pbl image compiling process
[J-u-boot.git] / arch / powerpc / cpu / mpc8xxx / ddr / interactive.c
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6f5e1dc5 1/*
73b5396b 2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6f5e1dc5 3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
6f5e1dc5
YS		 5 */
6
7/*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 * York Sun [at freescale.com]
12 */
13
14#include <common.h>
15#include <linux/ctype.h>
16#include <asm/types.h>
17
18#include <asm/fsl_ddr_sdram.h>
19#include "ddr.h"
20
21/* Option parameter Structures */
22struct options_string {
23 const char *option_name;
24 size_t offset;
25 unsigned int size;
26 const char printhex;
27};
28
29static unsigned int picos_to_mhz(unsigned int picos)
30{
31 return 1000000 / picos;
32}
33
34static void print_option_table(const struct options_string *table,
35 int table_size,
36 const void *base)
37{
38 unsigned int i;
39 unsigned int *ptr;
40 unsigned long long *ptr_l;
41
42 for (i = 0; i < table_size; i++) {
43 switch (table[i].size) {
44 case 4:
45 ptr = (unsigned int *) (base + table[i].offset);
46 if (table[i].printhex) {
47 printf("%s = 0x%08X\n",
48 table[i].option_name, *ptr);
49 } else {
50 printf("%s = %u\n",
51 table[i].option_name, *ptr);
52 }
53 break;
54 case 8:
55 ptr_l = (unsigned long long *) (base + table[i].offset);
56 printf("%s = %llu\n",
57 table[i].option_name, *ptr_l);
58 break;
59 default:
60 printf("Unrecognized size!\n");
61 break;
62 }
63 }
64}
65
66static int handle_option_table(const struct options_string *table,
67 int table_size,
68 void *base,
69 const char *opt,
70 const char *val)
71{
72 unsigned int i;
73 unsigned int value, *ptr;
74 unsigned long long value_l, *ptr_l;
75
76 for (i = 0; i < table_size; i++) {
77 if (strcmp(table[i].option_name, opt) != 0)
78 continue;
79 switch (table[i].size) {
80 case 4:
81 value = simple_strtoul(val, NULL, 0);
82 ptr = base + table[i].offset;
83 *ptr = value;
84 break;
85 case 8:
86 value_l = simple_strtoull(val, NULL, 0);
87 ptr_l = base + table[i].offset;
88 *ptr_l = value_l;
89 break;
90 default:
91 printf("Unrecognized size!\n");
92 break;
93 }
94 return 1;
95 }
96
97 return 0;
98}
99
100static void fsl_ddr_generic_edit(void *pdata,
101 void *pend,
102 unsigned int element_size,
103 unsigned int element_num,
104 unsigned int value)
105{
106 char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */
107
108 pcdata += element_num * element_size;
109 if ((pcdata + element_size) > (char *) pend) {
110 printf("trying to write past end of data\n");
111 return;
112 }
113
114 switch (element_size) {
115 case 1:
116 __raw_writeb(value, pcdata);
117 break;
118 case 2:
119 __raw_writew(value, pcdata);
120 break;
121 case 4:
122 __raw_writel(value, pcdata);
123 break;
124 default:
125 printf("unexpected element size %u\n", element_size);
126 break;
127 }
128}
129
130static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
131 unsigned int ctrl_num,
132 unsigned int dimm_num,
133 unsigned int element_num,
134 unsigned int value)
135{
136 generic_spd_eeprom_t *pspd;
137
138 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
139 fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
140}
141
142#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
143 sizeof((common_timing_params_t *)0)->x, 0}
144
145static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
146 unsigned int ctrl_num,
147 const char *optname_str,
148 const char *value_str)
149{
150 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
151
152 static const struct options_string options[] = {
153 COMMON_TIMING(tCKmin_X_ps),
154 COMMON_TIMING(tCKmax_ps),
155 COMMON_TIMING(tCKmax_max_ps),
156 COMMON_TIMING(tRCD_ps),
157 COMMON_TIMING(tRP_ps),
158 COMMON_TIMING(tRAS_ps),
159 COMMON_TIMING(tWR_ps),
160 COMMON_TIMING(tWTR_ps),
161 COMMON_TIMING(tRFC_ps),
162 COMMON_TIMING(tRRD_ps),
163 COMMON_TIMING(tRC_ps),
164 COMMON_TIMING(refresh_rate_ps),
165 COMMON_TIMING(tIS_ps),
166 COMMON_TIMING(tIH_ps),
167 COMMON_TIMING(tDS_ps),
168 COMMON_TIMING(tDH_ps),
169 COMMON_TIMING(tRTP_ps),
170 COMMON_TIMING(tDQSQ_max_ps),
171 COMMON_TIMING(tQHS_ps),
172 COMMON_TIMING(ndimms_present),
173 COMMON_TIMING(lowest_common_SPD_caslat),
174 COMMON_TIMING(highest_common_derated_caslat),
175 COMMON_TIMING(additive_latency),
176 COMMON_TIMING(all_DIMMs_burst_lengths_bitmask),
177 COMMON_TIMING(all_DIMMs_registered),
178 COMMON_TIMING(all_DIMMs_unbuffered),
179 COMMON_TIMING(all_DIMMs_ECC_capable),
180 COMMON_TIMING(total_mem),
181 COMMON_TIMING(base_address),
182 };
183 static const unsigned int n_opts = ARRAY_SIZE(options);
184
185 if (handle_option_table(options, n_opts, p, optname_str, value_str))
186 return;
187
188 printf("Error: couldn't find option string %s\n", optname_str);
189}
190
191#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
192 sizeof((dimm_params_t *)0)->x, 0}
193
194static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
195 unsigned int ctrl_num,
196 unsigned int dimm_num,
197 const char *optname_str,
198 const char *value_str)
199{
200 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
201
202 static const struct options_string options[] = {
203 DIMM_PARM(n_ranks),
204 DIMM_PARM(data_width),
205 DIMM_PARM(primary_sdram_width),
206 DIMM_PARM(ec_sdram_width),
207 DIMM_PARM(registered_dimm),
b61e0615 208 DIMM_PARM(device_width),
6f5e1dc5
YS		 209
210 DIMM_PARM(n_row_addr),
211 DIMM_PARM(n_col_addr),
212 DIMM_PARM(edc_config),
213 DIMM_PARM(n_banks_per_sdram_device),
214 DIMM_PARM(burst_lengths_bitmask),
215 DIMM_PARM(row_density),
216
217 DIMM_PARM(tCKmin_X_ps),
218 DIMM_PARM(tCKmin_X_minus_1_ps),
219 DIMM_PARM(tCKmin_X_minus_2_ps),
220 DIMM_PARM(tCKmax_ps),
221
222 DIMM_PARM(caslat_X),
223 DIMM_PARM(caslat_X_minus_1),
224 DIMM_PARM(caslat_X_minus_2),
225
226 DIMM_PARM(caslat_lowest_derated),
227
228 DIMM_PARM(tRCD_ps),
229 DIMM_PARM(tRP_ps),
230 DIMM_PARM(tRAS_ps),
231 DIMM_PARM(tWR_ps),
232 DIMM_PARM(tWTR_ps),
233 DIMM_PARM(tRFC_ps),
234 DIMM_PARM(tRRD_ps),
235 DIMM_PARM(tRC_ps),
236 DIMM_PARM(refresh_rate_ps),
237
238 DIMM_PARM(tIS_ps),
239 DIMM_PARM(tIH_ps),
240 DIMM_PARM(tDS_ps),
241 DIMM_PARM(tDH_ps),
242 DIMM_PARM(tRTP_ps),
243 DIMM_PARM(tDQSQ_max_ps),
244 DIMM_PARM(tQHS_ps),
245
246 DIMM_PARM(rank_density),
247 DIMM_PARM(capacity),
248 DIMM_PARM(base_address),
249 };
250
251 static const unsigned int n_opts = ARRAY_SIZE(options);
252
253 if (handle_option_table(options, n_opts, p, optname_str, value_str))
254 return;
255
256 printf("couldn't find option string %s\n", optname_str);
257}
258
259static void print_dimm_parameters(const dimm_params_t *pdimm)
260{
261 static const struct options_string options[] = {
262 DIMM_PARM(n_ranks),
263 DIMM_PARM(data_width),
264 DIMM_PARM(primary_sdram_width),
265 DIMM_PARM(ec_sdram_width),
266 DIMM_PARM(registered_dimm),
b61e0615 267 DIMM_PARM(device_width),
6f5e1dc5
YS		 268
269 DIMM_PARM(n_row_addr),
270 DIMM_PARM(n_col_addr),
271 DIMM_PARM(edc_config),
272 DIMM_PARM(n_banks_per_sdram_device),
273
274 DIMM_PARM(tCKmin_X_ps),
275 DIMM_PARM(tCKmin_X_minus_1_ps),
276 DIMM_PARM(tCKmin_X_minus_2_ps),
277 DIMM_PARM(tCKmax_ps),
278
279 DIMM_PARM(caslat_X),
280 DIMM_PARM(tAA_ps),
281 DIMM_PARM(caslat_X_minus_1),
282 DIMM_PARM(caslat_X_minus_2),
283 DIMM_PARM(caslat_lowest_derated),
284
285 DIMM_PARM(tRCD_ps),
286 DIMM_PARM(tRP_ps),
287 DIMM_PARM(tRAS_ps),
288 DIMM_PARM(tWR_ps),
289 DIMM_PARM(tWTR_ps),
290 DIMM_PARM(tRFC_ps),
291 DIMM_PARM(tRRD_ps),
292 DIMM_PARM(tRC_ps),
293 DIMM_PARM(refresh_rate_ps),
294
295 DIMM_PARM(tIS_ps),
296 DIMM_PARM(tIH_ps),
297 DIMM_PARM(tDS_ps),
298 DIMM_PARM(tDH_ps),
299 DIMM_PARM(tRTP_ps),
300 DIMM_PARM(tDQSQ_max_ps),
301 DIMM_PARM(tQHS_ps),
302 };
303 static const unsigned int n_opts = ARRAY_SIZE(options);
304
305 if (pdimm->n_ranks == 0) {
306 printf("DIMM not present\n");
307 return;
308 }
309 printf("DIMM organization parameters:\n");
310 printf("module part name = %s\n", pdimm->mpart);
311 printf("rank_density = %llu bytes (%llu megabytes)\n",
312 pdimm->rank_density, pdimm->rank_density / 0x100000);
313 printf("capacity = %llu bytes (%llu megabytes)\n",
314 pdimm->capacity, pdimm->capacity / 0x100000);
315 printf("burst_lengths_bitmask = %02X\n",
316 pdimm->burst_lengths_bitmask);
317 printf("base_addresss = %llu (%08llX %08llX)\n",
318 pdimm->base_address,
319 (pdimm->base_address >> 32),
320 pdimm->base_address & 0xFFFFFFFF);
321 print_option_table(options, n_opts, pdimm);
322}
323
324static void print_lowest_common_dimm_parameters(
325 const common_timing_params_t *plcd_dimm_params)
326{
327 static const struct options_string options[] = {
328 COMMON_TIMING(tCKmax_max_ps),
329 COMMON_TIMING(tRCD_ps),
330 COMMON_TIMING(tRP_ps),
331 COMMON_TIMING(tRAS_ps),
332 COMMON_TIMING(tWR_ps),
333 COMMON_TIMING(tWTR_ps),
334 COMMON_TIMING(tRFC_ps),
335 COMMON_TIMING(tRRD_ps),
336 COMMON_TIMING(tRC_ps),
337 COMMON_TIMING(refresh_rate_ps),
338 COMMON_TIMING(tIS_ps),
339 COMMON_TIMING(tDS_ps),
340 COMMON_TIMING(tDH_ps),
341 COMMON_TIMING(tRTP_ps),
342 COMMON_TIMING(tDQSQ_max_ps),
343 COMMON_TIMING(tQHS_ps),
344 COMMON_TIMING(lowest_common_SPD_caslat),
345 COMMON_TIMING(highest_common_derated_caslat),
346 COMMON_TIMING(additive_latency),
347 COMMON_TIMING(ndimms_present),
348 COMMON_TIMING(all_DIMMs_registered),
349 COMMON_TIMING(all_DIMMs_unbuffered),
350 COMMON_TIMING(all_DIMMs_ECC_capable),
351 };
352 static const unsigned int n_opts = ARRAY_SIZE(options);
353
354 /* Clock frequencies */
355 printf("tCKmin_X_ps = %u (%u MHz)\n",
356 plcd_dimm_params->tCKmin_X_ps,
357 picos_to_mhz(plcd_dimm_params->tCKmin_X_ps));
358 printf("tCKmax_ps = %u (%u MHz)\n",
359 plcd_dimm_params->tCKmax_ps,
360 picos_to_mhz(plcd_dimm_params->tCKmax_ps));
361 printf("all_DIMMs_burst_lengths_bitmask = %02X\n",
362 plcd_dimm_params->all_DIMMs_burst_lengths_bitmask);
363
364 print_option_table(options, n_opts, plcd_dimm_params);
365
366 printf("total_mem = %llu (%llu megabytes)\n",
367 plcd_dimm_params->total_mem,
368 plcd_dimm_params->total_mem / 0x100000);
369 printf("base_address = %llu (%llu megabytes)\n",
370 plcd_dimm_params->base_address,
371 plcd_dimm_params->base_address / 0x100000);
372}
373
374#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
375 sizeof((memctl_options_t *)0)->x, 0}
376#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
377 offsetof(memctl_options_t, cs_local_opts[x].y), \
378 sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
379
380static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
381 unsigned int ctl_num,
382 const char *optname_str,
383 const char *value_str)
384{
385 memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
386 /*
387 * This array all on the stack and *computed* each time this
388 * function is rung.
389 */
390 static const struct options_string options[] = {
391 CTRL_OPTIONS_CS(0, odt_rd_cfg),
392 CTRL_OPTIONS_CS(0, odt_wr_cfg),
393#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
394 CTRL_OPTIONS_CS(1, odt_rd_cfg),
395 CTRL_OPTIONS_CS(1, odt_wr_cfg),
396#endif
397#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
398 CTRL_OPTIONS_CS(2, odt_rd_cfg),
399 CTRL_OPTIONS_CS(2, odt_wr_cfg),
400#endif
401#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
402 CTRL_OPTIONS_CS(3, odt_rd_cfg),
403 CTRL_OPTIONS_CS(3, odt_wr_cfg),
404#endif
405#if defined(CONFIG_FSL_DDR3)
406 CTRL_OPTIONS_CS(0, odt_rtt_norm),
407 CTRL_OPTIONS_CS(0, odt_rtt_wr),
408#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
409 CTRL_OPTIONS_CS(1, odt_rtt_norm),
410 CTRL_OPTIONS_CS(1, odt_rtt_wr),
411#endif
412#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
413 CTRL_OPTIONS_CS(2, odt_rtt_norm),
414 CTRL_OPTIONS_CS(2, odt_rtt_wr),
415#endif
416#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
417 CTRL_OPTIONS_CS(3, odt_rtt_norm),
418 CTRL_OPTIONS_CS(3, odt_rtt_wr),
419#endif
420#endif
421 CTRL_OPTIONS(memctl_interleaving),
422 CTRL_OPTIONS(memctl_interleaving_mode),
423 CTRL_OPTIONS(ba_intlv_ctl),
424 CTRL_OPTIONS(ECC_mode),
425 CTRL_OPTIONS(ECC_init_using_memctl),
426 CTRL_OPTIONS(DQS_config),
427 CTRL_OPTIONS(self_refresh_in_sleep),
428 CTRL_OPTIONS(dynamic_power),
429 CTRL_OPTIONS(data_bus_width),
430 CTRL_OPTIONS(burst_length),
431 CTRL_OPTIONS(cas_latency_override),
432 CTRL_OPTIONS(cas_latency_override_value),
433 CTRL_OPTIONS(use_derated_caslat),
434 CTRL_OPTIONS(additive_latency_override),
435 CTRL_OPTIONS(additive_latency_override_value),
436 CTRL_OPTIONS(clk_adjust),
437 CTRL_OPTIONS(cpo_override),
438 CTRL_OPTIONS(write_data_delay),
439 CTRL_OPTIONS(half_strength_driver_enable),
440
441 /*
442 * These can probably be changed to 2T_EN and 3T_EN
443 * (using a leading numerical character) without problem
444 */
445 CTRL_OPTIONS(twoT_en),
446 CTRL_OPTIONS(threeT_en),
447 CTRL_OPTIONS(ap_en),
b61e0615 448 CTRL_OPTIONS(x4_en),
6f5e1dc5
YS		 449 CTRL_OPTIONS(bstopre),
450 CTRL_OPTIONS(wrlvl_override),
451 CTRL_OPTIONS(wrlvl_sample),
452 CTRL_OPTIONS(wrlvl_start),
453 CTRL_OPTIONS(rcw_override),
454 CTRL_OPTIONS(rcw_1),
455 CTRL_OPTIONS(rcw_2),
57495e4e
YS		 456 CTRL_OPTIONS(ddr_cdr1),
457 CTRL_OPTIONS(ddr_cdr2),
6f5e1dc5
YS		 458 CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
459 CTRL_OPTIONS(tFAW_window_four_activates_ps),
460 CTRL_OPTIONS(trwt_override),
461 CTRL_OPTIONS(trwt),
462 };
463
464 static const unsigned int n_opts = ARRAY_SIZE(options);
465
466 if (handle_option_table(options, n_opts, p,
467 optname_str, value_str))
468 return;
469
470 printf("couldn't find option string %s\n", optname_str);
471}
472
473#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
474 sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
475#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
476 offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
477 sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
478
479static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
480{
481 unsigned int i;
482 static const struct options_string options[] = {
483 CFG_REGS_CS(0, bnds),
484 CFG_REGS_CS(0, config),
485 CFG_REGS_CS(0, config_2),
486#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
487 CFG_REGS_CS(1, bnds),
488 CFG_REGS_CS(1, config),
489 CFG_REGS_CS(1, config_2),
490#endif
491#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
492 CFG_REGS_CS(2, bnds),
493 CFG_REGS_CS(2, config),
494 CFG_REGS_CS(2, config_2),
495#endif
496#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
497 CFG_REGS_CS(3, bnds),
498 CFG_REGS_CS(3, config),
499 CFG_REGS_CS(3, config_2),
500#endif
501 CFG_REGS(timing_cfg_3),
502 CFG_REGS(timing_cfg_0),
503 CFG_REGS(timing_cfg_1),
504 CFG_REGS(timing_cfg_2),
505 CFG_REGS(ddr_sdram_cfg),
506 CFG_REGS(ddr_sdram_cfg_2),
507 CFG_REGS(ddr_sdram_mode),
508 CFG_REGS(ddr_sdram_mode_2),
509 CFG_REGS(ddr_sdram_mode_3),
510 CFG_REGS(ddr_sdram_mode_4),
511 CFG_REGS(ddr_sdram_mode_5),
512 CFG_REGS(ddr_sdram_mode_6),
513 CFG_REGS(ddr_sdram_mode_7),
514 CFG_REGS(ddr_sdram_mode_8),
515 CFG_REGS(ddr_sdram_interval),
516 CFG_REGS(ddr_data_init),
517 CFG_REGS(ddr_sdram_clk_cntl),
518 CFG_REGS(ddr_init_addr),
519 CFG_REGS(ddr_init_ext_addr),
520 CFG_REGS(timing_cfg_4),
521 CFG_REGS(timing_cfg_5),
522 CFG_REGS(ddr_zq_cntl),
523 CFG_REGS(ddr_wrlvl_cntl),
57495e4e
YS		 524 CFG_REGS(ddr_wrlvl_cntl_2),
525 CFG_REGS(ddr_wrlvl_cntl_3),
6f5e1dc5
YS		 526 CFG_REGS(ddr_sr_cntr),
527 CFG_REGS(ddr_sdram_rcw_1),
528 CFG_REGS(ddr_sdram_rcw_2),
529 CFG_REGS(ddr_cdr1),
530 CFG_REGS(ddr_cdr2),
531 CFG_REGS(err_disable),
532 CFG_REGS(err_int_en),
57495e4e 533 CFG_REGS(ddr_eor),
6f5e1dc5
YS		 534 };
535 static const unsigned int n_opts = ARRAY_SIZE(options);
536
537 print_option_table(options, n_opts, ddr);
538
539 for (i = 0; i < 32; i++)
540 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
541}
542
543static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
544 unsigned int ctrl_num,
545 const char *regname,
546 const char *value_str)
547{
548 unsigned int i;
549 fsl_ddr_cfg_regs_t *ddr;
550 char buf[20];
551 static const struct options_string options[] = {
552 CFG_REGS_CS(0, bnds),
553 CFG_REGS_CS(0, config),
554 CFG_REGS_CS(0, config_2),
555#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
556 CFG_REGS_CS(1, bnds),
557 CFG_REGS_CS(1, config),
558 CFG_REGS_CS(1, config_2),
559#endif
560#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
561 CFG_REGS_CS(2, bnds),
562 CFG_REGS_CS(2, config),
563 CFG_REGS_CS(2, config_2),
564#endif
565#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
566 CFG_REGS_CS(3, bnds),
567 CFG_REGS_CS(3, config),
568 CFG_REGS_CS(3, config_2),
569#endif
570 CFG_REGS(timing_cfg_3),
571 CFG_REGS(timing_cfg_0),
572 CFG_REGS(timing_cfg_1),
573 CFG_REGS(timing_cfg_2),
574 CFG_REGS(ddr_sdram_cfg),
575 CFG_REGS(ddr_sdram_cfg_2),
576 CFG_REGS(ddr_sdram_mode),
577 CFG_REGS(ddr_sdram_mode_2),
578 CFG_REGS(ddr_sdram_mode_3),
579 CFG_REGS(ddr_sdram_mode_4),
580 CFG_REGS(ddr_sdram_mode_5),
581 CFG_REGS(ddr_sdram_mode_6),
582 CFG_REGS(ddr_sdram_mode_7),
583 CFG_REGS(ddr_sdram_mode_8),
584 CFG_REGS(ddr_sdram_interval),
585 CFG_REGS(ddr_data_init),
586 CFG_REGS(ddr_sdram_clk_cntl),
587 CFG_REGS(ddr_init_addr),
588 CFG_REGS(ddr_init_ext_addr),
589 CFG_REGS(timing_cfg_4),
590 CFG_REGS(timing_cfg_5),
591 CFG_REGS(ddr_zq_cntl),
592 CFG_REGS(ddr_wrlvl_cntl),
57495e4e
YS		 593 CFG_REGS(ddr_wrlvl_cntl_2),
594 CFG_REGS(ddr_wrlvl_cntl_3),
6f5e1dc5
YS		 595 CFG_REGS(ddr_sr_cntr),
596 CFG_REGS(ddr_sdram_rcw_1),
597 CFG_REGS(ddr_sdram_rcw_2),
598 CFG_REGS(ddr_cdr1),
599 CFG_REGS(ddr_cdr2),
600 CFG_REGS(err_disable),
601 CFG_REGS(err_int_en),
602 CFG_REGS(ddr_sdram_rcw_2),
603 CFG_REGS(ddr_sdram_rcw_2),
57495e4e 604 CFG_REGS(ddr_eor),
6f5e1dc5
YS		 605 };
606 static const unsigned int n_opts = ARRAY_SIZE(options);
607
608 debug("fsl_ddr_regs_edit: ctrl_num = %u, "
609 "regname = %s, value = %s\n",
610 ctrl_num, regname, value_str);
611 if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
612 return;
613
614 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
615
616 if (handle_option_table(options, n_opts, ddr, regname, value_str))
617 return;
618
619 for (i = 0; i < 32; i++) {
620 unsigned int value = simple_strtoul(value_str, NULL, 0);
621 sprintf(buf, "debug_%u", i + 1);
622 if (strcmp(buf, regname) == 0) {
623 ddr->debug[i] = value;
624 return;
625 }
626 }
627 printf("Error: couldn't find register string %s\n", regname);
628}
629
630#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
631 sizeof((memctl_options_t *)0)->x, 1}
632
633static void print_memctl_options(const memctl_options_t *popts)
634{
635 static const struct options_string options[] = {
636 CTRL_OPTIONS_CS(0, odt_rd_cfg),
637 CTRL_OPTIONS_CS(0, odt_wr_cfg),
638#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
639 CTRL_OPTIONS_CS(1, odt_rd_cfg),
640 CTRL_OPTIONS_CS(1, odt_wr_cfg),
641#endif
642#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
643 CTRL_OPTIONS_CS(2, odt_rd_cfg),
644 CTRL_OPTIONS_CS(2, odt_wr_cfg),
645#endif
646#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
647 CTRL_OPTIONS_CS(3, odt_rd_cfg),
648 CTRL_OPTIONS_CS(3, odt_wr_cfg),
649#endif
650#if defined(CONFIG_FSL_DDR3)
651 CTRL_OPTIONS_CS(0, odt_rtt_norm),
652 CTRL_OPTIONS_CS(0, odt_rtt_wr),
653#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
654 CTRL_OPTIONS_CS(1, odt_rtt_norm),
655 CTRL_OPTIONS_CS(1, odt_rtt_wr),
656#endif
657#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
658 CTRL_OPTIONS_CS(2, odt_rtt_norm),
659 CTRL_OPTIONS_CS(2, odt_rtt_wr),
660#endif
661#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
662 CTRL_OPTIONS_CS(3, odt_rtt_norm),
663 CTRL_OPTIONS_CS(3, odt_rtt_wr),
664#endif
665#endif
666 CTRL_OPTIONS(memctl_interleaving),
667 CTRL_OPTIONS(memctl_interleaving_mode),
668 CTRL_OPTIONS_HEX(ba_intlv_ctl),
669 CTRL_OPTIONS(ECC_mode),
670 CTRL_OPTIONS(ECC_init_using_memctl),
671 CTRL_OPTIONS(DQS_config),
672 CTRL_OPTIONS(self_refresh_in_sleep),
673 CTRL_OPTIONS(dynamic_power),
674 CTRL_OPTIONS(data_bus_width),
675 CTRL_OPTIONS(burst_length),
676 CTRL_OPTIONS(cas_latency_override),
677 CTRL_OPTIONS(cas_latency_override_value),
678 CTRL_OPTIONS(use_derated_caslat),
679 CTRL_OPTIONS(additive_latency_override),
680 CTRL_OPTIONS(additive_latency_override_value),
681 CTRL_OPTIONS(clk_adjust),
682 CTRL_OPTIONS(cpo_override),
683 CTRL_OPTIONS(write_data_delay),
684 CTRL_OPTIONS(half_strength_driver_enable),
685 /*
686 * These can probably be changed to 2T_EN and 3T_EN
687 * (using a leading numerical character) without problem
688 */
689 CTRL_OPTIONS(twoT_en),
690 CTRL_OPTIONS(threeT_en),
691 CTRL_OPTIONS(registered_dimm_en),
692 CTRL_OPTIONS(ap_en),
b61e0615 693 CTRL_OPTIONS(x4_en),
6f5e1dc5
YS		 694 CTRL_OPTIONS(bstopre),
695 CTRL_OPTIONS(wrlvl_override),
696 CTRL_OPTIONS(wrlvl_sample),
697 CTRL_OPTIONS(wrlvl_start),
698 CTRL_OPTIONS(rcw_override),
699 CTRL_OPTIONS(rcw_1),
700 CTRL_OPTIONS(rcw_2),
57495e4e
YS		 701 CTRL_OPTIONS_HEX(ddr_cdr1),
702 CTRL_OPTIONS_HEX(ddr_cdr2),
6f5e1dc5
YS		 703 CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
704 CTRL_OPTIONS(tFAW_window_four_activates_ps),
705 CTRL_OPTIONS(trwt_override),
706 CTRL_OPTIONS(trwt),
707 };
708 static const unsigned int n_opts = ARRAY_SIZE(options);
709
710 print_option_table(options, n_opts, popts);
711}
712
713#ifdef CONFIG_FSL_DDR1
714void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
715{
716 unsigned int i;
717
718 printf("%-3d : %02x %s\n", 0, spd->info_size,
719 " spd->info_size, * 0 # bytes written into serial memory *");
720 printf("%-3d : %02x %s\n", 1, spd->chip_size,
721 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
722 printf("%-3d : %02x %s\n", 2, spd->mem_type,
723 " spd->mem_type, * 2 Fundamental memory type *");
724 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
725 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
726 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
727 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
728 printf("%-3d : %02x %s\n", 5, spd->nrows,
729 " spd->nrows * 5 # of DIMM Banks *");
730 printf("%-3d : %02x %s\n", 6, spd->dataw_lsb,
731 " spd->dataw_lsb, * 6 Data Width lsb of this assembly *");
732 printf("%-3d : %02x %s\n", 7, spd->dataw_msb,
733 " spd->dataw_msb, * 7 Data Width msb of this assembly *");
734 printf("%-3d : %02x %s\n", 8, spd->voltage,
735 " spd->voltage, * 8 Voltage intf std of this assembly *");
736 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
737 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
738 printf("%-3d : %02x %s\n", 10, spd->clk_access,
739 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
740 printf("%-3d : %02x %s\n", 11, spd->config,
741 " spd->config, * 11 DIMM Configuration type *");
742 printf("%-3d : %02x %s\n", 12, spd->refresh,
743 " spd->refresh, * 12 Refresh Rate/Type *");
744 printf("%-3d : %02x %s\n", 13, spd->primw,
745 " spd->primw, * 13 Primary SDRAM Width *");
746 printf("%-3d : %02x %s\n", 14, spd->ecw,
747 " spd->ecw, * 14 Error Checking SDRAM width *");
748 printf("%-3d : %02x %s\n", 15, spd->min_delay,
749 " spd->min_delay, * 15 Back to Back Random Access *");
750 printf("%-3d : %02x %s\n", 16, spd->burstl,
751 " spd->burstl, * 16 Burst Lengths Supported *");
752 printf("%-3d : %02x %s\n", 17, spd->nbanks,
753 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
754 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
755 " spd->cas_lat, * 18 CAS# Latencies Supported *");
756 printf("%-3d : %02x %s\n", 19, spd->cs_lat,
757 " spd->cs_lat, * 19 Chip Select Latency *");
758 printf("%-3d : %02x %s\n", 20, spd->write_lat,
759 " spd->write_lat, * 20 Write Latency/Recovery *");
760 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
761 " spd->mod_attr, * 21 SDRAM Module Attributes *");
762 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
763 " spd->dev_attr, * 22 SDRAM Device Attributes *");
764 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
765 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
766 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
767 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
768 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
769 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
770 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
771 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
772 printf("%-3d : %02x %s\n", 27, spd->trp,
773 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
774 printf("%-3d : %02x %s\n", 28, spd->trrd,
775 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
776 printf("%-3d : %02x %s\n", 29, spd->trcd,
777 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
778 printf("%-3d : %02x %s\n", 30, spd->tras,
779 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
780 printf("%-3d : %02x %s\n", 31, spd->bank_dens,
781 " spd->bank_dens, * 31 Density of each bank on module *");
782 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
783 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
784 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
785 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
786 printf("%-3d : %02x %s\n", 34, spd->data_setup,
787 " spd->data_setup, * 34 Data signal input setup time *");
788 printf("%-3d : %02x %s\n", 35, spd->data_hold,
789 " spd->data_hold, * 35 Data signal input hold time *");
790 printf("%-3d : %02x %s\n", 36, spd->res_36_40[0],
791 " spd->res_36_40[0], * 36 Reserved / tWR *");
792 printf("%-3d : %02x %s\n", 37, spd->res_36_40[1],
793 " spd->res_36_40[1], * 37 Reserved / tWTR *");
794 printf("%-3d : %02x %s\n", 38, spd->res_36_40[2],
795 " spd->res_36_40[2], * 38 Reserved / tRTP *");
796 printf("%-3d : %02x %s\n", 39, spd->res_36_40[3],
797 " spd->res_36_40[3], * 39 Reserved / mem_probe *");
798 printf("%-3d : %02x %s\n", 40, spd->res_36_40[4],
799 " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
800 printf("%-3d : %02x %s\n", 41, spd->trc,
801 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
802 printf("%-3d : %02x %s\n", 42, spd->trfc,
803 " spd->trfc, * 42 Min Auto to Active period tRFC *");
804 printf("%-3d : %02x %s\n", 43, spd->tckmax,
805 " spd->tckmax, * 43 Max device cycle time tCKmax *");
806 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
807 " spd->tdqsq, * 44 Max DQS to DQ skew *");
808 printf("%-3d : %02x %s\n", 45, spd->tqhs,
809 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
810 printf("%-3d : %02x %s\n", 46, spd->res_46,
811 " spd->res_46, * 46 Reserved/ PLL Relock time *");
812 printf("%-3d : %02x %s\n", 47, spd->dimm_height,
813 " spd->dimm_height * 47 SDRAM DIMM Height *");
814
815 printf("%-3d-%3d: ", 48, 61);
816
817 for (i = 0; i < 14; i++)
818 printf("%02x", spd->res_48_61[i]);
819
820 printf(" * 48-61 IDD in SPD and Reserved space *\n");
821
822 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
823 " spd->spd_rev, * 62 SPD Data Revision Code *");
824 printf("%-3d : %02x %s\n", 63, spd->cksum,
825 " spd->cksum, * 63 Checksum for bytes 0-62 *");
826 printf("%-3d-%3d: ", 64, 71);
827
828 for (i = 0; i < 8; i++)
829 printf("%02x", spd->mid[i]);
830
831 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
832 printf("%-3d : %02x %s\n", 72, spd->mloc,
833 " spd->mloc, * 72 Manufacturing Location *");
834
835 printf("%-3d-%3d: >>", 73, 90);
836
837 for (i = 0; i < 18; i++)
838 printf("%c", spd->mpart[i]);
839
840 printf("<<* 73 Manufacturer's Part Number *\n");
841
842 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
843 "* 91 Revision Code *");
844 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
845 "* 93 Manufacturing Date *");
846 printf("%-3d-%3d: ", 95, 98);
847
848 for (i = 0; i < 4; i++)
849 printf("%02x", spd->sernum[i]);
850
851 printf("* 95 Assembly Serial Number *\n");
852
853 printf("%-3d-%3d: ", 99, 127);
854
855 for (i = 0; i < 27; i++)
856 printf("%02x", spd->mspec[i]);
857
858 printf("* 99 Manufacturer Specific Data *\n");
859}
860#endif
861
862#ifdef CONFIG_FSL_DDR2
863void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
864{
865 unsigned int i;
866
867 printf("%-3d : %02x %s\n", 0, spd->info_size,
868 " spd->info_size, * 0 # bytes written into serial memory *");
869 printf("%-3d : %02x %s\n", 1, spd->chip_size,
870 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
871 printf("%-3d : %02x %s\n", 2, spd->mem_type,
872 " spd->mem_type, * 2 Fundamental memory type *");
873 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
874 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
875 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
876 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
877 printf("%-3d : %02x %s\n", 5, spd->mod_ranks,
878 " spd->mod_ranks * 5 # of Module Rows on this assembly *");
879 printf("%-3d : %02x %s\n", 6, spd->dataw,
880 " spd->dataw, * 6 Data Width of this assembly *");
881 printf("%-3d : %02x %s\n", 7, spd->res_7,
882 " spd->res_7, * 7 Reserved *");
883 printf("%-3d : %02x %s\n", 8, spd->voltage,
884 " spd->voltage, * 8 Voltage intf std of this assembly *");
885 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
886 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
887 printf("%-3d : %02x %s\n", 10, spd->clk_access,
888 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
889 printf("%-3d : %02x %s\n", 11, spd->config,
890 " spd->config, * 11 DIMM Configuration type *");
891 printf("%-3d : %02x %s\n", 12, spd->refresh,
892 " spd->refresh, * 12 Refresh Rate/Type *");
893 printf("%-3d : %02x %s\n", 13, spd->primw,
894 " spd->primw, * 13 Primary SDRAM Width *");
895 printf("%-3d : %02x %s\n", 14, spd->ecw,
896 " spd->ecw, * 14 Error Checking SDRAM width *");
897 printf("%-3d : %02x %s\n", 15, spd->res_15,
898 " spd->res_15, * 15 Reserved *");
899 printf("%-3d : %02x %s\n", 16, spd->burstl,
900 " spd->burstl, * 16 Burst Lengths Supported *");
901 printf("%-3d : %02x %s\n", 17, spd->nbanks,
902 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
903 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
904 " spd->cas_lat, * 18 CAS# Latencies Supported *");
905 printf("%-3d : %02x %s\n", 19, spd->mech_char,
906 " spd->mech_char, * 19 Mechanical Characteristics *");
907 printf("%-3d : %02x %s\n", 20, spd->dimm_type,
908 " spd->dimm_type, * 20 DIMM type *");
909 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
910 " spd->mod_attr, * 21 SDRAM Module Attributes *");
911 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
912 " spd->dev_attr, * 22 SDRAM Device Attributes *");
913 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
914 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
915 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
916 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
917 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
918 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
919 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
920 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
921 printf("%-3d : %02x %s\n", 27, spd->trp,
922 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
923 printf("%-3d : %02x %s\n", 28, spd->trrd,
924 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
925 printf("%-3d : %02x %s\n", 29, spd->trcd,
926 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
927 printf("%-3d : %02x %s\n", 30, spd->tras,
928 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
929 printf("%-3d : %02x %s\n", 31, spd->rank_dens,
930 " spd->rank_dens, * 31 Density of each rank on module *");
931 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
932 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
933 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
934 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
935 printf("%-3d : %02x %s\n", 34, spd->data_setup,
936 " spd->data_setup, * 34 Data signal input setup time *");
937 printf("%-3d : %02x %s\n", 35, spd->data_hold,
938 " spd->data_hold, * 35 Data signal input hold time *");
939 printf("%-3d : %02x %s\n", 36, spd->twr,
940 " spd->twr, * 36 Write Recovery time tWR *");
941 printf("%-3d : %02x %s\n", 37, spd->twtr,
942 " spd->twtr, * 37 Int write to read delay tWTR *");
943 printf("%-3d : %02x %s\n", 38, spd->trtp,
944 " spd->trtp, * 38 Int read to precharge delay tRTP *");
945 printf("%-3d : %02x %s\n", 39, spd->mem_probe,
946 " spd->mem_probe, * 39 Mem analysis probe characteristics *");
947 printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext,
948 " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
949 printf("%-3d : %02x %s\n", 41, spd->trc,
950 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
951 printf("%-3d : %02x %s\n", 42, spd->trfc,
952 " spd->trfc, * 42 Min Auto to Active period tRFC *");
953 printf("%-3d : %02x %s\n", 43, spd->tckmax,
954 " spd->tckmax, * 43 Max device cycle time tCKmax *");
955 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
956 " spd->tdqsq, * 44 Max DQS to DQ skew *");
957 printf("%-3d : %02x %s\n", 45, spd->tqhs,
958 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
959 printf("%-3d : %02x %s\n", 46, spd->pll_relock,
960 " spd->pll_relock, * 46 PLL Relock time *");
961 printf("%-3d : %02x %s\n", 47, spd->Tcasemax,
962 " spd->Tcasemax, * 47 Tcasemax *");
963 printf("%-3d : %02x %s\n", 48, spd->psiTAdram,
964 " spd->psiTAdram, * 48 Thermal Resistance of DRAM Package "
965 "from Top (Case) to Ambient (Psi T-A DRAM) *");
966 printf("%-3d : %02x %s\n", 49, spd->dt0_mode,
967 " spd->dt0_mode, * 49 DRAM Case Temperature Rise from "
968 "Ambient due to Activate-Precharge/Mode Bits "
969 "(DT0/Mode Bits) *)");
970 printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q,
971 " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from "
972 "Ambient due to Precharge/Quiet Standby "
973 "(DT2N/DT2Q) *");
974 printf("%-3d : %02x %s\n", 51, spd->dt2p,
975 " spd->dt2p, * 51 DRAM Case Temperature Rise from "
976 "Ambient due to Precharge Power-Down (DT2P) *");
977 printf("%-3d : %02x %s\n", 52, spd->dt3n,
978 " spd->dt3n, * 52 DRAM Case Temperature Rise from "
979 "Ambient due to Active Standby (DT3N) *");
980 printf("%-3d : %02x %s\n", 53, spd->dt3pfast,
981 " spd->dt3pfast, * 53 DRAM Case Temperature Rise from "
982 "Ambient due to Active Power-Down with Fast PDN Exit "
983 "(DT3Pfast) *");
984 printf("%-3d : %02x %s\n", 54, spd->dt3pslow,
985 " spd->dt3pslow, * 54 DRAM Case Temperature Rise from "
986 "Ambient due to Active Power-Down with Slow PDN Exit "
987 "(DT3Pslow) *");
988 printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w,
989 " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
990 "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
991 "(DT4R/DT4R4W Mode Bit) *");
992 printf("%-3d : %02x %s\n", 56, spd->dt5b,
993 " spd->dt5b, * 56 DRAM Case Temperature Rise from "
994 "Ambient due to Burst Refresh (DT5B) *");
995 printf("%-3d : %02x %s\n", 57, spd->dt7,
996 " spd->dt7, * 57 DRAM Case Temperature Rise from "
997 "Ambient due to Bank Interleave Reads with "
998 "Auto-Precharge (DT7) *");
999 printf("%-3d : %02x %s\n", 58, spd->psiTApll,
1000 " spd->psiTApll, * 58 Thermal Resistance of PLL Package form"
1001 " Top (Case) to Ambient (Psi T-A PLL) *");
1002 printf("%-3d : %02x %s\n", 59, spd->psiTAreg,
1003 " spd->psiTAreg, * 59 Thermal Reisitance of Register Package"
1004 " from Top (Case) to Ambient (Psi T-A Register) *");
1005 printf("%-3d : %02x %s\n", 60, spd->dtpllactive,
1006 " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1007 "Ambient due to PLL Active (DT PLL Active) *");
1008 printf("%-3d : %02x %s\n", 61, spd->dtregact,
1009 " spd->dtregact, "
1010 "* 61 Register Case Temperature Rise from Ambient due to "
1011 "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1012 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
1013 " spd->spd_rev, * 62 SPD Data Revision Code *");
1014 printf("%-3d : %02x %s\n", 63, spd->cksum,
1015 " spd->cksum, * 63 Checksum for bytes 0-62 *");
1016
1017 printf("%-3d-%3d: ", 64, 71);
1018
1019 for (i = 0; i < 8; i++)
1020 printf("%02x", spd->mid[i]);
1021
1022 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1023
1024 printf("%-3d : %02x %s\n", 72, spd->mloc,
1025 " spd->mloc, * 72 Manufacturing Location *");
1026
1027 printf("%-3d-%3d: >>", 73, 90);
1028 for (i = 0; i < 18; i++)
1029 printf("%c", spd->mpart[i]);
1030
1031
1032 printf("<<* 73 Manufacturer's Part Number *\n");
1033
1034 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1035 "* 91 Revision Code *");
1036 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1037 "* 93 Manufacturing Date *");
1038 printf("%-3d-%3d: ", 95, 98);
1039
1040 for (i = 0; i < 4; i++)
1041 printf("%02x", spd->sernum[i]);
1042
1043 printf("* 95 Assembly Serial Number *\n");
1044
1045 printf("%-3d-%3d: ", 99, 127);
1046 for (i = 0; i < 27; i++)
1047 printf("%02x", spd->mspec[i]);
1048
1049
1050 printf("* 99 Manufacturer Specific Data *\n");
1051}
1052#endif
1053
1054#ifdef CONFIG_FSL_DDR3
1055void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1056{
1057 unsigned int i;
1058
1059 /* General Section: Bytes 0-59 */
1060
1d083ff2 1061#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
6f5e1dc5
YS		 1062#define PRINT_NNXXS(n0, n1, x0, x1, s) \
1063 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1064
1065 PRINT_NXS(0, spd->info_size_crc,
1066 "info_size_crc bytes written into serial memory, "
1067 "CRC coverage");
1068 PRINT_NXS(1, spd->spd_rev,
1069 "spd_rev SPD Revision");
1070 PRINT_NXS(2, spd->mem_type,
1071 "mem_type Key Byte / DRAM Device Type");
1072 PRINT_NXS(3, spd->module_type,
1073 "module_type Key Byte / Module Type");
1074 PRINT_NXS(4, spd->density_banks,
1075 "density_banks SDRAM Density and Banks");
1076 PRINT_NXS(5, spd->addressing,
1077 "addressing SDRAM Addressing");
1078 PRINT_NXS(6, spd->module_vdd,
1079 "module_vdd Module Nominal Voltage, VDD");
1080 PRINT_NXS(7, spd->organization,
1081 "organization Module Organization");
1082 PRINT_NXS(8, spd->bus_width,
1083 "bus_width Module Memory Bus Width");
1084 PRINT_NXS(9, spd->ftb_div,
1085 "ftb_div Fine Timebase (FTB) Dividend / Divisor");
1086 PRINT_NXS(10, spd->mtb_dividend,
1087 "mtb_dividend Medium Timebase (MTB) Dividend");
1088 PRINT_NXS(11, spd->mtb_divisor,
1089 "mtb_divisor Medium Timebase (MTB) Divisor");
1090 PRINT_NXS(12, spd->tCK_min,
1091 "tCK_min SDRAM Minimum Cycle Time");
1092 PRINT_NXS(13, spd->res_13,
1093 "res_13 Reserved");
1094 PRINT_NXS(14, spd->caslat_lsb,
1095 "caslat_lsb CAS Latencies Supported, LSB");
1096 PRINT_NXS(15, spd->caslat_msb,
1097 "caslat_msb CAS Latencies Supported, MSB");
1098 PRINT_NXS(16, spd->tAA_min,
1099 "tAA_min Min CAS Latency Time");
1100 PRINT_NXS(17, spd->tWR_min,
1101 "tWR_min Min Write REcovery Time");
1102 PRINT_NXS(18, spd->tRCD_min,
1103 "tRCD_min Min RAS# to CAS# Delay Time");
1104 PRINT_NXS(19, spd->tRRD_min,
1105 "tRRD_min Min Row Active to Row Active Delay Time");
1106 PRINT_NXS(20, spd->tRP_min,
1107 "tRP_min Min Row Precharge Delay Time");
1108 PRINT_NXS(21, spd->tRAS_tRC_ext,
1109 "tRAS_tRC_ext Upper Nibbles for tRAS and tRC");
1110 PRINT_NXS(22, spd->tRAS_min_lsb,
1111 "tRAS_min_lsb Min Active to Precharge Delay Time, LSB");
1112 PRINT_NXS(23, spd->tRC_min_lsb,
1113 "tRC_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1114 PRINT_NXS(24, spd->tRFC_min_lsb,
1115 "tRFC_min_lsb Min Refresh Recovery Delay Time LSB");
1116 PRINT_NXS(25, spd->tRFC_min_msb,
1117 "tRFC_min_msb Min Refresh Recovery Delay Time MSB");
1118 PRINT_NXS(26, spd->tWTR_min,
1119 "tWTR_min Min Internal Write to Read Command Delay Time");
1120 PRINT_NXS(27, spd->tRTP_min,
1121 "tRTP_min "
1122 "Min Internal Read to Precharge Command Delay Time");
1123 PRINT_NXS(28, spd->tFAW_msb,
1124 "tFAW_msb Upper Nibble for tFAW");
1125 PRINT_NXS(29, spd->tFAW_min,
1126 "tFAW_min Min Four Activate Window Delay Time");
1127 PRINT_NXS(30, spd->opt_features,
1128 "opt_features SDRAM Optional Features");
1129 PRINT_NXS(31, spd->therm_ref_opt,
1130 "therm_ref_opt SDRAM Thermal and Refresh Opts");
1131 PRINT_NXS(32, spd->therm_sensor,
1132 "therm_sensor SDRAM Thermal Sensor");
1133 PRINT_NXS(33, spd->device_type,
1134 "device_type SDRAM Device Type");
73b5396b
YS		 1135 PRINT_NXS(34, spd->fine_tCK_min,
1136 "fine_tCK_min Fine offset for tCKmin");
1137 PRINT_NXS(35, spd->fine_tAA_min,
1138 "fine_tAA_min Fine offset for tAAmin");
1139 PRINT_NXS(36, spd->fine_tRCD_min,
1140 "fine_tRCD_min Fine offset for tRCDmin");
1141 PRINT_NXS(37, spd->fine_tRP_min,
1142 "fine_tRP_min Fine offset for tRPmin");
1143 PRINT_NXS(38, spd->fine_tRC_min,
1144 "fine_tRC_min Fine offset for tRCmin");
1145
1146 printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */
1147
1148 for (i = 39; i <= 59; i++)
1149 printf("%02x ", spd->res_39_59[i - 39]);
6f5e1dc5
YS		 1150
1151 puts("\n");
1152
1153 switch (spd->module_type) {
1154 case 0x02: /* UDIMM */
1155 case 0x03: /* SO-DIMM */
1156 case 0x04: /* Micro-DIMM */
1157 case 0x06: /* Mini-UDIMM */
1158 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1159 "mod_height (Unbuffered) Module Nominal Height");
1160 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1161 "mod_thickness (Unbuffered) Module Maximum Thickness");
1162 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1163 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1164 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1165 "addr_mapping (Unbuffered) Address mapping from "
1166 "Edge Connector to DRAM");
1167 break;
1168 case 0x01: /* RDIMM */
1169 case 0x05: /* Mini-RDIMM */
1170 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1171 "mod_height (Registered) Module Nominal Height");
1172 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1173 "mod_thickness (Registered) Module Maximum Thickness");
1174 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1175 "ref_raw_card (Registered) Reference Raw Card Used");
1176 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1177 "modu_attr (Registered) DIMM Module Attributes");
1178 PRINT_NXS(64, spd->mod_section.registered.thermal,
1179 "thermal (Registered) Thermal Heat "
1180 "Spreader Solution");
1181 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1182 "reg_id_lo (Registered) Register Manufacturer ID "
1183 "Code, LSB");
1184 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1185 "reg_id_hi (Registered) Register Manufacturer ID "
1186 "Code, MSB");
1187 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1188 "reg_rev (Registered) Register "
1189 "Revision Number");
1190 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1191 "reg_type (Registered) Register Type");
1192 for (i = 69; i <= 76; i++) {
1193 printf("%-3d : %02x rcw[%d]\n", i,
1194 spd->mod_section.registered.rcw[i-69], i-69);
1195 }
1196 break;
1197 default:
1198 /* Module-specific Section, Unsupported Module Type */
1199 printf("%-3d-%3d: ", 60, 116);
1200
1201 for (i = 60; i <= 116; i++)
1202 printf("%02x", spd->mod_section.uc[i - 60]);
1203
1204 break;
1205 }
1206
1207 /* Unique Module ID: Bytes 117-125 */
1208 PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1209 PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1210 PRINT_NXS(119, spd->mloc, "Mfg Location");
1211 PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1212
1213 printf("%-3d-%3d: ", 122, 125);
1214
1215 for (i = 122; i <= 125; i++)
1216 printf("%02x ", spd->sernum[i - 122]);
1217 printf(" Module Serial Number\n");
1218
1219 /* CRC: Bytes 126-127 */
1220 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1221
1222 /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1223 printf("%-3d-%3d: ", 128, 145);
1224 for (i = 128; i <= 145; i++)
1225 printf("%02x ", spd->mpart[i - 128]);
1226 printf(" Mfg's Module Part Number\n");
1227
1228 PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1229 "Module Revision code");
1230
1231 PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1232 PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1233
1234 printf("%-3d-%3d: ", 150, 175);
1235 for (i = 150; i <= 175; i++)
1236 printf("%02x ", spd->msd[i - 150]);
1237 printf(" Mfg's Specific Data\n");
1238
1239 printf("%-3d-%3d: ", 176, 255);
1240 for (i = 176; i <= 255; i++)
1241 printf("%02x", spd->cust[i - 176]);
1242 printf(" Mfg's Specific Data\n");
1243
1244}
1245#endif
1246
1247static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1248{
1249#if defined(CONFIG_FSL_DDR1)
1250 ddr1_spd_dump(spd);
1251#elif defined(CONFIG_FSL_DDR2)
1252 ddr2_spd_dump(spd);
1253#elif defined(CONFIG_FSL_DDR3)
1254 ddr3_spd_dump(spd);
1255#endif
1256}
1257
1258static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1259 unsigned int ctrl_mask,
1260 unsigned int dimm_mask,
1261 unsigned int do_mask)
1262{
1263 unsigned int i, j, retval;
1264
1265 /* STEP 1: DIMM SPD data */
1266 if (do_mask & STEP_GET_SPD) {
1267 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1268 if (!(ctrl_mask & (1 << i)))
1269 continue;
1270
1271 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1272 if (!(dimm_mask & (1 << j)))
1273 continue;
1274
1275 printf("SPD info: Controller=%u "
1276 "DIMM=%u\n", i, j);
1277 generic_spd_dump(
1278 &(pinfo->spd_installed_dimms[i][j]));
1279 printf("\n");
1280 }
1281 printf("\n");
1282 }
1283 printf("\n");
1284 }
1285
1286 /* STEP 2: DIMM Parameters */
1287 if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1288 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1289 if (!(ctrl_mask & (1 << i)))
1290 continue;
1291 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1292 if (!(dimm_mask & (1 << j)))
1293 continue;
1294 printf("DIMM parameters: Controller=%u "
1295 "DIMM=%u\n", i, j);
1296 print_dimm_parameters(
1297 &(pinfo->dimm_params[i][j]));
1298 printf("\n");
1299 }
1300 printf("\n");
1301 }
1302 printf("\n");
1303 }
1304
1305 /* STEP 3: Common Parameters */
1306 if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1307 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1308 if (!(ctrl_mask & (1 << i)))
1309 continue;
1310 printf("\"lowest common\" DIMM parameters: "
1311 "Controller=%u\n", i);
1312 print_lowest_common_dimm_parameters(
1313 &pinfo->common_timing_params[i]);
1314 printf("\n");
1315 }
1316 printf("\n");
1317 }
1318
1319 /* STEP 4: User Configuration Options */
1320 if (do_mask & STEP_GATHER_OPTS) {
1321 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1322 if (!(ctrl_mask & (1 << i)))
1323 continue;
1324 printf("User Config Options: Controller=%u\n", i);
1325 print_memctl_options(&pinfo->memctl_opts[i]);
1326 printf("\n");
1327 }
1328 printf("\n");
1329 }
1330
1331 /* STEP 5: Address assignment */
1332 if (do_mask & STEP_ASSIGN_ADDRESSES) {
1333 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1334 if (!(ctrl_mask & (1 << i)))
1335 continue;
1336 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1337 printf("Address Assignment: Controller=%u "
1338 "DIMM=%u\n", i, j);
1339 printf("Don't have this functionality yet\n");
1340 }
1341 printf("\n");
1342 }
1343 printf("\n");
1344 }
1345
1346 /* STEP 6: computed controller register values */
1347 if (do_mask & STEP_COMPUTE_REGS) {
1348 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
1349 if (!(ctrl_mask & (1 << i)))
1350 continue;
1351 printf("Computed Register Values: Controller=%u\n", i);
1352 print_fsl_memctl_config_regs(
1353 &pinfo->fsl_ddr_config_reg[i]);
1354 retval = check_fsl_memctl_config_regs(
1355 &pinfo->fsl_ddr_config_reg[i]);
1356 if (retval) {
1357 printf("check_fsl_memctl_config_regs "
1358 "result = %u\n", retval);
1359 }
1360 printf("\n");
1361 }
1362 printf("\n");
1363 }
1364}
1365
1366struct data_strings {
1367 const char *data_name;
1368 unsigned int step_mask;
1369 unsigned int dimm_number_required;
1370};
1371
1372#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1373
bf418930
JY		 1374static unsigned int fsl_ddr_parse_interactive_cmd(
1375 char **argv,
1376 int argc,
1377 unsigned int *pstep_mask,
1378 unsigned int *pctlr_mask,
1379 unsigned int *pdimm_mask,
1380 unsigned int *pdimm_number_required
1381 ) {
1382
6f5e1dc5
YS		 1383 static const struct data_strings options[] = {
1384 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1385 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1386 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1387 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1388 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1389 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1390 };
1391 static const unsigned int n_opts = ARRAY_SIZE(options);
bf418930
JY		 1392
1393 unsigned int i, j;
1394 unsigned int error = 0;
bf418930
JY		 1395
1396 for (i = 1; i < argc; i++) {
992f2fb2
JY		 1397 unsigned int matched = 0;
1398
bf418930
JY		 1399 for (j = 0; j < n_opts; j++) {
1400 if (strcmp(options[j].data_name, argv[i]) != 0)
1401 continue;
1402 *pstep_mask |= options[j].step_mask;
1403 *pdimm_number_required =
1404 options[j].dimm_number_required;
1405 matched = 1;
1406 break;
1407 }
1408
1409 if (matched)
1410 continue;
1411
1412 if (argv[i][0] == 'c') {
1413 char c = argv[i][1];
1414 if (isdigit(c))
1415 *pctlr_mask |= 1 << (c - '0');
1416 continue;
1417 }
1418
1419 if (argv[i][0] == 'd') {
1420 char c = argv[i][1];
1421 if (isdigit(c))
1422 *pdimm_mask |= 1 << (c - '0');
1423 continue;
1424 }
1425
1426 printf("unknown arg %s\n", argv[i]);
1427 *pstep_mask = 0;
1428 error = 1;
1429 break;
1430 }
1431
1432 return error;
1433}
1434
e8ba6c50
JY		 1435int fsl_ddr_interactive_env_var_exists(void)
1436{
1437 char buffer[CONFIG_SYS_CBSIZE];
1438
1439 if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1440 return 1;
1441
1442 return 0;
1443}
1444
1445unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
bf418930
JY		 1446{
1447 unsigned long long ddrsize;
1448 const char *prompt = "FSL DDR>";
1449 char buffer[CONFIG_SYS_CBSIZE];
e8ba6c50
JY		 1450 char buffer2[CONFIG_SYS_CBSIZE];
1451 char *p = NULL;
bf418930
JY		 1452 char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
1453 int argc;
1454 unsigned int next_step = STEP_GET_SPD;
6f5e1dc5
YS		 1455 const char *usage = {
1456 "commands:\n"
1457 "print print SPD and intermediate computed data\n"
1458 "reset reboot machine\n"
1459 "recompute reload SPD and options to default and recompute regs\n"
1460 "edit modify spd, parameter, or option\n"
1461 "compute recompute registers from current next_step to end\n"
5926ee38 1462 "copy copy parameters\n"
6f5e1dc5
YS		 1463 "next_step shows current next_step\n"
1464 "help this message\n"
1465 "go program the memory controller and continue with u-boot\n"
1466 };
1467
e8ba6c50
JY		 1468 if (var_is_set) {
1469 if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
1470 p = buffer2;
1471 } else {
1472 var_is_set = 0;
1473 }
1474 }
1475
6f5e1dc5
YS		 1476 /*
1477 * The strategy for next_step is that it points to the next
1478 * step in the computation process that needs to be done.
1479 */
1480 while (1) {
e8ba6c50
JY		 1481 if (var_is_set) {
1482 char *pend = strchr(p, ';');
1483 if (pend) {
1484 /* found command separator, copy sub-command */
1485 *pend = '\0';
1486 strcpy(buffer, p);
1487 p = pend + 1;
1488 } else {
1489 /* separator not found, copy whole string */
1490 strcpy(buffer, p);
1491 p = NULL;
1492 var_is_set = 0;
1493 }
1494 } else {
1495 /*
1496 * No need to worry for buffer overflow here in
1497 * this function; readline() maxes out at CFG_CBSIZE
1498 */
1499 readline_into_buffer(prompt, buffer, 0);
1500 }
6f5e1dc5
YS		 1501 argc = parse_line(buffer, argv);
1502 if (argc == 0)
1503 continue;
1504
1505
1506 if (strcmp(argv[0], "help") == 0) {
1507 puts(usage);
1508 continue;
1509 }
1510
1511 if (strcmp(argv[0], "next_step") == 0) {
1512 printf("next_step = 0x%02X (%s)\n",
1513 next_step,
1514 step_to_string(next_step));
1515 continue;
1516 }
1517
5926ee38
JY		 1518 if (strcmp(argv[0], "copy") == 0) {
1519 unsigned int error = 0;
1520 unsigned int step_mask = 0;
1521 unsigned int src_ctlr_mask = 0;
1522 unsigned int src_dimm_mask = 0;
1523 unsigned int dimm_number_required = 0;
1524 unsigned int src_ctlr_num = 0;
1525 unsigned int src_dimm_num = 0;
1526 unsigned int dst_ctlr_num = -1;
1527 unsigned int dst_dimm_num = -1;
1528 unsigned int i, num_dest_parms;
1529
1530 if (argc == 1) {
1531 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1532 continue;
1533 }
1534
1535 error = fsl_ddr_parse_interactive_cmd(
1536 argv, argc,
1537 &step_mask,
1538 &src_ctlr_mask,
1539 &src_dimm_mask,
1540 &dimm_number_required
1541 );
1542
1543 /* XXX: only dimm_number_required and step_mask will
1544 be used by this function. Parse the controller and
1545 DIMM number separately because it is easier. */
1546
1547 if (error)
1548 continue;
1549
1550 /* parse source destination controller / DIMM */
1551
1552 num_dest_parms = dimm_number_required ? 2 : 1;
1553
1554 for (i = 0; i < argc; i++) {
1555 if (argv[i][0] == 'c') {
1556 char c = argv[i][1];
1557 if (isdigit(c)) {
1558 src_ctlr_num = (c - '0');
1559 break;
1560 }
1561 }
1562 }
1563
1564 for (i = 0; i < argc; i++) {
1565 if (argv[i][0] == 'd') {
1566 char c = argv[i][1];
1567 if (isdigit(c)) {
1568 src_dimm_num = (c - '0');
1569 break;
1570 }
1571 }
1572 }
1573
1574 /* parse destination controller / DIMM */
1575
1576 for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1577 if (argv[i][0] == 'c') {
1578 char c = argv[i][1];
1579 if (isdigit(c)) {
1580 dst_ctlr_num = (c - '0');
1581 break;
1582 }
1583 }
1584 }
1585
1586 for (i = argc - 1; i >= argc - num_dest_parms; i--) {
1587 if (argv[i][0] == 'd') {
1588 char c = argv[i][1];
1589 if (isdigit(c)) {
1590 dst_dimm_num = (c - '0');
1591 break;
1592 }
1593 }
1594 }
1595
1596 /* TODO: validate inputs */
1597
1598 debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
1599 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
1600
1601
1602 switch (step_mask) {
1603
1604 case STEP_GET_SPD:
1605 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
1606 &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
1607 sizeof(pinfo->spd_installed_dimms[0][0]));
1608 break;
1609
1610 case STEP_COMPUTE_DIMM_PARMS:
1611 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
1612 &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
1613 sizeof(pinfo->dimm_params[0][0]));
1614 break;
1615
1616 case STEP_COMPUTE_COMMON_PARMS:
1617 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
1618 &(pinfo->common_timing_params[src_ctlr_num]),
1619 sizeof(pinfo->common_timing_params[0]));
1620 break;
1621
1622 case STEP_GATHER_OPTS:
1623 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
1624 &(pinfo->memctl_opts[src_ctlr_num]),
1625 sizeof(pinfo->memctl_opts[0]));
1626 break;
1627
1628 /* someday be able to have addresses to copy addresses... */
1629
1630 case STEP_COMPUTE_REGS:
1631 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
1632 &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
1633 sizeof(pinfo->memctl_opts[0]));
1634 break;
1635
1636 default:
1637 printf("unexpected step_mask value\n");
1638 }
1639
1640 continue;
1641
1642 }
1643
6f5e1dc5 1644 if (strcmp(argv[0], "edit") == 0) {
6f5e1dc5
YS		 1645 unsigned int error = 0;
1646 unsigned int step_mask = 0;
1647 unsigned int ctlr_mask = 0;
1648 unsigned int dimm_mask = 0;
1649 char *p_element = NULL;
1650 char *p_value = NULL;
1651 unsigned int dimm_number_required = 0;
1652 unsigned int ctrl_num;
1653 unsigned int dimm_num;
6f5e1dc5
YS		 1654
1655 if (argc == 1) {
1656 /* Only the element and value must be last */
1657 printf("edit <c#> <d#> "
1658 "<spd|dimmparms|commonparms|opts|"
1659 "addresses|regs> <element> <value>\n");
1660 printf("for spd, specify byte number for "
1661 "element\n");
1662 continue;
1663 }
1664
bf418930
JY		 1665 error = fsl_ddr_parse_interactive_cmd(
1666 argv, argc - 2,
1667 &step_mask,
1668 &ctlr_mask,
1669 &dimm_mask,
1670 &dimm_number_required
1671 );
6f5e1dc5
YS		 1672
1673 if (error)
1674 continue;
1675
1676
1677 /* Check arguments */
1678
1679 /* ERROR: If no steps were found */
1680 if (step_mask == 0) {
1681 printf("Error: No valid steps were specified "
1682 "in argument.\n");
1683 continue;
1684 }
1685
1686 /* ERROR: If multiple steps were found */
1687 if (step_mask & (step_mask - 1)) {
1688 printf("Error: Multiple steps specified in "
1689 "argument.\n");
1690 continue;
1691 }
1692
1693 /* ERROR: Controller not specified */
1694 if (ctlr_mask == 0) {
1695 printf("Error: controller number not "
1696 "specified or no element and "
1697 "value specified\n");
1698 continue;
1699 }
1700
1701 if (ctlr_mask & (ctlr_mask - 1)) {
1702 printf("Error: multiple controllers "
1703 "specified, %X\n", ctlr_mask);
1704 continue;
1705 }
1706
1707 /* ERROR: DIMM number not specified */
1708 if (dimm_number_required && dimm_mask == 0) {
1709 printf("Error: DIMM number number not "
1710 "specified or no element and "
1711 "value specified\n");
1712 continue;
1713 }
1714
1715 if (dimm_mask & (dimm_mask - 1)) {
1716 printf("Error: multipled DIMMs specified\n");
1717 continue;
1718 }
1719
1720 p_element = argv[argc - 2];
1721 p_value = argv[argc - 1];
1722
1723 ctrl_num = __ilog2(ctlr_mask);
1724 dimm_num = __ilog2(dimm_mask);
1725
1726 switch (step_mask) {
1727 case STEP_GET_SPD:
1728 {
1729 unsigned int element_num;
1730 unsigned int value;
1731
1732 element_num = simple_strtoul(p_element,
1733 NULL, 0);
1734 value = simple_strtoul(p_value,
1735 NULL, 0);
1736 fsl_ddr_spd_edit(pinfo,
1737 ctrl_num,
1738 dimm_num,
1739 element_num,
1740 value);
1741 next_step = STEP_COMPUTE_DIMM_PARMS;
1742 }
1743 break;
1744
1745 case STEP_COMPUTE_DIMM_PARMS:
1746 fsl_ddr_dimm_parameters_edit(
1747 pinfo, ctrl_num, dimm_num,
1748 p_element, p_value);
1749 next_step = STEP_COMPUTE_COMMON_PARMS;
1750 break;
1751
1752 case STEP_COMPUTE_COMMON_PARMS:
1753 lowest_common_dimm_parameters_edit(pinfo,
1754 ctrl_num, p_element, p_value);
1755 next_step = STEP_GATHER_OPTS;
1756 break;
1757
1758 case STEP_GATHER_OPTS:
1759 fsl_ddr_options_edit(pinfo, ctrl_num,
1760 p_element, p_value);
1761 next_step = STEP_ASSIGN_ADDRESSES;
1762 break;
1763
1764 case STEP_ASSIGN_ADDRESSES:
1765 printf("editing of address assignment "
1766 "not yet implemented\n");
1767 break;
1768
1769 case STEP_COMPUTE_REGS:
1770 {
1771 fsl_ddr_regs_edit(pinfo,
1772 ctrl_num,
1773 p_element,
1774 p_value);
1775 next_step = STEP_PROGRAM_REGS;
1776 }
1777 break;
1778
1779 default:
1780 printf("programming error\n");
1781 while (1)
1782 ;
1783 break;
1784 }
1785 continue;
1786 }
1787
1788 if (strcmp(argv[0], "reset") == 0) {
1789 /*
1790 * Reboot machine.
1791 * Args don't seem to matter because this
1792 * doesn't return
1793 */
1794 do_reset(NULL, 0, 0, NULL);
57495e4e 1795 printf("Reset didn't work\n");
6f5e1dc5
YS		 1796 }
1797
1798 if (strcmp(argv[0], "recompute") == 0) {
1799 /*
1800 * Recalculate everything, starting with
1801 * loading SPD EEPROM from DIMMs
1802 */
1803 next_step = STEP_GET_SPD;
1804 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1805 continue;
1806 }
1807
1808 if (strcmp(argv[0], "compute") == 0) {
1809 /*
1810 * Compute rest of steps starting at
1811 * the current next_step/
1812 */
1813 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1814 continue;
1815 }
1816
1817 if (strcmp(argv[0], "print") == 0) {
6f5e1dc5
YS		 1818 unsigned int error = 0;
1819 unsigned int step_mask = 0;
1820 unsigned int ctlr_mask = 0;
1821 unsigned int dimm_mask = 0;
bf418930 1822 unsigned int dimm_number_required = 0;
6f5e1dc5
YS		 1823
1824 if (argc == 1) {
1825 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
1826 "[commonparms] [opts] [addresses] [regs]\n");
1827 continue;
1828 }
1829
bf418930
JY		 1830 error = fsl_ddr_parse_interactive_cmd(
1831 argv, argc,
1832 &step_mask,
1833 &ctlr_mask,
1834 &dimm_mask,
1835 &dimm_number_required
1836 );
6f5e1dc5
YS		 1837
1838 if (error)
1839 continue;
1840
1841 /* If no particular controller was found, print all */
1842 if (ctlr_mask == 0)
1843 ctlr_mask = 0xFF;
1844
1845 /* If no particular dimm was found, print all dimms. */
1846 if (dimm_mask == 0)
1847 dimm_mask = 0xFF;
1848
1849 /* If no steps were found, print all steps. */
1850 if (step_mask == 0)
1851 step_mask = STEP_ALL;
1852
1853 fsl_ddr_printinfo(pinfo, ctlr_mask,
1854 dimm_mask, step_mask);
1855 continue;
1856 }
1857
1858 if (strcmp(argv[0], "go") == 0) {
1859 if (next_step)
1860 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
1861 break;
1862 }
1863
1864 printf("unknown command %s\n", argv[0]);
1865 }
1866
1867 debug("end of memory = %llu\n", (u64)ddrsize);
1868
1869 return ddrsize;
1870}
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