[J-u-boot.git] / arch / powerpc / cpu / mpc5xx / start.S

/*
 *  Copyright (C) 1998	Dan Malek <[email protected]>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000, 2001, 2002 Wolfgang Denk <[email protected]>
 *  Copyright (C) 2003  Martin Winistoerfer, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * File:		start.S
 *
 * Discription:		startup code
 *
 */

#include <asm-offsets.h>
#include <config.h>
#include <mpc5xx.h>
#include <timestamp.h>
#include <version.h>

#define CONFIG_5xx 1		/* needed for Linux kernel header files */
#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <linux/config.h>
#include <asm/processor.h>
#include <asm/u-boot.h>

#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING ""
#endif

/* We don't have a MMU.
*/
#undef	MSR_KERNEL
#define MSR_KERNEL ( MSR_ME | MSR_RI )		/* Machine Check and Recoverable Interr. */

/*
 * Set up GOT: Global Offset Table
 *
 * Use r12 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(_end)
	GOT_ENTRY(__bss_start)
	END_GOT

/*
 * r3 - 1st arg to board_init(): IMMP pointer
 * r4 - 2nd arg to board_init(): boot flag
 */
	.text
	.long	0x27051956			/* U-Boot Magic Number */
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
	.ascii CONFIG_IDENT_STRING, "\0"

	. = EXC_OFF_SYS_RESET
	.globl	_start
_start:
	mfspr	r3, 638
	li	r4, CONFIG_SYS_ISB			/* Set ISB bit */
	or	r3, r3, r4
	mtspr	638, r3

	/* Initialize machine status; enable machine check interrupt		*/
	/*----------------------------------------------------------------------*/
	li	r3, MSR_KERNEL			/* Set ME, RI flags */
	mtmsr	r3
	mtspr	SRR1, r3			/* Make SRR1 match MSR */

	/* Initialize debug port registers					*/
	/*----------------------------------------------------------------------*/
	xor	r0, r0, r0			/* Clear R0 */
	mtspr	LCTRL1, r0			/* Initialize debug port regs */
	mtspr	LCTRL2, r0
	mtspr	COUNTA, r0
	mtspr	COUNTB, r0

#if defined(CONFIG_PATI)
	/* the external flash access on PATI fails if programming the PLL to 40MHz.
	 * Copy the PLL programming code to the internal RAM and execute it
	 *----------------------------------------------------------------------*/
	lis	r3, CONFIG_SYS_MONITOR_BASE@h
	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
	addi	r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET

	lis	r4, CONFIG_SYS_INIT_RAM_ADDR@h
	ori	r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
	mtlr	r4
	addis	r5,0,0x0
	ori	r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
	mtctr	r5
	addi	r3, r3, -4
	addi	r4, r4, -4
0:
	lwzu	r0,4(r3)
	stwu	r0,4(r4)
	bdnz	0b                /* copy loop */
	blrl
#endif

	/*
	 * Calculate absolute address in FLASH and jump there
	 *----------------------------------------------------------------------*/

	lis	r3, CONFIG_SYS_MONITOR_BASE@h
	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r3
	blr

in_flash:

	/* Initialize some SPRs that are hard to access from C			*/
	/*----------------------------------------------------------------------*/

	lis     r3, CONFIG_SYS_IMMR@h			/* Pass IMMR as arg1 to C routine */
	lis	r2, CONFIG_SYS_INIT_SP_ADDR@h
	ori	r1, r2, CONFIG_SYS_INIT_SP_ADDR@l	/* Set up the stack in internal SRAM */
	/* Note: R0 is still 0 here */
	stwu	r0, -4(r1)			/* Clear final stack frame so that	*/
	stwu	r0, -4(r1)			/* stack backtraces terminate cleanly	*/

	/*
	 * Disable serialized ifetch and show cycles
	 * (i.e. set processor to normal mode) for maximum
	 * performance.
	 */

	li	r2, 0x0007
	mtspr	ICTRL, r2

	/* Set up debug mode entry */

	lis	r2, CONFIG_SYS_DER@h
	ori	r2, r2, CONFIG_SYS_DER@l
	mtspr	DER, r2

	/* Let the C-code set up the rest					*/
	/*									*/
	/* Be careful to keep code relocatable !				*/
	/*----------------------------------------------------------------------*/

	GET_GOT			/* initialize GOT access			*/

	/* r3: IMMR */
	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/

	bl	board_init_f	/* run 1st part of board init code (from Flash) */

	/* NOTREACHED - board_init_f() does not return */


	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG(SRR0, SRR1)
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG(SRR0, SRR1)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
		MSR_KERNEL, COPY_EE)

	/* FPU on MPC5xx available. We will use it later.
	*/
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

	/* I guess we could implement decrementer, and may have
	 * to someday for timekeeping.
	 */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
	STD_EXCEPTION(0xd00, SingleStep, UnknownException)

	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)

	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
	 * for all unimplemented and illegal instructions.
	 */
	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)

	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)

	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)


	.globl	_end_of_vectors
_end_of_vectors:


	. = 0x2000

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	mtspr	SPRG2,r22		/* r1 is now kernel sp */
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28			/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC				/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)		/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi


/*
 * unsigned int get_immr (unsigned int mask)
 *
 * return (mask ? (IMMR & mask) : IMMR);
 */
	.globl	get_immr
get_immr:
	mr	r4,r3		/* save mask */
	mfspr	r3, IMMR	/* IMMR */
	cmpwi	0,r4,0		/* mask != 0 ? */
	beq	4f
	and	r3,r3,r4	/* IMMR & mask */
4:
	blr

	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr


/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	mr	r1,  r3		/* Set new stack pointer in SRAM	*/
	mr	r9,  r4		/* Save copy of global data pointer in SRAM */
	mr	r10, r5		/* Save copy of monitor destination Address in SRAM */

	GET_GOT
	mr	r3,  r5				/* Destination Address	*/
	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
	lwz	r5, GOT(__init_end)
	sub	r5, r5, r4

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4

	/* First our own GOT */
	add	r12, r12, r15
	/* the the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */

	cmplw	cr1,r3,r4
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary	*/
	beq	4f		/* Protect against 0 count		*/
	mtctr	r0
	bge	cr1,2f

	la	r8,-4(r4)
	la	r7,-4(r3)
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b
	b	4f

2:	slwi	r0,r0,2
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

4:	sync
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */

	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:

	/*
	 * Relocation Function, r12 point to got2+0x8000
	 *
	 * Adjust got2 pointers, no need to check for 0, this code
	 * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	cmpwi	r0,0
	beq-	2f
	add	r0,r0,r11
	stw	r0,0(r3)
2:	bdnz	1b

	/*
	 * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */
	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	cmpwi	r0,0
	add	r0,r0,r11
	stw	r10,0(r3)
	beq-	5f
	stw	r0,0(r4)
5:	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(__bss_start)
	lwz	r4,GOT(_end)
	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	bne	5b
6:

	mr	r3, r9		/* Global Data pointer		*/
	mr	r4, r10		/* Destination Address		*/
	bl	board_init_r

	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	mflr	r4			/* save link register		*/
	GET_GOT
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100		/* reset vector always at 0x100 */

	cmplw	0, r7, r8
	bgelr				/* return if r7>=r8 - just in case */
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	3b

	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	4b

	mtlr	r4			/* restore link register	*/
	blr

#if defined(CONFIG_PATI)
/* Program the PLL */
pll_prog_code_start:
	lis	r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
	ori	r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
	lis	r3, (0x55ccaa33)@h
	ori	r3, r3, (0x55ccaa33)@l
	stw	r3, 0(r4)
	lis	r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
	ori	r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
	lis	r3, CONFIG_SYS_PLPRCR@h
	ori	r3, r3, CONFIG_SYS_PLPRCR@l
	stw	r3, 0(r4)
	addis	r3,0,0x0
	ori	r3,r3,0xA000
	mtctr	r3
..spinlp:
  bdnz    ..spinlp                /* spin loop */
	blr
pll_prog_code_end:
	nop
	blr
#endif
Commit	Line	Data
0db5bca8 WD	1	/*
	2	* Copyright (C) 1998 Dan Malek <[email protected]>
	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
	4	* Copyright (C) 2000, 2001, 2002 Wolfgang Denk <[email protected]>
	5	* Copyright (C) 2003 Martin Winistoerfer, [email protected].
8bde7f77	6	*
0db5bca8 WD	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* File: start.S
8bde7f77	28	*
0db5bca8 WD	29	* Discription: startup code
	30	*
	31	*/
	32
25ddd1fb	33	#include <asm-offsets.h>
0db5bca8 WD	34	#include <config.h>
0db5bca8 WD	35	#include <mpc5xx.h>
561858ee	36	#include <timestamp.h>
0db5bca8 WD	37	#include <version.h>
	38
	39	#define CONFIG_5xx 1 /* needed for Linux kernel header files */
	40	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	41
	42	#include <ppc_asm.tmpl>
	43	#include <ppc_defs.h>
8bde7f77	44
0db5bca8	45	#include <linux/config.h>
8bde7f77	46	#include <asm/processor.h>
d98b0523	47	#include <asm/u-boot.h>
0db5bca8 WD	48
	49	#ifndef CONFIG_IDENT_STRING
	50	#define CONFIG_IDENT_STRING ""
	51	#endif
	52
	53	/* We don't have a MMU.
	54	*/
	55	#undef MSR_KERNEL
	56	#define MSR_KERNEL ( MSR_ME \| MSR_RI ) /* Machine Check and Recoverable Interr. */
	57
	58	/*
	59	* Set up GOT: Global Offset Table
	60	*
0f8aa159	61	* Use r12 to access the GOT
0db5bca8 WD	62	*/
	63	START_GOT
	64	GOT_ENTRY(_GOT2_TABLE_)
	65	GOT_ENTRY(_FIXUP_TABLE_)
	66
	67	GOT_ENTRY(_start)
	68	GOT_ENTRY(_start_of_vectors)
	69	GOT_ENTRY(_end_of_vectors)
	70	GOT_ENTRY(transfer_to_handler)
	71
3b57fe0a	72	GOT_ENTRY(__init_end)
0db5bca8	73	GOT_ENTRY(_end)
5d232d0e	74	GOT_ENTRY(__bss_start)
0db5bca8 WD	75	END_GOT
	76
	77	/*
	78	* r3 - 1st arg to board_init(): IMMP pointer
	79	* r4 - 2nd arg to board_init(): boot flag
	80	*/
	81	.text
	82	.long 0x27051956 /* U-Boot Magic Number */
	83	.globl version_string
	84	version_string:
	85	.ascii U_BOOT_VERSION
561858ee	86	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
0db5bca8 WD	87	.ascii CONFIG_IDENT_STRING, "\0"
	88
	89	. = EXC_OFF_SYS_RESET
	90	.globl _start
	91	_start:
	92	mfspr r3, 638
6d0f6bcf	93	li r4, CONFIG_SYS_ISB /* Set ISB bit */
8bde7f77	94	or r3, r3, r4
0db5bca8	95	mtspr 638, r3
0db5bca8 WD	96
	97	/* Initialize machine status; enable machine check interrupt */
	98	/----------------------------------------------------------------------/
	99	li r3, MSR_KERNEL /* Set ME, RI flags */
	100	mtmsr r3
	101	mtspr SRR1, r3 /* Make SRR1 match MSR */
	102
	103	/* Initialize debug port registers */
	104	/----------------------------------------------------------------------/
	105	xor r0, r0, r0 /* Clear R0 */
	106	mtspr LCTRL1, r0 /* Initialize debug port regs */
	107	mtspr LCTRL2, r0
	108	mtspr COUNTA, r0
	109	mtspr COUNTB, r0
	110
b6e4c403 WD	111	#if defined(CONFIG_PATI)
	112	/* the external flash access on PATI fails if programming the PLL to 40MHz.
	113	* Copy the PLL programming code to the internal RAM and execute it
	114	----------------------------------------------------------------------/
6d0f6bcf JCPV	115	lis r3, CONFIG_SYS_MONITOR_BASE@h
6d0f6bcf JCPV	116	ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
b6e4c403 WD	117	addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
b6e4c403 WD	118
6d0f6bcf JCPV	119	lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
6d0f6bcf JCPV	120	ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
b6e4c403 WD	121	mtlr r4
	122	addis r5,0,0x0
	123	ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
	124	mtctr r5
	125	addi r3, r3, -4
	126	addi r4, r4, -4
	127	0:
	128	lwzu r0,4(r3)
	129	stwu r0,4(r4)
	130	bdnz 0b /* copy loop */
	131	blrl
	132	#endif
	133
0db5bca8 WD	134	/*
	135	* Calculate absolute address in FLASH and jump there
	136	----------------------------------------------------------------------/
	137
6d0f6bcf JCPV	138	lis r3, CONFIG_SYS_MONITOR_BASE@h
6d0f6bcf JCPV	139	ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
0db5bca8 WD	140	addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	141	mtlr r3
	142	blr
	143
	144	in_flash:
	145
	146	/* Initialize some SPRs that are hard to access from C */
	147	/----------------------------------------------------------------------/
8bde7f77	148
6d0f6bcf JCPV	149	lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */
	150	lis r2, CONFIG_SYS_INIT_SP_ADDR@h
	151	ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
0db5bca8 WD	152	/* Note: R0 is still 0 here */
	153	stwu r0, -4(r1) /* Clear final stack frame so that */
	154	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
	155
	156	/*
	157	* Disable serialized ifetch and show cycles
	158	* (i.e. set processor to normal mode) for maximum
	159	* performance.
	160	*/
	161
	162	li r2, 0x0007
	163	mtspr ICTRL, r2
	164
	165	/* Set up debug mode entry */
	166
6d0f6bcf JCPV	167	lis r2, CONFIG_SYS_DER@h
6d0f6bcf JCPV	168	ori r2, r2, CONFIG_SYS_DER@l
0db5bca8 WD	169	mtspr DER, r2
	170
	171	/* Let the C-code set up the rest */
	172	/* */
	173	/* Be careful to keep code relocatable ! */
	174	/----------------------------------------------------------------------/
	175
	176	GET_GOT /* initialize GOT access */
	177
	178	/* r3: IMMR */
	179	bl cpu_init_f /* run low-level CPU init code (from Flash) */
	180
0db5bca8 WD	181	bl board_init_f /* run 1st part of board init code (from Flash) */
0db5bca8 WD	182
52ebd9c1 PT	183	/* NOTREACHED - board_init_f() does not return */
52ebd9c1 PT	184
0db5bca8	185
0db5bca8 WD	186	.globl _start_of_vectors
	187	_start_of_vectors:
	188
	189	/* Machine check */
	190	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
	191
	192	/* Data Storage exception. "Never" generated on the 860. */
	193	STD_EXCEPTION(0x300, DataStorage, UnknownException)
	194
	195	/* Instruction Storage exception. "Never" generated on the 860. */
	196	STD_EXCEPTION(0x400, InstStorage, UnknownException)
	197
	198	/* External Interrupt exception. */
	199	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
	200
	201	/* Alignment exception. */
	202	. = 0x600
	203	Alignment:
02032e8f	204	EXCEPTION_PROLOG(SRR0, SRR1)
0db5bca8 WD	205	mfspr r4,DAR
	206	stw r4,_DAR(r21)
	207	mfspr r5,DSISR
	208	stw r5,_DSISR(r21)
	209	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887	210	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
0db5bca8 WD	211
	212	/* Program check exception */
	213	. = 0x700
	214	ProgramCheck:
02032e8f	215	EXCEPTION_PROLOG(SRR0, SRR1)
0db5bca8	216	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887 JT	217	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
fc4e1887 JT	218	MSR_KERNEL, COPY_EE)
0db5bca8 WD	219
	220	/* FPU on MPC5xx available. We will use it later.
	221	*/
	222	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
	223
	224	/* I guess we could implement decrementer, and may have
	225	* to someday for timekeeping.
	226	*/
	227	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	228	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	229	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
27b207fd	230	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
0db5bca8 WD	231	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
	232
	233	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	234	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
	235
	236	/* On the MPC8xx, this is a software emulation interrupt. It occurs
	237	* for all unimplemented and illegal instructions.
	238	*/
	239	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
	240	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	241	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	242	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	243	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
	244
	245	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	246	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	247	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	248	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	249	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	250	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	251	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
	252
	253	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	254	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
	255	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	256	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
	257
	258
	259	.globl _end_of_vectors
	260	_end_of_vectors:
	261
	262
	263	. = 0x2000
	264
	265	/*
	266	* This code finishes saving the registers to the exception frame
	267	* and jumps to the appropriate handler for the exception.
	268	* Register r21 is pointer into trap frame, r1 has new stack pointer.
	269	*/
	270	.globl transfer_to_handler
	271	transfer_to_handler:
	272	stw r22,_NIP(r21)
	273	lis r22,MSR_POW@h
	274	andc r23,r23,r22
	275	stw r23,_MSR(r21)
	276	SAVE_GPR(7, r21)
	277	SAVE_4GPRS(8, r21)
	278	SAVE_8GPRS(12, r21)
	279	SAVE_8GPRS(24, r21)
	280	mflr r23
	281	andi. r24,r23,0x3f00 /* get vector offset */
	282	stw r24,TRAP(r21)
	283	li r22,0
	284	stw r22,RESULT(r21)
	285	mtspr SPRG2,r22 /* r1 is now kernel sp */
	286	lwz r24,0(r23) /* virtual address of handler */
	287	lwz r23,4(r23) /* where to go when done */
	288	mtspr SRR0,r24
	289	mtspr SRR1,r20
	290	mtlr r23
	291	SYNC
	292	rfi /* jump to handler, enable MMU */
	293
	294	int_return:
295	mfmsr r28 /* Disable interrupts */
296	li r4,0
297	ori r4,r4,MSR_EE
298	andc r28,r28,r4
299	SYNC /* Some chip revs need this... */
300	mtmsr r28
301	SYNC
302	lwz r2,_CTR(r1)
303	lwz r0,_LINK(r1)
304	mtctr r2
305	mtlr r0
306	lwz r2,_XER(r1)
307	lwz r0,_CCR(r1)
308	mtspr XER,r2
309	mtcrf 0xFF,r0
310	REST_10GPRS(3, r1)
311	REST_10GPRS(13, r1)
312	REST_8GPRS(23, r1)
313	REST_GPR(31, r1)
314	lwz r2,_NIP(r1) /* Restore environment */
315	lwz r0,_MSR(r1)
316	mtspr SRR0,r2
317	mtspr SRR1,r0
318	lwz r0,GPR0(r1)
319	lwz r2,GPR2(r1)
320	lwz r1,GPR1(r1)
321	SYNC
322	rfi
323
8bde7f77	324
0db5bca8 WD	325	/*
	326	* unsigned int get_immr (unsigned int mask)
	327	*
	328	* return (mask ? (IMMR & mask) : IMMR);
	329	*/
	330	.globl get_immr
	331	get_immr:
	332	mr r4,r3 /* save mask */
	333	mfspr r3, IMMR /* IMMR */
	334	cmpwi 0,r4,0 /* mask != 0 ? */
	335	beq 4f
	336	and r3,r3,r4 /* IMMR & mask */
	337	4:
	338	blr
	339
	340	.globl get_pvr
	341	get_pvr:
	342	mfspr r3, PVR
	343	blr
	344
	345
	346	/------------------------------------------------------------------------------/
	347
	348	/*
	349	* void relocate_code (addr_sp, gd, addr_moni)
	350	*
	351	* This "function" does not return, instead it continues in RAM
	352	* after relocating the monitor code.
	353	*
	354	* r3 = dest
	355	* r4 = src
	356	* r5 = length in bytes
	357	* r6 = cachelinesize
	358	*/
	359	.globl relocate_code
	360	relocate_code:
	361	mr r1, r3 /* Set new stack pointer in SRAM */
	362	mr r9, r4 /* Save copy of global data pointer in SRAM */
	363	mr r10, r5 /* Save copy of monitor destination Address in SRAM */
	364
0f8aa159	365	GET_GOT
0db5bca8	366	mr r3, r5 /* Destination Address */
6d0f6bcf JCPV	367	lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
6d0f6bcf JCPV	368	ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
3b57fe0a WD	369	lwz r5, GOT(__init_end)
3b57fe0a WD	370	sub r5, r5, r4
0db5bca8 WD	371
	372	/*
	373	* Fix GOT pointer:
	374	*
6d0f6bcf	375	* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
0db5bca8 WD	376	*
	377	* Offset:
	378	*/
	379	sub r15, r10, r4
	380
	381	/* First our own GOT */
0f8aa159	382	add r12, r12, r15
0db5bca8 WD	383	/* the the one used by the C code */
	384	add r30, r30, r15
	385
	386	/*
	387	* Now relocate code
	388	*/
	389
	390	cmplw cr1,r3,r4
	391	addi r0,r5,3
	392	srwi. r0,r0,2
	393	beq cr1,4f /* In place copy is not necessary */
	394	beq 4f /* Protect against 0 count */
	395	mtctr r0
	396	bge cr1,2f
	397
	398	la r8,-4(r4)
	399	la r7,-4(r3)
	400	1: lwzu r0,4(r8)
	401	stwu r0,4(r7)
	402	bdnz 1b
	403	b 4f
	404
	405	2: slwi r0,r0,2
	406	add r8,r4,r0
	407	add r7,r3,r0
	408	3: lwzu r0,-4(r8)
	409	stwu r0,-4(r7)
	410	bdnz 3b
	411
8bde7f77	412	4: sync
0db5bca8 WD	413	isync
	414
	415	/*
	416	* We are done. Do not return, instead branch to second part of board
	417	* initialization, now running from RAM.
	418	*/
	419
	420	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	421	mtlr r0
	422	blr
	423
	424	in_ram:
	425
	426	/*
0f8aa159	427	* Relocation Function, r12 point to got2+0x8000
0db5bca8	428	*
8bde7f77 WD	429	* Adjust got2 pointers, no need to check for 0, this code
8bde7f77 WD	430	* already puts a few entries in the table.
0db5bca8 WD	431	*/
	432	li r0,__got2_entries@sectoff@l
	433	la r3,GOT(_GOT2_TABLE_)
	434	lwz r11,GOT(_GOT2_TABLE_)
	435	mtctr r0
	436	sub r11,r3,r11
	437	addi r3,r3,-4
	438	1: lwzu r0,4(r3)
afc3ba0f JT	439	cmpwi r0,0
afc3ba0f JT	440	beq- 2f
0db5bca8 WD	441	add r0,r0,r11
0db5bca8 WD	442	stw r0,0(r3)
afc3ba0f	443	2: bdnz 1b
0db5bca8 WD	444
0db5bca8 WD	445	/*
8bde7f77	446	* Now adjust the fixups and the pointers to the fixups
0db5bca8 WD	447	* in case we need to move ourselves again.
0db5bca8 WD	448	*/
afc3ba0f	449	li r0,__fixup_entries@sectoff@l
0db5bca8 WD	450	lwz r3,GOT(_FIXUP_TABLE_)
	451	cmpwi r0,0
	452	mtctr r0
	453	addi r3,r3,-4
	454	beq 4f
	455	3: lwzu r4,4(r3)
	456	lwzux r0,r4,r11
d1e0b10a	457	cmpwi r0,0
0db5bca8 WD	458	add r0,r0,r11
0db5bca8 WD	459	stw r10,0(r3)
d1e0b10a	460	beq- 5f
0db5bca8	461	stw r0,0(r4)
d1e0b10a	462	5: bdnz 3b
0db5bca8 WD	463	4:
	464	clear_bss:
	465	/*
	466	* Now clear BSS segment
	467	*/
5d232d0e	468	lwz r3,GOT(__bss_start)
0db5bca8 WD	469	lwz r4,GOT(_end)
	470	cmplw 0, r3, r4
	471	beq 6f
	472
	473	li r0, 0
	474	5:
	475	stw r0, 0(r3)
	476	addi r3, r3, 4
	477	cmplw 0, r3, r4
	478	bne 5b
	479	6:
	480
	481	mr r3, r9 /* Global Data pointer */
	482	mr r4, r10 /* Destination Address */
	483	bl board_init_r
	484
0db5bca8 WD	485	/*
	486	* Copy exception vector code to low memory
	487	*
	488	* r3: dest_addr
	489	* r7: source address, r8: end address, r9: target address
	490	*/
	491	.globl trap_init
	492	trap_init:
0f8aa159 JT	493	mflr r4 /* save link register */
0f8aa159 JT	494	GET_GOT
0db5bca8 WD	495	lwz r7, GOT(_start)
	496	lwz r8, GOT(_end_of_vectors)
	497
682011ff	498	li r9, 0x100 /* reset vector always at 0x100 */
0db5bca8 WD	499
	500	cmplw 0, r7, r8
	501	bgelr /* return if r7>=r8 - just in case */
0db5bca8 WD	502	1:
	503	lwz r0, 0(r7)
	504	stw r0, 0(r9)
	505	addi r7, r7, 4
	506	addi r9, r9, 4
	507	cmplw 0, r7, r8
	508	bne 1b
	509
	510	/*
	511	* relocate `hdlr' and `int_return' entries
	512	*/
	513	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	514	li r8, Alignment - _start + EXC_OFF_SYS_RESET
	515	2:
	516	bl trap_reloc
	517	addi r7, r7, 0x100 /* next exception vector */
	518	cmplw 0, r7, r8
	519	blt 2b
	520
	521	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	522	bl trap_reloc
	523
	524	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	525	bl trap_reloc
	526
	527	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	528	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
	529	3:
	530	bl trap_reloc
	531	addi r7, r7, 0x100 /* next exception vector */
	532	cmplw 0, r7, r8
	533	blt 3b
	534
	535	li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	536	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
	537	4:
	538	bl trap_reloc
	539	addi r7, r7, 0x100 /* next exception vector */
	540	cmplw 0, r7, r8
	541	blt 4b
	542
	543	mtlr r4 /* restore link register */
	544	blr
	545
b6e4c403 WD	546	#if defined(CONFIG_PATI)
	547	/* Program the PLL */
	548	pll_prog_code_start:
6d0f6bcf JCPV	549	lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
6d0f6bcf JCPV	550	ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
b6e4c403 WD	551	lis r3, (0x55ccaa33)@h
	552	ori r3, r3, (0x55ccaa33)@l
	553	stw r3, 0(r4)
6d0f6bcf JCPV	554	lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
	555	ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
	556	lis r3, CONFIG_SYS_PLPRCR@h
	557	ori r3, r3, CONFIG_SYS_PLPRCR@l
b6e4c403 WD	558	stw r3, 0(r4)
	559	addis r3,0,0x0
	560	ori r3,r3,0xA000
	561	mtctr r3
	562	..spinlp:
	563	bdnz ..spinlp /* spin loop */
	564	blr
	565	pll_prog_code_end:
	566	nop
	567	blr
	568	#endif