[J-u-boot.git] / drivers / watchdog / imx_watchdog.c

/*
 * watchdog.c - driver for i.mx on-chip watchdog
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <asm/io.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>

struct watchdog_regs {
	u16	wcr;	/* Control */
	u16	wsr;	/* Service */
	u16	wrsr;	/* Reset Status */
};

#define WCR_WDZST	0x01
#define WCR_WDBG	0x02
#define WCR_WDE		0x04	/* WDOG enable */
#define WCR_WDT		0x08
#define WCR_SRS		0x10
#define SET_WCR_WT(x)	(x << 8)

#ifdef CONFIG_IMX_WATCHDOG
void hw_watchdog_reset(void)
{
	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;

	writew(0x5555, &wdog->wsr);
	writew(0xaaaa, &wdog->wsr);
}

void hw_watchdog_init(void)
{
	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
	u16 timeout;

	/*
	 * The timer watchdog can be set between
	 * 0.5 and 128 Seconds. If not defined
	 * in configuration file, sets 128 Seconds
	 */
#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
#endif
	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
		SET_WCR_WT(timeout), &wdog->wcr);
	hw_watchdog_reset();
}
#endif

void reset_cpu(ulong addr)
{
	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;

	writew(WCR_WDE, &wdog->wcr);
	writew(0x5555, &wdog->wsr);
	writew(0xaaaa, &wdog->wsr);	/* load minimum 1/2 second timeout */
	while (1) {
		/*
		 * spin for .5 seconds before reset
		 */
	}
}
Commit	Line	Data
abbab703 TK	1	/*
	2	* watchdog.c - driver for i.mx on-chip watchdog
	3	*
	4	* Licensed under the GPL-2 or later.
	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <watchdog.h>
	10	#include <asm/arch/imx-regs.h>
	11
	12	struct watchdog_regs {
	13	u16 wcr; /* Control */
	14	u16 wsr; /* Service */
	15	u16 wrsr; /* Reset Status */
	16	};
	17
	18	#define WCR_WDZST 0x01
	19	#define WCR_WDBG 0x02
	20	#define WCR_WDE 0x04 /* WDOG enable */
	21	#define WCR_WDT 0x08
723ec69a	22	#define WCR_SRS 0x10
abbab703 TK	23	#define SET_WCR_WT(x) (x << 8)
	24
	25	#ifdef CONFIG_IMX_WATCHDOG
	26	void hw_watchdog_reset(void)
	27	{
	28	struct watchdog_regs wdog = (struct watchdog_regs )WDOG1_BASE_ADDR;
	29
	30	writew(0x5555, &wdog->wsr);
	31	writew(0xaaaa, &wdog->wsr);
	32	}
	33
	34	void hw_watchdog_init(void)
	35	{
	36	struct watchdog_regs wdog = (struct watchdog_regs )WDOG1_BASE_ADDR;
	37	u16 timeout;
	38
	39	/*
	40	* The timer watchdog can be set between
	41	* 0.5 and 128 Seconds. If not defined
	42	* in configuration file, sets 128 Seconds
	43	*/
	44	#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
	45	#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
	46	#endif
	47	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
723ec69a	48	writew(WCR_WDZST \| WCR_WDBG \| WCR_WDE \| WCR_WDT \| WCR_SRS \|
5cab8740	49	SET_WCR_WT(timeout), &wdog->wcr);
abbab703 TK	50	hw_watchdog_reset();
	51	}
	52	#endif
	53
	54	void reset_cpu(ulong addr)
	55	{
	56	struct watchdog_regs wdog = (struct watchdog_regs )WDOG1_BASE_ADDR;
	57
	58	writew(WCR_WDE, &wdog->wcr);
	59	writew(0x5555, &wdog->wsr);
	60	writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
	61	while (1) {
	62	/*
	63	* spin for .5 seconds before reset
	64	*/
	65	}
	66	}