[J-u-boot.git] / arch / ppc / cpu / mpc8260 / ether_scc.c

/*
 * MPC8260 SCC Ethernet
 *
 * Copyright (c) 2000 MontaVista Software, Inc.   Dan Malek ([email protected])
 *
 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[email protected]>
 *
 * (C) Copyright (c) 2001
 * Advent Networks, Inc. <http://www.adventnetworks.com>
 * Jay Monkman <[email protected]>
 *
 * Modified so that it plays nicely when more than one ETHERNET interface
 * is in use a la ether_fcc.c.
 * (C) Copyright 2008
 * DENX Software Engineerin GmbH
 * Gary Jennejohn <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/cpm_8260.h>
#include <mpc8260.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <config.h>

#ifndef CONFIG_NET_MULTI
#error "CONFIG_NET_MULTI must be defined."
#endif

#if (CONFIG_ETHER_INDEX == 1)
#  define PROFF_ENET            PROFF_SCC1
#  define CPM_CR_ENET_PAGE      CPM_CR_SCC1_PAGE
#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC1_SBLOCK
#  define CMXSCR_MASK          (CMXSCR_SC1          |\
				CMXSCR_RS1CS_MSK    |\
				CMXSCR_TS1CS_MSK)

#elif (CONFIG_ETHER_INDEX == 2)
#  define PROFF_ENET            PROFF_SCC2
#  define CPM_CR_ENET_PAGE      CPM_CR_SCC2_PAGE
#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC2_SBLOCK
#  define CMXSCR_MASK          (CMXSCR_SC2          |\
				CMXSCR_RS2CS_MSK    |\
				CMXSCR_TS2CS_MSK)

#elif (CONFIG_ETHER_INDEX == 3)
#  define PROFF_ENET            PROFF_SCC3
#  define CPM_CR_ENET_PAGE      CPM_CR_SCC3_PAGE
#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC3_SBLOCK
#  define CMXSCR_MASK          (CMXSCR_SC3          |\
				CMXSCR_RS3CS_MSK    |\
				CMXSCR_TS3CS_MSK)
#elif (CONFIG_ETHER_INDEX == 4)
#  define PROFF_ENET            PROFF_SCC4
#  define CPM_CR_ENET_PAGE      CPM_CR_SCC4_PAGE
#  define CPM_CR_ENET_SBLOCK    CPM_CR_SCC4_SBLOCK
#  define CMXSCR_MASK          (CMXSCR_SC4          |\
				CMXSCR_RS4CS_MSK    |\
				CMXSCR_TS4CS_MSK)

#endif


/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH  1520

#define TX_BUF_CNT 2

#if !defined(CONFIG_SYS_SCC_TOUT_LOOP)
  #define CONFIG_SYS_SCC_TOUT_LOOP 1000000
#endif

static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];

static uint rxIdx;      /* index of the current RX buffer */
static uint txIdx;      /* index of the current TX buffer */

/*
 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
 *  immr->udata_bd address on Dual-Port RAM
 * Provide for Double Buffering
 */

typedef volatile struct CommonBufferDescriptor {
    cbd_t rxbd[PKTBUFSRX];         /* Rx BD */
    cbd_t txbd[TX_BUF_CNT];        /* Tx BD */
} RTXBD;

static RTXBD *rtx;


static int sec_send(struct eth_device *dev, volatile void *packet, int length)
{
    int i;
    int result = 0;

    if (length <= 0) {
	printf("scc: bad packet size: %d\n", length);
	goto out;
    }

    for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
	if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
	    puts ("scc: tx buffer not ready\n");
	    goto out;
	}
    }

    rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
    rtx->txbd[txIdx].cbd_datlen = length;
    rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
				BD_ENET_TX_WRAP);

    for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
	if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
	    puts ("scc: tx error\n");
	    goto out;
	}
    }

    /* return only status bits */
    result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;

 out:
    return result;
}


static int sec_rx(struct eth_device *dev)
{
    int length;

    for (;;)
    {
	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
	    length = -1;
	    break;     /* nothing received - leave for() loop */
	}

	length = rtx->rxbd[rxIdx].cbd_datlen;

	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
	{
	    printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
	}
	else
	{
	    /* Pass the packet up to the protocol layers. */
	    NetReceive(NetRxPackets[rxIdx], length - 4);
	}


	/* Give the buffer back to the SCC. */
	rtx->rxbd[rxIdx].cbd_datlen = 0;

	/* wrap around buffer index when necessary */
	if ((rxIdx + 1) >= PKTBUFSRX) {
	    rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
					       BD_ENET_RX_EMPTY);
	    rxIdx = 0;
	}
	else {
	    rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
	    rxIdx++;
	}
    }
    return length;
}

/**************************************************************
 *
 * SCC Ethernet Initialization Routine
 *
 *************************************************************/

static int sec_init(struct eth_device *dev, bd_t *bis)
{
    int i;
    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
    scc_enet_t *pram_ptr;
    uint dpaddr;
    uchar ea[6];

    rxIdx = 0;
    txIdx = 0;

    /*
     * Assign static pointer to BD area.
     * Avoid exhausting DPRAM, which would cause a panic.
     */
    if (rtx == NULL) {
	    dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
	    rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
    }

    /* 24.21 - (1-3): ioports have been set up already */

    /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
    immr->im_cpmux.cmx_uar = 0;
    immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
			       CONFIG_SYS_CMXSCR_VALUE);


    /* 24.21 (6) write RBASE and TBASE to parameter RAM */
    pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
    pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
    pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);

    pram_ptr->sen_genscc.scc_rfcr = 0x18;  /* Nrml Ops and Mot byte ordering */
    pram_ptr->sen_genscc.scc_tfcr = 0x18;  /* Mot byte ordering, Nrml access */

    pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */

    pram_ptr->sen_cpres  = ~(0x0);        /* Preset CRC */
    pram_ptr->sen_cmask  = 0xdebb20e3;    /* Constant Mask for CRC */


    /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
    while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
    immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
				     CPM_CR_ENET_SBLOCK,
				     0x0c,
				     CPM_CR_INIT_TRX) | CPM_CR_FLG;

    /* 24.21 - (8-18): Set up parameter RAM */
    pram_ptr->sen_crcec  = 0x0;           /* Error Counter CRC (unused) */
    pram_ptr->sen_alec   = 0x0;           /* Align Error Counter (unused) */
    pram_ptr->sen_disfc  = 0x0;           /* Discard Frame Counter (unused) */

    pram_ptr->sen_pads   = 0x8888;        /* Short Frame PAD Characters */

    pram_ptr->sen_retlim = 15;            /* Retry Limit Threshold */

    pram_ptr->sen_maxflr = 1518;  /* MAX Frame Length Register */
    pram_ptr->sen_minflr = 64;            /* MIN Frame Length Register */

    pram_ptr->sen_maxd1  = DBUF_LENGTH;   /* MAX DMA1 Length Register */
    pram_ptr->sen_maxd2  = DBUF_LENGTH;   /* MAX DMA2 Length Register */

    pram_ptr->sen_gaddr1 = 0x0;   /* Group Address Filter 1 (unused) */
    pram_ptr->sen_gaddr2 = 0x0;   /* Group Address Filter 2 (unused) */
    pram_ptr->sen_gaddr3 = 0x0;   /* Group Address Filter 3 (unused) */
    pram_ptr->sen_gaddr4 = 0x0;   /* Group Address Filter 4 (unused) */

    eth_getenv_enetaddr("ethaddr", ea);
    pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
    pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
    pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];

    pram_ptr->sen_pper   = 0x0;   /* Persistence (unused) */

    pram_ptr->sen_iaddr1 = 0x0;   /* Individual Address Filter 1 (unused) */
    pram_ptr->sen_iaddr2 = 0x0;   /* Individual Address Filter 2 (unused) */
    pram_ptr->sen_iaddr3 = 0x0;   /* Individual Address Filter 3 (unused) */
    pram_ptr->sen_iaddr4 = 0x0;   /* Individual Address Filter 4 (unused) */

    pram_ptr->sen_taddrh = 0x0;   /* Tmp Address (MSB) (unused) */
    pram_ptr->sen_taddrm = 0x0;   /* Tmp Address (unused) */
    pram_ptr->sen_taddrl = 0x0;   /* Tmp Address (LSB) (unused) */

    /* 24.21 - (19): Initialize RxBD */
    for (i = 0; i < PKTBUFSRX; i++)
    {
	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	rtx->rxbd[i].cbd_datlen = 0;                  /* Reset */
	rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
    }

    rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

    /* 24.21 - (20): Initialize TxBD */
    for (i = 0; i < TX_BUF_CNT; i++)
    {
	rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD  |
			       BD_ENET_TX_LAST |
			       BD_ENET_TX_TC);
	rtx->txbd[i].cbd_datlen = 0;                  /* Reset */
	rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
    }

    rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;

    /* 24.21 - (21): Write 0xffff to SCCE */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);

    /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
						   SCCE_ENET_RXF |
						   SCCE_ENET_TXB);

    /* 24.21 - (23): we don't use ethernet interrupts */

    /* 24.21 - (24): Clear GSMR_H to enable normal operations */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;

    /* 24.21 - (25): Clear GSMR_L to enable normal operations */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI        |
						    SCC_GSMRL_TPL_48     |
						    SCC_GSMRL_TPP_10     |
						    SCC_GSMRL_MODE_ENET);

    /* 24.21 - (26): Initialize DSR */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;

    /* 24.21 - (27): Initialize PSMR2
     *
     * Settings:
     *	CRC = 32-Bit CCITT
     *	NIB = Begin searching for SFD 22 bits after RENA
     *	FDE = Full Duplex Enable
     *	BRO = Reject broadcast packets
     *	PROMISCOUS = Catch all packets regardless of dest. MAC adress
     */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr   =	SCC_PSMR_ENCRC	|
							SCC_PSMR_NIB22	|
#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
							SCC_PSMR_FDE	|
#endif
#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
							SCC_PSMR_BRO	|
#endif
#if defined(CONFIG_SCC_ENET_PROMISCOUS)
							SCC_PSMR_PRO	|
#endif
							0;

    /* 24.21 - (28): Write to GSMR_L to enable SCC */
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
						     SCC_GSMRL_ENT);

    return 0;
}


static void sec_halt(struct eth_device *dev)
{
    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
    immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
						      SCC_GSMRL_ENT);
}

#if 0
static void sec_restart(void)
{
    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
    immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
							    SCC_GSMRL_ENT);
}
#endif

int mpc82xx_scc_enet_initialize(bd_t *bis)
{
	struct eth_device *dev;

	dev = (struct eth_device *) malloc(sizeof *dev);
	memset(dev, 0, sizeof *dev);

	sprintf(dev->name, "SCC ETHERNET");
	dev->init   = sec_init;
	dev->halt   = sec_halt;
	dev->send   = sec_send;
	dev->recv   = sec_rx;

	eth_register(dev);

	return 1;
}
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* MPC8260 SCC Ethernet
	3	*
	4	* Copyright (c) 2000 MontaVista Software, Inc. Dan Malek ([email protected])
	5	*
	6	* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <[email protected]>
	8	*
	9	* (C) Copyright (c) 2001
	10	* Advent Networks, Inc. <http://www.adventnetworks.com>
	11	* Jay Monkman <[email protected]>
	12	*
ba705b5b GJ	13	* Modified so that it plays nicely when more than one ETHERNET interface
	14	* is in use a la ether_fcc.c.
	15	* (C) Copyright 2008
	16	* DENX Software Engineerin GmbH
	17	* Gary Jennejohn <[email protected]>
	18	*
fe8c2806 WD	19	* See file CREDITS for list of people who contributed to this
	20	* project.
	21	*
	22	* This program is free software; you can redistribute it and/or
	23	* modify it under the terms of the GNU General Public License as
	24	* published by the Free Software Foundation; either version 2 of
	25	* the License, or (at your option) any later version.
	26	*
	27	* This program is distributed in the hope that it will be useful,
	28	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	29	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	30	* GNU General Public License for more details.
	31	*
	32	* You should have received a copy of the GNU General Public License
	33	* along with this program; if not, write to the Free Software
	34	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	35	* MA 02111-1307 USA
	36	*/
	37
	38	#include <common.h>
	39	#include <asm/cpm_8260.h>
	40	#include <mpc8260.h>
ba705b5b	41	#include <malloc.h>
fe8c2806 WD	42	#include <net.h>
	43	#include <command.h>
	44	#include <config.h>
	45
ba705b5b GJ	46	#ifndef CONFIG_NET_MULTI
	47	#error "CONFIG_NET_MULTI must be defined."
	48	#endif
fe8c2806 WD	49
	50	#if (CONFIG_ETHER_INDEX == 1)
	51	# define PROFF_ENET PROFF_SCC1
	52	# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE
	53	# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK
	54	# define CMXSCR_MASK (CMXSCR_SC1 \|\
8bde7f77 WD	55	CMXSCR_RS1CS_MSK \|\
8bde7f77 WD	56	CMXSCR_TS1CS_MSK)
fe8c2806 WD	57
	58	#elif (CONFIG_ETHER_INDEX == 2)
	59	# define PROFF_ENET PROFF_SCC2
	60	# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE
	61	# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK
	62	# define CMXSCR_MASK (CMXSCR_SC2 \|\
8bde7f77 WD	63	CMXSCR_RS2CS_MSK \|\
8bde7f77 WD	64	CMXSCR_TS2CS_MSK)
fe8c2806 WD	65
	66	#elif (CONFIG_ETHER_INDEX == 3)
	67	# define PROFF_ENET PROFF_SCC3
	68	# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE
	69	# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK
	70	# define CMXSCR_MASK (CMXSCR_SC3 \|\
8bde7f77 WD	71	CMXSCR_RS3CS_MSK \|\
8bde7f77 WD	72	CMXSCR_TS3CS_MSK)
fe8c2806 WD	73	#elif (CONFIG_ETHER_INDEX == 4)
	74	# define PROFF_ENET PROFF_SCC4
	75	# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE
	76	# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK
	77	# define CMXSCR_MASK (CMXSCR_SC4 \|\
8bde7f77 WD	78	CMXSCR_RS4CS_MSK \|\
8bde7f77 WD	79	CMXSCR_TS4CS_MSK)
fe8c2806 WD	80
	81	#endif
	82
	83
	84	/* Ethernet Transmit and Receive Buffers */
	85	#define DBUF_LENGTH 1520
	86
	87	#define TX_BUF_CNT 2
	88
6d0f6bcf JCPV	89	#if !defined(CONFIG_SYS_SCC_TOUT_LOOP)
6d0f6bcf JCPV	90	#define CONFIG_SYS_SCC_TOUT_LOOP 1000000
ac9db066	91	#endif
fe8c2806 WD	92
	93	static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];
	94
	95	static uint rxIdx; /* index of the current RX buffer */
	96	static uint txIdx; /* index of the current TX buffer */
	97
	98	/*
	99	* SCC Ethernet Tx and Rx buffer descriptors allocated at the
	100	* immr->udata_bd address on Dual-Port RAM
	101	* Provide for Double Buffering
	102	*/
	103
	104	typedef volatile struct CommonBufferDescriptor {
	105	cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
	106	cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
	107	} RTXBD;
	108
	109	static RTXBD *rtx;
	110
	111
ba705b5b	112	static int sec_send(struct eth_device dev, volatile void packet, int length)
fe8c2806 WD	113	{
	114	int i;
	115	int result = 0;
	116
	117	if (length <= 0) {
8bde7f77 WD	118	printf("scc: bad packet size: %d\n", length);
8bde7f77 WD	119	goto out;
fe8c2806 WD	120	}
	121
	122	for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
6d0f6bcf	123	if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
4b9206ed	124	puts ("scc: tx buffer not ready\n");
8bde7f77 WD	125	goto out;
8bde7f77 WD	126	}
fe8c2806 WD	127	}
	128
	129	rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
	130	rtx->txbd[txIdx].cbd_datlen = length;
	131	rtx->txbd[txIdx].cbd_sc \|= (BD_ENET_TX_READY \| BD_ENET_TX_LAST \|
8bde7f77	132	BD_ENET_TX_WRAP);
fe8c2806 WD	133
fe8c2806 WD	134	for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
6d0f6bcf	135	if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
4b9206ed	136	puts ("scc: tx error\n");
8bde7f77 WD	137	goto out;
8bde7f77 WD	138	}
fe8c2806 WD	139	}
	140
	141	/* return only status bits */
	142	result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
	143
	144	out:
	145	return result;
	146	}
	147
	148
ba705b5b	149	static int sec_rx(struct eth_device *dev)
fe8c2806 WD	150	{
	151	int length;
	152
	153	for (;;)
	154	{
8bde7f77 WD	155	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
	156	length = -1;
	157	break; /* nothing received - leave for() loop */
	158	}
	159
	160	length = rtx->rxbd[rxIdx].cbd_datlen;
	161
	162	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
	163	{
	164	printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
	165	}
	166	else
	167	{
	168	/* Pass the packet up to the protocol layers. */
	169	NetReceive(NetRxPackets[rxIdx], length - 4);
	170	}
	171
	172
	173	/* Give the buffer back to the SCC. */
	174	rtx->rxbd[rxIdx].cbd_datlen = 0;
	175
	176	/* wrap around buffer index when necessary */
	177	if ((rxIdx + 1) >= PKTBUFSRX) {
	178	rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP \|
	179	BD_ENET_RX_EMPTY);
	180	rxIdx = 0;
	181	}
	182	else {
	183	rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
	184	rxIdx++;
	185	}
fe8c2806 WD	186	}
	187	return length;
	188	}
	189
	190	/**************************************************************
	191	*
	192	* SCC Ethernet Initialization Routine
	193	*
	194	*************************************************************/
	195
ba705b5b	196	static int sec_init(struct eth_device dev, bd_t bis)
fe8c2806 WD	197	{
fe8c2806 WD	198	int i;
6d0f6bcf	199	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
fe8c2806 WD	200	scc_enet_t *pram_ptr;
fe8c2806 WD	201	uint dpaddr;
6bacfa6a	202	uchar ea[6];
fe8c2806 WD	203
	204	rxIdx = 0;
	205	txIdx = 0;
	206
ba705b5b GJ	207	/*
	208	* Assign static pointer to BD area.
	209	* Avoid exhausting DPRAM, which would cause a panic.
	210	*/
	211	if (rtx == NULL) {
	212	dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
	213	rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
	214	}
fe8c2806 WD	215
	216	/* 24.21 - (1-3): ioports have been set up already */
	217
	218	/* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
	219	immr->im_cpmux.cmx_uar = 0;
	220	immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) \|
6d0f6bcf	221	CONFIG_SYS_CMXSCR_VALUE);
fe8c2806 WD	222
	223
	224	/* 24.21 (6) write RBASE and TBASE to parameter RAM */
	225	pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
	226	pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
	227	pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);
	228
	229	pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */
	230	pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */
	231
	232	pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */
	233
	234	pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
	235	pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
	236
	237
	238	/* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
	239	while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
	240	immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
8bde7f77 WD	241	CPM_CR_ENET_SBLOCK,
	242	0x0c,
	243	CPM_CR_INIT_TRX) \| CPM_CR_FLG;
fe8c2806 WD	244
	245	/* 24.21 - (8-18): Set up parameter RAM */
	246	pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
	247	pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */
	248	pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
	249
	250	pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
	251
	252	pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
	253
	254	pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
	255	pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
	256
	257	pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
	258	pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
	259
	260	pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
	261	pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
	262	pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
	263	pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
	264
6bacfa6a	265	eth_getenv_enetaddr("ethaddr", ea);
fe8c2806 WD	266	pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
	267	pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
	268	pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
fe8c2806 WD	269
	270	pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
	271
	272	pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
	273	pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
	274	pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
	275	pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
	276
	277	pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
	278	pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
	279	pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
	280
fe8c2806 WD	281	/* 24.21 - (19): Initialize RxBD */
	282	for (i = 0; i < PKTBUFSRX; i++)
	283	{
8bde7f77 WD	284	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	285	rtx->rxbd[i].cbd_datlen = 0; /* Reset */
	286	rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
fe8c2806 WD	287	}
	288
	289	rtx->rxbd[PKTBUFSRX - 1].cbd_sc \|= BD_ENET_RX_WRAP;
	290
	291	/* 24.21 - (20): Initialize TxBD */
	292	for (i = 0; i < TX_BUF_CNT; i++)
	293	{
8bde7f77 WD	294	rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD \|
	295	BD_ENET_TX_LAST \|
	296	BD_ENET_TX_TC);
	297	rtx->txbd[i].cbd_datlen = 0; /* Reset */
	298	rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
fe8c2806 WD	299	}
	300
	301	rtx->txbd[TX_BUF_CNT - 1].cbd_sc \|= BD_ENET_TX_WRAP;
	302
	303	/* 24.21 - (21): Write 0xffff to SCCE */
	304	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);
	305
	306	/* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
	307	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE \|
8bde7f77 WD	308	SCCE_ENET_RXF \|
8bde7f77 WD	309	SCCE_ENET_TXB);
fe8c2806 WD	310
	311	/* 24.21 - (23): we don't use ethernet interrupts */
	312
	313	/* 24.21 - (24): Clear GSMR_H to enable normal operations */
	314	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;
	315
	316	/* 24.21 - (25): Clear GSMR_L to enable normal operations */
	317	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI \|
8bde7f77 WD	318	SCC_GSMRL_TPL_48 \|
	319	SCC_GSMRL_TPP_10 \|
	320	SCC_GSMRL_MODE_ENET);
fe8c2806 WD	321
	322	/* 24.21 - (26): Initialize DSR */
	323	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
	324
	325	/* 24.21 - (27): Initialize PSMR2
	326	*
	327	* Settings:
	328	* CRC = 32-Bit CCITT
	329	* NIB = Begin searching for SFD 22 bits after RENA
	330	* FDE = Full Duplex Enable
	331	* BRO = Reject broadcast packets
	332	* PROMISCOUS = Catch all packets regardless of dest. MAC adress
	333	*/
	334	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC \|
	335	SCC_PSMR_NIB22 \|
	336	#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
	337	SCC_PSMR_FDE \|
	338	#endif
	339	#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
	340	SCC_PSMR_BRO \|
	341	#endif
	342	#if defined(CONFIG_SCC_ENET_PROMISCOUS)
	343	SCC_PSMR_PRO \|
	344	#endif
	345	0;
	346
	347	/* 24.21 - (28): Write to GSMR_L to enable SCC */
	348	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl \|= (SCC_GSMRL_ENR \|
8bde7f77	349	SCC_GSMRL_ENT);
fe8c2806	350
48b42616	351	return 0;
fe8c2806 WD	352	}
	353
	354
ba705b5b	355	static void sec_halt(struct eth_device *dev)
fe8c2806	356	{
6d0f6bcf	357	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
fe8c2806	358	immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR \|
8bde7f77	359	SCC_GSMRL_ENT);
fe8c2806 WD	360	}
	361
	362	#if 0
ba705b5b	363	static void sec_restart(void)
fe8c2806	364	{
6d0f6bcf	365	volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
fe8c2806	366	immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl \|= (SCC_GSMRL_ENR \|
8bde7f77	367	SCC_GSMRL_ENT);
fe8c2806 WD	368	}
	369	#endif
	370
ba705b5b GJ	371	int mpc82xx_scc_enet_initialize(bd_t *bis)
	372	{
	373	struct eth_device *dev;
	374
	375	dev = (struct eth_device ) malloc(sizeof dev);
	376	memset(dev, 0, sizeof *dev);
	377
	378	sprintf(dev->name, "SCC ETHERNET");
	379	dev->init = sec_init;
	380	dev->halt = sec_halt;
	381	dev->send = sec_send;
	382	dev->recv = sec_rx;
	383
	384	eth_register(dev);
	385
	386	return 1;
	387	}