[J-u-boot.git] / include / vsc9953.h

/*
 *  vsc9953.h
 *
 *  Driver for the Vitesse VSC9953 L2 Switch
 *
 *  This software may be used and distributed according to the
 *  terms of the GNU Public License, Version 2, incorporated
 *  herein by reference.
 *
 * Copyright 2013  Freescale Semiconductor, Inc.
 *
 */

#ifndef _VSC9953_H_
#define _VSC9953_H_

#include <config.h>
#include <miiphy.h>
#include <asm/types.h>

#define VSC9953_OFFSET			(CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)

#define VSC9953_SYS_OFFSET		0x010000
#define VSC9953_REW_OFFSET		0x030000
#define VSC9953_DEV_GMII_OFFSET		0x100000
#define VSC9953_QSYS_OFFSET		0x200000
#define VSC9953_ANA_OFFSET		0x280000
#define VSC9953_DEVCPU_GCB		0x070000
#define VSC9953_ES0			0x040000
#define VSC9953_IS1			0x050000
#define VSC9953_IS2			0x060000

#define T1040_SWITCH_GMII_DEV_OFFSET	0x010000
#define VSC9953_PHY_REGS_OFFST		0x0000AC

/* Macros for vsc9953_chip_regs.soft_rst register */
#define VSC9953_SOFT_SWC_RST_ENA	0x00000001

/* Macros for vsc9953_sys_sys.reset_cfg register */
#define VSC9953_CORE_ENABLE		0x80
#define VSC9953_MEM_ENABLE		0x40
#define VSC9953_MEM_INIT		0x20

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
#define VSC9953_MAC_ENA_CFG		0x00000011

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
#define VSC9953_MAC_MODE_CFG		0x00000011

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
#define VSC9953_MAC_IFG_CFG		0x00000515

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
#define VSC9953_MAC_HDX_CFG		0x00001043

/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
#define VSC9953_MAC_MAX_LEN		0x000005ee

/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
#define VSC9953_CLOCK_CFG		0x00000001
#define VSC9953_CLOCK_CFG_1000M		0x00000001

/* Macros for vsc9953_sys_sys.front_port_mode register */
#define VSC9953_FRONT_PORT_MODE	0x00000000

/* Macros for vsc9953_ana_pfc.pfc_cfg register */
#define VSC9953_PFC_FC			0x00000001
#define VSC9953_PFC_FC_QSGMII		0x00000000

/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
#define VSC9953_MAC_FC_CFG		0x04700000
#define VSC9953_MAC_FC_CFG_QSGMII	0x00700000

/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
#define VSC9953_PAUSE_CFG		0x001ffffe

/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
#define VSC9953_TOT_TAIL_DROP_LVL	0x000003ff

/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
#define VSC9953_VCAP_MV_CFG		0x0000ffff
#define VSC9953_VCAP_UPDATE_CTRL	0x01000004

/* Macros for vsc9953_ana_port.vlan_cfg register */
#define VSC9953_VLAN_CFG_AWARE_ENA	0x00100000
#define VSC9953_VLAN_CFG_POP_CNT_MASK	0x000c0000
#define VSC9953_VLAN_CFG_VID_MASK	0x00000fff

/* Macros for vsc9953_rew_port.port_vlan_cfg register */
#define VSC9953_PORT_VLAN_CFG_VID_MASK	0x00000fff

/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
#define VSC9953_ANA_TBL_VID_MASK	0x00000fff

/* Macros for vsc9953_ana_ana_tables.vlan_access register */
#define VSC9953_VLAN_PORT_MASK		0x00001ffc
#define VSC9953_VLAN_CMD_MASK		0x00000003
#define VSC9953_VLAN_CMD_IDLE		0x00000000
#define VSC9953_VLAN_CMD_READ		0x00000001
#define VSC9953_VLAN_CMD_WRITE		0x00000002
#define VSC9953_VLAN_CMD_INIT		0x00000003

/* Macros for vsc9953_qsys_sys.switch_port_mode register */
#define VSC9953_PORT_ENA		0x00002000

/* Macros for vsc9953_ana_ana.adv_learn register */
#define VSC9953_VLAN_CHK		0x00000400

/* Macros for vsc9953_rew_port.port_tag_cfg register */
#define VSC9953_TAG_CFG_MASK		0x00000180
#define VSC9953_TAG_CFG_NONE		0x00000000
#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO	0x00000080
#define VSC9953_TAG_CFG_ALL_BUT_ZERO		0x00000100
#define VSC9953_TAG_CFG_ALL		0x00000180

#define VSC9953_MAX_PORTS		10
#define VSC9953_PORT_CHECK(port)	\
	(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
	( \
		(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
	) ? 0 : 1 \
)
#define VSC9953_MAX_VLAN		4096
#define VSC9953_VLAN_CHECK(vid)	\
	(((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)

#define DEFAULT_VSC9953_MDIO_NAME	"VSC9953_MDIO0"

#define MIIMIND_OPR_PEND		0x00000004

struct vsc9953_mdio_info {
	struct vsc9953_mii_mng	*regs;
	char	*name;
};

/* VSC9953 ANA structure */

struct vsc9953_ana_port {
	u32	vlan_cfg;
	u32	drop_cfg;
	u32	qos_cfg;
	u32	vcap_cfg;
	u32	vcap_s1_key_cfg[3];
	u32	vcap_s2_cfg;
	u32	qos_pcp_dei_map_cfg[16];
	u32	cpu_fwd_cfg;
	u32	cpu_fwd_bpdu_cfg;
	u32	cpu_fwd_garp_cfg;
	u32	cpu_fwd_ccm_cfg;
	u32	port_cfg;
	u32	pol_cfg;
	u32	reserved[34];
};

struct vsc9953_ana_pol {
	u32	pol_pir_cfg;
	u32	pol_cir_cfg;
	u32	pol_mode_cfg;
	u32	pol_pir_state;
	u32	pol_cir_state;
	u32	reserved1[3];
};

struct vsc9953_ana_ana_tables {
	u32	entry_lim[11];
	u32	an_moved;
	u32	mach_data;
	u32	macl_data;
	u32	mac_access;
	u32	mact_indx;
	u32	vlan_access;
	u32	vlan_tidx;
};

struct vsc9953_ana_ana {
	u32	adv_learn;
	u32	vlan_mask;
	u32	reserved;
	u32	anag_efil;
	u32	an_events;
	u32	storm_limit_burst;
	u32	storm_limit_cfg[4];
	u32	isolated_prts;
	u32	community_ports;
	u32	auto_age;
	u32	mac_options;
	u32	learn_disc;
	u32	agen_ctrl;
	u32	mirror_ports;
	u32	emirror_ports;
	u32	flooding;
	u32	flooding_ipmc;
	u32	sflow_cfg[11];
	u32	port_mode[12];
};

struct vsc9953_ana_pgid {
	u32	port_grp_id[91];
};

struct vsc9953_ana_pfc {
	u32	pfc_cfg;
	u32	reserved1[15];
};

struct vsc9953_ana_pol_misc {
	u32	pol_flowc[10];
	u32	reserved1[17];
	u32	pol_hyst;
};

struct vsc9953_ana_common {
	u32	aggr_cfg;
	u32	cpuq_cfg;
	u32	cpuq_8021_cfg;
	u32	dscp_cfg;
	u32	dscp_rewr_cfg;
	u32	vcap_rng_type_cfg;
	u32	vcap_rng_val_cfg;
	u32	discard_cfg;
	u32	fid_cfg;
};

struct vsc9953_analyzer {
	struct vsc9953_ana_port	port[11];
	u32	reserved1[9536];
	struct vsc9953_ana_pol	pol[164];
	struct vsc9953_ana_ana_tables	ana_tables;
	u32	reserved2[14];
	struct vsc9953_ana_ana	ana;
	u32	reserved3[22];
	struct vsc9953_ana_pgid	port_id_tbl;
	u32	reserved4[549];
	struct vsc9953_ana_pfc	pfc[10];
	struct vsc9953_ana_pol_misc	pol_misc;
	u32	reserved5[196];
	struct vsc9953_ana_common	common;
};
/* END VSC9953 ANA structure t*/

/* VSC9953 DEV_GMII structure */

struct vsc9953_dev_gmii_port_mode {
	u32	clock_cfg;
	u32	port_misc;
	u32	reserved1;
	u32	eee_cfg;
};

struct vsc9953_dev_gmii_mac_cfg_status {
	u32	mac_ena_cfg;
	u32	mac_mode_cfg;
	u32	mac_maxlen_cfg;
	u32	mac_tags_cfg;
	u32	mac_adv_chk_cfg;
	u32	mac_ifg_cfg;
	u32	mac_hdx_cfg;
	u32	mac_fc_mac_low_cfg;
	u32	mac_fc_mac_high_cfg;
	u32	mac_sticky;
};

struct vsc9953_dev_gmii {
	struct vsc9953_dev_gmii_port_mode	port_mode;
	struct vsc9953_dev_gmii_mac_cfg_status	mac_cfg_status;
};

/* END VSC9953 DEV_GMII structure */

/* VSC9953 QSYS structure */

struct vsc9953_qsys_hsch {
	u32	cir_cfg;
	u32	reserved1;
	u32	se_cfg;
	u32	se_dwrr_cfg[8];
	u32	cir_state;
	u32	reserved2[20];
};

struct vsc9953_qsys_sys {
	u32	port_mode[12];
	u32	switch_port_mode[11];
	u32	stat_cnt_cfg;
	u32	eee_cfg[10];
	u32	eee_thrs;
	u32	igr_no_sharing;
	u32	egr_no_sharing;
	u32	sw_status[11];
	u32	ext_cpu_cfg;
	u32	cpu_group_map;
	u32	reserved1[23];
};

struct vsc9953_qsys_qos_cfg {
	u32	red_profile[16];
	u32	res_qos_mode;
};

struct vsc9953_qsys_drop_cfg {
	u32	egr_drop_mode;
};

struct vsc9953_qsys_mmgt {
	u32	eq_cntrl;
	u32	reserved1;
};

struct vsc9953_qsys_hsch_misc {
	u32	hsch_misc_cfg;
	u32	reserved1[546];
};

struct vsc9953_qsys_res_ctrl {
	u32	res_cfg;
	u32	res_stat;

};

struct vsc9953_qsys_reg {
	struct vsc9953_qsys_hsch	hsch[108];
	struct vsc9953_qsys_sys	sys;
	struct vsc9953_qsys_qos_cfg	qos_cfg;
	struct vsc9953_qsys_drop_cfg	drop_cfg;
	struct vsc9953_qsys_mmgt	mmgt;
	struct vsc9953_qsys_hsch_misc	hsch_misc;
	struct vsc9953_qsys_res_ctrl	res_ctrl[1024];
};

/* END VSC9953 QSYS structure */

/* VSC9953 SYS structure */

struct vsc9953_sys_stat {
	u32	rx_cntrs[64];
	u32	tx_cntrs[64];
	u32	drop_cntrs[64];
	u32	reserved1[6];
};

struct vsc9953_sys_sys {
	u32	reset_cfg;
	u32	reserved1;
	u32	vlan_etype_cfg;
	u32	port_mode[12];
	u32	front_port_mode[10];
	u32	frame_aging;
	u32	stat_cfg;
	u32	reserved2[50];
};

struct vsc9953_sys_pause_cfg {
	u32	pause_cfg[11];
	u32	pause_tot_cfg;
	u32	tail_drop_level[11];
	u32	tot_tail_drop_lvl;
	u32	mac_fc_cfg[10];
};

struct vsc9953_sys_mmgt {
	u16	free_cnt;
};

struct vsc9953_system_reg {
	struct vsc9953_sys_stat	stat;
	struct vsc9953_sys_sys	sys;
	struct vsc9953_sys_pause_cfg	pause_cfg;
	struct vsc9953_sys_mmgt	mmgt;
};

/* END VSC9953 SYS structure */

/* VSC9953 REW structure */

struct	vsc9953_rew_port {
	u32	port_vlan_cfg;
	u32	port_tag_cfg;
	u32	port_port_cfg;
	u32	port_dscp_cfg;
	u32	port_pcp_dei_qos_map_cfg[16];
	u32	reserved[12];
};

struct	vsc9953_rew_common {
	u32	reserve[4];
	u32	dscp_remap_dp1_cfg[64];
	u32	dscp_remap_cfg[64];
};

struct	vsc9953_rew_reg {
	struct vsc9953_rew_port	port[12];
	struct vsc9953_rew_common	common;
};

/* END VSC9953 REW structure */

/* VSC9953 DEVCPU_GCB structure */

struct vsc9953_chip_regs {
	u32	chipd_id;
	u32	gpr;
	u32	soft_rst;
};

struct vsc9953_gpio {
	u32	gpio_out_set[10];
	u32	gpio_out_clr[10];
	u32	gpio_out[10];
	u32	gpio_in[10];
};

struct vsc9953_mii_mng {
	u32	miimstatus;
	u32	reserved1;
	u32	miimcmd;
	u32	miimdata;
	u32	miimcfg;
	u32	miimscan_0;
	u32	miimscan_1;
	u32	miiscan_lst_rslts;
	u32	miiscan_lst_rslts_valid;
};

struct vsc9953_mii_read_scan {
	u32	mii_scan_results_sticky[2];
};

struct vsc9953_devcpu_gcb {
	struct vsc9953_chip_regs	chip_regs;
	struct vsc9953_gpio		gpio;
	struct vsc9953_mii_mng	mii_mng[2];
	struct vsc9953_mii_read_scan	mii_read_scan;
};

/* END VSC9953 DEVCPU_GCB structure */

/* VSC9953 IS* structure */

struct vsc9953_vcap_core_cfg {
	u32	vcap_update_ctrl;
	u32	vcap_mv_cfg;
};

struct vsc9953_vcap {
	struct vsc9953_vcap_core_cfg	vcap_core_cfg;
};

/* END VSC9953 IS* structure */

#define VSC9953_PORT_INFO_INITIALIZER(idx) \
{									\
	.enabled	= 0,						\
	.phyaddr	= 0,						\
	.index		= idx,						\
	.phy_regs	= NULL,						\
	.enet_if	= PHY_INTERFACE_MODE_NONE,			\
	.bus		= NULL,						\
	.phydev		= NULL,						\
}

/* Structure to describe a VSC9953 port */
struct vsc9953_port_info {
	u8	enabled;
	u8	phyaddr;
	int	index;
	void	*phy_regs;
	phy_interface_t	enet_if;
	struct mii_dev	*bus;
	struct phy_device	*phydev;
};

/* Structure to describe a VSC9953 switch */
struct vsc9953_info {
	struct vsc9953_port_info	port[VSC9953_MAX_PORTS];
};

void vsc9953_init(bd_t *bis);

void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
void vsc9953_port_info_set_phy_address(int port_no, int address);
void vsc9953_port_enable(int port_no);
void vsc9953_port_disable(int port_no);
void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);

#endif /* _VSC9953_H_ */
Commit	Line	Data
6706b115 CC	1	/*
	2	* vsc9953.h
	3	*
	4	* Driver for the Vitesse VSC9953 L2 Switch
	5	*
	6	* This software may be used and distributed according to the
	7	* terms of the GNU Public License, Version 2, incorporated
	8	* herein by reference.
	9	*
	10	* Copyright 2013 Freescale Semiconductor, Inc.
	11	*
	12	*/
	13
	14	#ifndef _VSC9953_H_
	15	#define _VSC9953_H_
	16
	17	#include <config.h>
	18	#include <miiphy.h>
	19	#include <asm/types.h>
6706b115 CC	20
	21	#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
	22
	23	#define VSC9953_SYS_OFFSET 0x010000
9de05987	24	#define VSC9953_REW_OFFSET 0x030000
6706b115 CC	25	#define VSC9953_DEV_GMII_OFFSET 0x100000
	26	#define VSC9953_QSYS_OFFSET 0x200000
	27	#define VSC9953_ANA_OFFSET 0x280000
	28	#define VSC9953_DEVCPU_GCB 0x070000
	29	#define VSC9953_ES0 0x040000
	30	#define VSC9953_IS1 0x050000
	31	#define VSC9953_IS2 0x060000
	32
	33	#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
	34	#define VSC9953_PHY_REGS_OFFST 0x0000AC
	35
3cc8cfff	36	/* Macros for vsc9953_chip_regs.soft_rst register */
c4390486	37	#define VSC9953_SOFT_SWC_RST_ENA 0x00000001
3cc8cfff CC	38
3cc8cfff CC	39	/* Macros for vsc9953_sys_sys.reset_cfg register */
c4390486 CC	40	#define VSC9953_CORE_ENABLE 0x80
	41	#define VSC9953_MEM_ENABLE 0x40
	42	#define VSC9953_MEM_INIT 0x20
6706b115	43
3cc8cfff	44	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
c4390486	45	#define VSC9953_MAC_ENA_CFG 0x00000011
3cc8cfff CC	46
3cc8cfff CC	47	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
c4390486	48	#define VSC9953_MAC_MODE_CFG 0x00000011
3cc8cfff CC	49
3cc8cfff CC	50	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
c4390486	51	#define VSC9953_MAC_IFG_CFG 0x00000515
3cc8cfff CC	52
3cc8cfff CC	53	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
c4390486	54	#define VSC9953_MAC_HDX_CFG 0x00001043
3cc8cfff CC	55
	56	/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
	57	#define VSC9953_MAC_MAX_LEN 0x000005ee
	58
	59	/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
c4390486 CC	60	#define VSC9953_CLOCK_CFG 0x00000001
c4390486 CC	61	#define VSC9953_CLOCK_CFG_1000M 0x00000001
3cc8cfff CC	62
	63	/* Macros for vsc9953_sys_sys.front_port_mode register */
	64	#define VSC9953_FRONT_PORT_MODE 0x00000000
	65
	66	/* Macros for vsc9953_ana_pfc.pfc_cfg register */
c4390486 CC	67	#define VSC9953_PFC_FC 0x00000001
c4390486 CC	68	#define VSC9953_PFC_FC_QSGMII 0x00000000
3cc8cfff CC	69
3cc8cfff CC	70	/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
c4390486 CC	71	#define VSC9953_MAC_FC_CFG 0x04700000
c4390486 CC	72	#define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
3cc8cfff CC	73
3cc8cfff CC	74	/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
c4390486	75	#define VSC9953_PAUSE_CFG 0x001ffffe
3cc8cfff CC	76
3cc8cfff CC	77	/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
c4390486	78	#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
6706b115	79
3cc8cfff	80	/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
c4390486 CC	81	#define VSC9953_VCAP_MV_CFG 0x0000ffff
c4390486 CC	82	#define VSC9953_VCAP_UPDATE_CTRL 0x01000004
3cc8cfff	83
9de05987 CC	84	/* Macros for vsc9953_ana_port.vlan_cfg register */
	85	#define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
	86	#define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
	87	#define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
	88
	89	/* Macros for vsc9953_rew_port.port_vlan_cfg register */
	90	#define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
	91
	92	/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
	93	#define VSC9953_ANA_TBL_VID_MASK 0x00000fff
	94
	95	/* Macros for vsc9953_ana_ana_tables.vlan_access register */
	96	#define VSC9953_VLAN_PORT_MASK 0x00001ffc
	97	#define VSC9953_VLAN_CMD_MASK 0x00000003
	98	#define VSC9953_VLAN_CMD_IDLE 0x00000000
	99	#define VSC9953_VLAN_CMD_READ 0x00000001
	100	#define VSC9953_VLAN_CMD_WRITE 0x00000002
	101	#define VSC9953_VLAN_CMD_INIT 0x00000003
	102
3cc8cfff	103	/* Macros for vsc9953_qsys_sys.switch_port_mode register */
fe91095b	104	#define VSC9953_PORT_ENA 0x00002000
3cc8cfff	105
9de05987 CC	106	/* Macros for vsc9953_ana_ana.adv_learn register */
	107	#define VSC9953_VLAN_CHK 0x00000400
	108
	109	/* Macros for vsc9953_rew_port.port_tag_cfg register */
	110	#define VSC9953_TAG_CFG_MASK 0x00000180
	111	#define VSC9953_TAG_CFG_NONE 0x00000000
	112	#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
	113	#define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
	114	#define VSC9953_TAG_CFG_ALL 0x00000180
	115
6706b115 CC	116	#define VSC9953_MAX_PORTS 10
	117	#define VSC9953_PORT_CHECK(port) \
	118	(((port) < 0 \|\| (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
	119	#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
	120	( \
	121	(port) < VSC9953_MAX_PORTS - 2 \|\| (port) >= VSC9953_MAX_PORTS \
	122	) ? 0 : 1 \
	123	)
9de05987 CC	124	#define VSC9953_MAX_VLAN 4096
	125	#define VSC9953_VLAN_CHECK(vid) \
	126	(((vid) < 0 \|\| (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
6706b115 CC	127
	128	#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
	129
	130	#define MIIMIND_OPR_PEND 0x00000004
	131
	132	struct vsc9953_mdio_info {
	133	struct vsc9953_mii_mng *regs;
	134	char *name;
	135	};
	136
3cc8cfff	137	/* VSC9953 ANA structure */
6706b115	138
3cc8cfff	139	struct vsc9953_ana_port {
6706b115 CC	140	u32 vlan_cfg;
	141	u32 drop_cfg;
	142	u32 qos_cfg;
	143	u32 vcap_cfg;
	144	u32 vcap_s1_key_cfg[3];
	145	u32 vcap_s2_cfg;
	146	u32 qos_pcp_dei_map_cfg[16];
	147	u32 cpu_fwd_cfg;
	148	u32 cpu_fwd_bpdu_cfg;
	149	u32 cpu_fwd_garp_cfg;
	150	u32 cpu_fwd_ccm_cfg;
	151	u32 port_cfg;
	152	u32 pol_cfg;
	153	u32 reserved[34];
	154	};
	155
	156	struct vsc9953_ana_pol {
	157	u32 pol_pir_cfg;
	158	u32 pol_cir_cfg;
	159	u32 pol_mode_cfg;
	160	u32 pol_pir_state;
	161	u32 pol_cir_state;
	162	u32 reserved1[3];
	163	};
	164
	165	struct vsc9953_ana_ana_tables {
	166	u32 entry_lim[11];
	167	u32 an_moved;
	168	u32 mach_data;
	169	u32 macl_data;
	170	u32 mac_access;
	171	u32 mact_indx;
	172	u32 vlan_access;
	173	u32 vlan_tidx;
	174	};
	175
	176	struct vsc9953_ana_ana {
	177	u32 adv_learn;
	178	u32 vlan_mask;
440873df	179	u32 reserved;
6706b115 CC	180	u32 anag_efil;
	181	u32 an_events;
	182	u32 storm_limit_burst;
	183	u32 storm_limit_cfg[4];
	184	u32 isolated_prts;
	185	u32 community_ports;
	186	u32 auto_age;
	187	u32 mac_options;
	188	u32 learn_disc;
	189	u32 agen_ctrl;
	190	u32 mirror_ports;
	191	u32 emirror_ports;
	192	u32 flooding;
	193	u32 flooding_ipmc;
	194	u32 sflow_cfg[11];
	195	u32 port_mode[12];
	196	};
	197
	198	struct vsc9953_ana_pgid {
	199	u32 port_grp_id[91];
	200	};
	201
3cc8cfff	202	struct vsc9953_ana_pfc {
6706b115 CC	203	u32 pfc_cfg;
	204	u32 reserved1[15];
	205	};
	206
	207	struct vsc9953_ana_pol_misc {
	208	u32 pol_flowc[10];
	209	u32 reserved1[17];
	210	u32 pol_hyst;
	211	};
	212
3cc8cfff	213	struct vsc9953_ana_common {
6706b115 CC	214	u32 aggr_cfg;
	215	u32 cpuq_cfg;
	216	u32 cpuq_8021_cfg;
	217	u32 dscp_cfg;
	218	u32 dscp_rewr_cfg;
	219	u32 vcap_rng_type_cfg;
	220	u32 vcap_rng_val_cfg;
	221	u32 discard_cfg;
	222	u32 fid_cfg;
	223	};
	224
	225	struct vsc9953_analyzer {
	226	struct vsc9953_ana_port port[11];
	227	u32 reserved1[9536];
	228	struct vsc9953_ana_pol pol[164];
	229	struct vsc9953_ana_ana_tables ana_tables;
	230	u32 reserved2[14];
	231	struct vsc9953_ana_ana ana;
	232	u32 reserved3[22];
	233	struct vsc9953_ana_pgid port_id_tbl;
	234	u32 reserved4[549];
	235	struct vsc9953_ana_pfc pfc[10];
	236	struct vsc9953_ana_pol_misc pol_misc;
	237	u32 reserved5[196];
	238	struct vsc9953_ana_common common;
	239	};
3cc8cfff	240	/* END VSC9953 ANA structure t*/
6706b115	241
3cc8cfff	242	/* VSC9953 DEV_GMII structure */
6706b115	243
3cc8cfff	244	struct vsc9953_dev_gmii_port_mode {
6706b115 CC	245	u32 clock_cfg;
	246	u32 port_misc;
	247	u32 reserved1;
	248	u32 eee_cfg;
	249	};
	250
3cc8cfff	251	struct vsc9953_dev_gmii_mac_cfg_status {
6706b115 CC	252	u32 mac_ena_cfg;
	253	u32 mac_mode_cfg;
	254	u32 mac_maxlen_cfg;
	255	u32 mac_tags_cfg;
	256	u32 mac_adv_chk_cfg;
	257	u32 mac_ifg_cfg;
	258	u32 mac_hdx_cfg;
	259	u32 mac_fc_mac_low_cfg;
	260	u32 mac_fc_mac_high_cfg;
	261	u32 mac_sticky;
	262	};
	263
	264	struct vsc9953_dev_gmii {
	265	struct vsc9953_dev_gmii_port_mode port_mode;
	266	struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
	267	};
	268
3cc8cfff	269	/* END VSC9953 DEV_GMII structure */
6706b115	270
3cc8cfff	271	/* VSC9953 QSYS structure */
6706b115	272
3cc8cfff	273	struct vsc9953_qsys_hsch {
6706b115 CC	274	u32 cir_cfg;
	275	u32 reserved1;
	276	u32 se_cfg;
	277	u32 se_dwrr_cfg[8];
	278	u32 cir_state;
	279	u32 reserved2[20];
	280	};
	281
3cc8cfff	282	struct vsc9953_qsys_sys {
6706b115 CC	283	u32 port_mode[12];
	284	u32 switch_port_mode[11];
	285	u32 stat_cnt_cfg;
	286	u32 eee_cfg[10];
	287	u32 eee_thrs;
	288	u32 igr_no_sharing;
	289	u32 egr_no_sharing;
	290	u32 sw_status[11];
	291	u32 ext_cpu_cfg;
	292	u32 cpu_group_map;
	293	u32 reserved1[23];
	294	};
	295
3cc8cfff	296	struct vsc9953_qsys_qos_cfg {
6706b115 CC	297	u32 red_profile[16];
	298	u32 res_qos_mode;
	299	};
	300
3cc8cfff	301	struct vsc9953_qsys_drop_cfg {
6706b115 CC	302	u32 egr_drop_mode;
	303	};
	304
3cc8cfff	305	struct vsc9953_qsys_mmgt {
6706b115 CC	306	u32 eq_cntrl;
	307	u32 reserved1;
	308	};
	309
3cc8cfff	310	struct vsc9953_qsys_hsch_misc {
6706b115 CC	311	u32 hsch_misc_cfg;
	312	u32 reserved1[546];
	313	};
	314
3cc8cfff	315	struct vsc9953_qsys_res_ctrl {
6706b115 CC	316	u32 res_cfg;
	317	u32 res_stat;
	318
	319	};
	320
3cc8cfff	321	struct vsc9953_qsys_reg {
6706b115 CC	322	struct vsc9953_qsys_hsch hsch[108];
	323	struct vsc9953_qsys_sys sys;
	324	struct vsc9953_qsys_qos_cfg qos_cfg;
	325	struct vsc9953_qsys_drop_cfg drop_cfg;
	326	struct vsc9953_qsys_mmgt mmgt;
	327	struct vsc9953_qsys_hsch_misc hsch_misc;
	328	struct vsc9953_qsys_res_ctrl res_ctrl[1024];
	329	};
	330
3cc8cfff	331	/* END VSC9953 QSYS structure */
6706b115	332
3cc8cfff	333	/* VSC9953 SYS structure */
6706b115	334
3cc8cfff	335	struct vsc9953_sys_stat {
6706b115 CC	336	u32 rx_cntrs[64];
	337	u32 tx_cntrs[64];
	338	u32 drop_cntrs[64];
	339	u32 reserved1[6];
	340	};
	341
3cc8cfff	342	struct vsc9953_sys_sys {
6706b115 CC	343	u32 reset_cfg;
	344	u32 reserved1;
	345	u32 vlan_etype_cfg;
	346	u32 port_mode[12];
	347	u32 front_port_mode[10];
	348	u32 frame_aging;
	349	u32 stat_cfg;
	350	u32 reserved2[50];
	351	};
	352
3cc8cfff	353	struct vsc9953_sys_pause_cfg {
6706b115 CC	354	u32 pause_cfg[11];
	355	u32 pause_tot_cfg;
	356	u32 tail_drop_level[11];
	357	u32 tot_tail_drop_lvl;
	358	u32 mac_fc_cfg[10];
	359	};
	360
3cc8cfff	361	struct vsc9953_sys_mmgt {
6706b115 CC	362	u16 free_cnt;
	363	};
	364
3cc8cfff	365	struct vsc9953_system_reg {
6706b115 CC	366	struct vsc9953_sys_stat stat;
	367	struct vsc9953_sys_sys sys;
	368	struct vsc9953_sys_pause_cfg pause_cfg;
	369	struct vsc9953_sys_mmgt mmgt;
	370	};
	371
3cc8cfff	372	/* END VSC9953 SYS structure */
6706b115	373
9de05987 CC	374	/* VSC9953 REW structure */
	375
	376	struct vsc9953_rew_port {
	377	u32 port_vlan_cfg;
	378	u32 port_tag_cfg;
	379	u32 port_port_cfg;
	380	u32 port_dscp_cfg;
	381	u32 port_pcp_dei_qos_map_cfg[16];
	382	u32 reserved[12];
	383	};
	384
	385	struct vsc9953_rew_common {
	386	u32 reserve[4];
	387	u32 dscp_remap_dp1_cfg[64];
	388	u32 dscp_remap_cfg[64];
	389	};
	390
	391	struct vsc9953_rew_reg {
	392	struct vsc9953_rew_port port[12];
	393	struct vsc9953_rew_common common;
	394	};
	395
	396	/* END VSC9953 REW structure */
6706b115	397
3cc8cfff	398	/* VSC9953 DEVCPU_GCB structure */
6706b115	399
3cc8cfff	400	struct vsc9953_chip_regs {
6706b115 CC	401	u32 chipd_id;
	402	u32 gpr;
	403	u32 soft_rst;
	404	};
	405
3cc8cfff	406	struct vsc9953_gpio {
6706b115 CC	407	u32 gpio_out_set[10];
	408	u32 gpio_out_clr[10];
	409	u32 gpio_out[10];
	410	u32 gpio_in[10];
	411	};
	412
	413	struct vsc9953_mii_mng {
	414	u32 miimstatus;
	415	u32 reserved1;
	416	u32 miimcmd;
	417	u32 miimdata;
	418	u32 miimcfg;
	419	u32 miimscan_0;
	420	u32 miimscan_1;
	421	u32 miiscan_lst_rslts;
	422	u32 miiscan_lst_rslts_valid;
	423	};
	424
3cc8cfff	425	struct vsc9953_mii_read_scan {
6706b115 CC	426	u32 mii_scan_results_sticky[2];
	427	};
	428
3cc8cfff	429	struct vsc9953_devcpu_gcb {
6706b115 CC	430	struct vsc9953_chip_regs chip_regs;
	431	struct vsc9953_gpio gpio;
	432	struct vsc9953_mii_mng mii_mng[2];
	433	struct vsc9953_mii_read_scan mii_read_scan;
	434	};
	435
3cc8cfff	436	/* END VSC9953 DEVCPU_GCB structure */
6706b115	437
3cc8cfff	438	/* VSC9953 IS* structure */
6706b115	439
3cc8cfff	440	struct vsc9953_vcap_core_cfg {
6706b115 CC	441	u32 vcap_update_ctrl;
	442	u32 vcap_mv_cfg;
	443	};
	444
3cc8cfff CC	445	struct vsc9953_vcap {
3cc8cfff CC	446	struct vsc9953_vcap_core_cfg vcap_core_cfg;
6706b115 CC	447	};
6706b115 CC	448
3cc8cfff	449	/* END VSC9953 IS* structure */
6706b115 CC	450
	451	#define VSC9953_PORT_INFO_INITIALIZER(idx) \
	452	{ \
	453	.enabled = 0, \
	454	.phyaddr = 0, \
	455	.index = idx, \
	456	.phy_regs = NULL, \
	457	.enet_if = PHY_INTERFACE_MODE_NONE, \
	458	.bus = NULL, \
	459	.phydev = NULL, \
	460	}
	461
	462	/* Structure to describe a VSC9953 port */
	463	struct vsc9953_port_info {
	464	u8 enabled;
	465	u8 phyaddr;
	466	int index;
	467	void *phy_regs;
	468	phy_interface_t enet_if;
	469	struct mii_dev *bus;
	470	struct phy_device *phydev;
	471	};
	472
	473	/* Structure to describe a VSC9953 switch */
	474	struct vsc9953_info {
3cc8cfff	475	struct vsc9953_port_info port[VSC9953_MAX_PORTS];
6706b115 CC	476	};
	477
	478	void vsc9953_init(bd_t *bis);
	479
3cc8cfff CC	480	void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
	481	void vsc9953_port_info_set_phy_address(int port_no, int address);
	482	void vsc9953_port_enable(int port_no);
	483	void vsc9953_port_disable(int port_no);
	484	void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
6706b115 CC	485
6706b115 CC	486	#endif /* _VSC9953_H_ */