[J-u-boot.git] / board / freescale / mpc8572ds / tlb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),

	/* TLB 1 */
	/* *I*** - Covers boot page */
	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 0, BOOKE_PAGESZ_4K, 1),

	/* *I*G* - CCSRBAR */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 1, BOOKE_PAGESZ_1M, 1),

	/* W**G* - Flash/promjet, localbus */
	/* This will be changed to *I*G* after relocation to RAM. */
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
		      0, 2, BOOKE_PAGESZ_256M, 1),

#ifndef CONFIG_NAND_SPL
	/* *I*G* - PCI */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 3, BOOKE_PAGESZ_1G, 1),

	/* *I*G* - PCI */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 4, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 5, BOOKE_PAGESZ_256M, 1),

	/* *I*G* - PCI I/O */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 6, BOOKE_PAGESZ_256K, 1),
#endif

	/* *I*G - NAND */
	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 7, BOOKE_PAGESZ_1M, 1),

	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 8, BOOKE_PAGESZ_4K, 1),

#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	/* *I*G - L2SRAM */
	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
			CONFIG_SYS_INIT_L2_ADDR_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, 9, BOOKE_PAGESZ_256K, 1),
	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, 10, BOOKE_PAGESZ_256K, 1),
#endif
};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
129ba616	2	/*
cb14e93b	3	* Copyright 2008-2010 Freescale Semiconductor, Inc.
129ba616 KG	4	*
	5	* (C) Copyright 2000
	6	* Wolfgang Denk, DENX Software Engineering, [email protected].
129ba616 KG	7	*/
	8
	9	#include <common.h>
	10	#include <asm/mmu.h>
	11
	12	struct fsl_e_tlb_entry tlb_table[] = {
	13	/* TLB 0 - for temp stack in cache */
6d0f6bcf	14	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
129ba616 KG	15	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
129ba616 KG	16	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	17	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
129ba616 KG	18	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
129ba616 KG	19	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	20	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
129ba616 KG	21	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
129ba616 KG	22	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	23	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
129ba616 KG	24	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	25	0, 0, BOOKE_PAGESZ_4K, 0),
	26
129ba616 KG	27	/* TLB 1 */
	28	/* I** - Covers boot page */
	29	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
abc76eb6	30	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
129ba616 KG	31	0, 0, BOOKE_PAGESZ_4K, 1),
	32
	33	/* IG* - CCSRBAR */
6d0f6bcf	34	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
129ba616 KG	35	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	36	0, 1, BOOKE_PAGESZ_1M, 1),
	37
	38	/* W*G - Flash/promjet, localbus */
	39	/* This will be changed to IG* after relocation to RAM. */
c953ddfd	40	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
7c0d4a75	41	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
129ba616 KG	42	0, 2, BOOKE_PAGESZ_256M, 1),
129ba616 KG	43
e4382acb	44	#ifndef CONFIG_NAND_SPL
129ba616	45	/* IG* - PCI */
5af0fdd8	46	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
129ba616 KG	47	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	48	0, 3, BOOKE_PAGESZ_1G, 1),
	49
	50	/* IG* - PCI */
5af0fdd8	51	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
129ba616 KG	52	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	53	0, 4, BOOKE_PAGESZ_256M, 1),
	54
5af0fdd8	55	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
129ba616 KG	56	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	57	0, 5, BOOKE_PAGESZ_256M, 1),
	58
	59	/* IG* - PCI I/O */
aca5f018	60	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
129ba616 KG	61	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
129ba616 KG	62	0, 6, BOOKE_PAGESZ_256K, 1),
e4382acb	63	#endif
c013b749 HW	64
	65	/* IG - NAND */
	66	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
	67	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	68	0, 7, BOOKE_PAGESZ_1M, 1),
	69
52b565f5	70	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
b5f65dfa HW	71	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
b5f65dfa HW	72	0, 8, BOOKE_PAGESZ_4K, 1),
cb14e93b KG	73
	74	#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	75	/* IG - L2SRAM */
	76	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
	77	CONFIG_SYS_INIT_L2_ADDR_PHYS,
	78	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	79	0, 9, BOOKE_PAGESZ_256K, 1),
	80	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
	81	CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
	82	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	83	0, 10, BOOKE_PAGESZ_256K, 1),
	84	#endif
129ba616 KG	85	};
	86
	87	int num_tlb_entries = ARRAY_SIZE(tlb_table);