[J-u-boot.git] / drivers / ata / sata_ceva.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2015 - 2016 Xilinx, Inc.
 * Michal Simek <[email protected]>
 */
#include <dm.h>
#include <ahci.h>
#include <generic-phy.h>
#include <log.h>
#include <reset.h>
#include <scsi.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/ioport.h>

/* Vendor Specific Register Offsets */
#define AHCI_VEND_PCFG  0xA4
#define AHCI_VEND_PPCFG 0xA8
#define AHCI_VEND_PP2C  0xAC
#define AHCI_VEND_PP3C  0xB0
#define AHCI_VEND_PP4C  0xB4
#define AHCI_VEND_PP5C  0xB8
#define AHCI_VEND_AXICC 0xBc
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC   0xC8

/* Vendor Specific Register bit definitions */
#define PAXIC_ADBW_BW64 0x1
#define PAXIC_MAWIDD	(1 << 8)
#define PAXIC_MARIDD	(1 << 16)
#define PAXIC_OTL	(0x4 << 20)

#define PCFG_TPSS_VAL	(0x32 << 16)
#define PCFG_TPRS_VAL	(0x2 << 12)
#define PCFG_PAD_VAL	0x2

#define PPCFG_TTA	0x1FFFE
#define PPCFG_PSSO_EN	(1 << 28)
#define PPCFG_PSS_EN	(1 << 29)
#define PPCFG_ESDF_EN	(1 << 31)

#define PP2C_CIBGMN	0x0F
#define PP2C_CIBGMX	(0x25 << 8)
#define PP2C_CIBGN	(0x18 << 16)
#define PP2C_CINMP	(0x29 << 24)

#define PP3C_CWBGMN	0x04
#define PP3C_CWBGMX	(0x0B << 8)
#define PP3C_CWBGN	(0x08 << 16)
#define PP3C_CWNMP	(0x0F << 24)

#define PP4C_BMX	0x0a
#define PP4C_BNM	(0x08 << 8)
#define PP4C_SFD	(0x4a << 16)
#define PP4C_PTST	(0x06 << 24)

#define PP5C_RIT	0x60216
#define PP5C_RCT	(0x7f0 << 20)

#define PTC_RX_WM_VAL	0x40
#define PTC_RSVD	(1 << 27)

#define PORT0_BASE	0x100
#define PORT1_BASE	0x180

/* Port Control Register Bit Definitions */
#define PORT_SCTL_SPD_GEN3	(0x3 << 4)
#define PORT_SCTL_SPD_GEN2	(0x2 << 4)
#define PORT_SCTL_SPD_GEN1	(0x1 << 4)
#define PORT_SCTL_IPM		(0x3 << 8)

#define PORT_BASE	0x100
#define PORT_OFFSET	0x80
#define NR_PORTS	2
#define DRV_NAME	"ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2	1

/* flag bit definition */
#define FLAG_COHERENT	1

/* register config value */
#define CEVA_PHY1_CFG	0xa003fffe
#define CEVA_PHY2_CFG	0x28184d1f
#define CEVA_PHY3_CFG	0x0e081509
#define CEVA_TRANS_CFG	0x08000029
#define CEVA_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021_AHCI_VEND_AXICC	0xC0
#define LS1021_CEVA_PHY2_CFG	0x28183414
#define LS1021_CEVA_PHY3_CFG	0x0e080e06
#define LS1021_CEVA_PHY4_CFG	0x064a080b
#define LS1021_CEVA_PHY5_CFG	0x2aa86470

/* ecc val pair */
#define ECC_DIS_VAL_CH1		0x00020000
#define ECC_DIS_VAL_CH2		0x80000000
#define ECC_DIS_VAL_CH3		0x40000000

enum ceva_soc {
	CEVA_1V84,
	CEVA_LS1012A,
	CEVA_LS1021A,
	CEVA_LS1028A,
	CEVA_LS1043A,
	CEVA_LS1046A,
	CEVA_LS1088A,
	CEVA_LS2080A,
};

struct ceva_sata_priv {
	ulong base;
	ulong ecc_base;
	enum ceva_soc soc;
	ulong flag;
};

static int ceva_init_sata(struct ceva_sata_priv *priv)
{
	ulong ecc_addr = priv->ecc_base;
	ulong base = priv->base;
	ulong tmp;

	switch (priv->soc) {
	case CEVA_1V84:
		tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
		writel(tmp, base + AHCI_VEND_PAXIC);
		tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
		writel(tmp, base + AHCI_VEND_PCFG);
		tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
		writel(tmp, base + AHCI_VEND_PPCFG);
		tmp = PTC_RX_WM_VAL | PTC_RSVD;
		writel(tmp, base + AHCI_VEND_PTC);
		break;

	case CEVA_LS1021A:
		if (!ecc_addr)
			return -EINVAL;
		writel(ECC_DIS_VAL_CH1, ecc_addr);
		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
		writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
		writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
		writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
		writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
		break;

	case CEVA_LS1012A:
	case CEVA_LS1043A:
	case CEVA_LS1046A:
		if (!ecc_addr)
			return -EINVAL;
		writel(ECC_DIS_VAL_CH2, ecc_addr);
		/* fallthrough */
	case CEVA_LS2080A:
		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
		break;

	case CEVA_LS1028A:
	case CEVA_LS1088A:
		if (!ecc_addr)
			return -EINVAL;
		writel(ECC_DIS_VAL_CH3, ecc_addr);
		writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
		writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
		break;
	}

	if (priv->flag & FLAG_COHERENT)
		writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);

	return 0;
}

static int sata_ceva_bind(struct udevice *dev)
{
	struct udevice *scsi_dev;

	return ahci_bind_scsi(dev, &scsi_dev);
}

static int sata_ceva_probe(struct udevice *dev)
{
	struct ceva_sata_priv *priv = dev_get_priv(dev);
	struct phy phy;
	int ret;
	struct reset_ctl_bulk resets;

	ret = generic_phy_get_by_index(dev, 0, &phy);
	if (!ret) {
		dev_dbg(dev, "Perform PHY initialization\n");
		ret = generic_phy_init(&phy);
		if (ret)
			return ret;
	} else if (ret != -ENOENT) {
		dev_dbg(dev, "could not get phy (err %d)\n", ret);
		return ret;
	}

	/* reset is optional */
	ret = reset_get_bulk(dev, &resets);
	if (ret && ret != -ENOTSUPP && ret != -ENOENT) {
		dev_dbg(dev, "Getting reset fails (err %d)\n", ret);
		return ret;
	}

	/* Just trigger reset when reset is specified */
	if (!ret) {
		dev_dbg(dev, "Perform IP reset\n");
		ret = reset_deassert_bulk(&resets);
		if (ret) {
			dev_dbg(dev, "Reset fails (err %d)\n", ret);
			reset_release_bulk(&resets);
			return ret;
		}
	}

	if (generic_phy_valid(&phy)) {
		dev_dbg(dev, "Perform PHY power on\n");
		ret = generic_phy_power_on(&phy);
		if (ret) {
			dev_dbg(dev, "PHY power on failed (err %d)\n", ret);
			return ret;
		}
	}

	ceva_init_sata(priv);

	return ahci_probe_scsi(dev, priv->base);
}

static const struct udevice_id sata_ceva_ids[] = {
	{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
	{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
	{ .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
	{ .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
	{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
	{ .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
	{ .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
	{ .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
	{ }
};

static int sata_ceva_of_to_plat(struct udevice *dev)
{
	struct ceva_sata_priv *priv = dev_get_priv(dev);
	struct resource res_regs;
	int ret;

	if (dev_read_bool(dev, "dma-coherent"))
		priv->flag |= FLAG_COHERENT;

	priv->base = dev_read_addr(dev);
	if (priv->base == FDT_ADDR_T_NONE)
		return -EINVAL;

	ret = dev_read_resource_byname(dev, "sata-ecc", &res_regs);
	if (ret)
		priv->ecc_base = 0;
	else
		priv->ecc_base = res_regs.start;

	priv->soc = dev_get_driver_data(dev);

	debug("ccsr-sata-base %lx\t ecc-base %lx\n",
	      priv->base,
	      priv->ecc_base);

	return 0;
}

U_BOOT_DRIVER(ceva_host_blk) = {
	.name = "ceva_sata",
	.id = UCLASS_AHCI,
	.of_match = sata_ceva_ids,
	.bind = sata_ceva_bind,
	.ops = &scsi_ops,
	.priv_auto	= sizeof(struct ceva_sata_priv),
	.probe = sata_ceva_probe,
	.of_to_plat = sata_ceva_of_to_plat,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
679b994a MS	2	/*
679b994a MS	3	* (C) Copyright 2015 - 2016 Xilinx, Inc.
174d7284	4	* Michal Simek <[email protected]>
679b994a	5	*/
49c4c78e	6	#include <dm.h>
679b994a	7	#include <ahci.h>
f6f5451d	8	#include <generic-phy.h>
f7ae49fc	9	#include <log.h>
f6f5451d	10	#include <reset.h>
679b994a	11	#include <scsi.h>
679b994a	12	#include <asm/io.h>
f6f5451d	13	#include <dm/device_compat.h>
d2ebc382	14	#include <linux/ioport.h>
679b994a MS	15
	16	/* Vendor Specific Register Offsets */
	17	#define AHCI_VEND_PCFG 0xA4
	18	#define AHCI_VEND_PPCFG 0xA8
	19	#define AHCI_VEND_PP2C 0xAC
	20	#define AHCI_VEND_PP3C 0xB0
	21	#define AHCI_VEND_PP4C 0xB4
	22	#define AHCI_VEND_PP5C 0xB8
79ed61e9	23	#define AHCI_VEND_AXICC 0xBc
679b994a MS	24	#define AHCI_VEND_PAXIC 0xC0
	25	#define AHCI_VEND_PTC 0xC8
	26
	27	/* Vendor Specific Register bit definitions */
	28	#define PAXIC_ADBW_BW64 0x1
	29	#define PAXIC_MAWIDD (1 << 8)
	30	#define PAXIC_MARIDD (1 << 16)
	31	#define PAXIC_OTL (0x4 << 20)
	32
	33	#define PCFG_TPSS_VAL (0x32 << 16)
	34	#define PCFG_TPRS_VAL (0x2 << 12)
	35	#define PCFG_PAD_VAL 0x2
	36
	37	#define PPCFG_TTA 0x1FFFE
	38	#define PPCFG_PSSO_EN (1 << 28)
	39	#define PPCFG_PSS_EN (1 << 29)
	40	#define PPCFG_ESDF_EN (1 << 31)
	41
	42	#define PP2C_CIBGMN 0x0F
	43	#define PP2C_CIBGMX (0x25 << 8)
	44	#define PP2C_CIBGN (0x18 << 16)
	45	#define PP2C_CINMP (0x29 << 24)
	46
	47	#define PP3C_CWBGMN 0x04
	48	#define PP3C_CWBGMX (0x0B << 8)
	49	#define PP3C_CWBGN (0x08 << 16)
	50	#define PP3C_CWNMP (0x0F << 24)
	51
	52	#define PP4C_BMX 0x0a
	53	#define PP4C_BNM (0x08 << 8)
	54	#define PP4C_SFD (0x4a << 16)
	55	#define PP4C_PTST (0x06 << 24)
	56
	57	#define PP5C_RIT 0x60216
	58	#define PP5C_RCT (0x7f0 << 20)
	59
	60	#define PTC_RX_WM_VAL 0x40
	61	#define PTC_RSVD (1 << 27)
	62
	63	#define PORT0_BASE 0x100
	64	#define PORT1_BASE 0x180
	65
	66	/* Port Control Register Bit Definitions */
	67	#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
	68	#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
	69	#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
	70	#define PORT_SCTL_IPM (0x3 << 8)
	71
	72	#define PORT_BASE 0x100
	73	#define PORT_OFFSET 0x80
	74	#define NR_PORTS 2
	75	#define DRV_NAME "ahci-ceva"
	76	#define CEVA_FLAG_BROKEN_GEN2 1
	77
79ed61e9 YT	78	/* flag bit definition */
	79	#define FLAG_COHERENT 1
	80
	81	/* register config value */
	82	#define CEVA_PHY1_CFG 0xa003fffe
	83	#define CEVA_PHY2_CFG 0x28184d1f
	84	#define CEVA_PHY3_CFG 0x0e081509
	85	#define CEVA_TRANS_CFG 0x08000029
	86	#define CEVA_AXICC_CFG 0x3fffffff
	87
df983a76	88	/* for ls1021a */
aaaffe90	89	#define LS1021_AHCI_VEND_AXICC 0xC0
df983a76 PM	90	#define LS1021_CEVA_PHY2_CFG 0x28183414
	91	#define LS1021_CEVA_PHY3_CFG 0x0e080e06
	92	#define LS1021_CEVA_PHY4_CFG 0x064a080b
	93	#define LS1021_CEVA_PHY5_CFG 0x2aa86470
	94
d2ebc382 PM	95	/* ecc val pair */
d2ebc382 PM	96	#define ECC_DIS_VAL_CH1 0x00020000
aaaffe90	97	#define ECC_DIS_VAL_CH2 0x80000000
d2ebc382	98	#define ECC_DIS_VAL_CH3 0x40000000
79ed61e9 YT	99
	100	enum ceva_soc {
	101	CEVA_1V84,
	102	CEVA_LS1012A,
df983a76	103	CEVA_LS1021A,
d2ebc382	104	CEVA_LS1028A,
822d0608	105	CEVA_LS1043A,
5fcae597	106	CEVA_LS1046A,
aaaffe90	107	CEVA_LS1088A,
1039d1ac	108	CEVA_LS2080A,
79ed61e9 YT	109	};
79ed61e9 YT	110
c3898a88 MS	111	struct ceva_sata_priv {
c3898a88 MS	112	ulong base;
d2ebc382	113	ulong ecc_base;
79ed61e9 YT	114	enum ceva_soc soc;
79ed61e9 YT	115	ulong flag;
c3898a88 MS	116	};
c3898a88 MS	117
79ed61e9	118	static int ceva_init_sata(struct ceva_sata_priv *priv)
679b994a	119	{
d2ebc382	120	ulong ecc_addr = priv->ecc_base;
79ed61e9	121	ulong base = priv->base;
679b994a	122	ulong tmp;
679b994a	123
79ed61e9 YT	124	switch (priv->soc) {
	125	case CEVA_1V84:
	126	tmp = PAXIC_ADBW_BW64 \| PAXIC_MAWIDD \| PAXIC_MARIDD \| PAXIC_OTL;
	127	writel(tmp, base + AHCI_VEND_PAXIC);
	128	tmp = PCFG_TPSS_VAL \| PCFG_TPRS_VAL \| PCFG_PAD_VAL;
	129	writel(tmp, base + AHCI_VEND_PCFG);
	130	tmp = PPCFG_TTA \| PPCFG_PSS_EN \| PPCFG_ESDF_EN;
	131	writel(tmp, base + AHCI_VEND_PPCFG);
679b994a	132	tmp = PTC_RX_WM_VAL \| PTC_RSVD;
79ed61e9 YT	133	writel(tmp, base + AHCI_VEND_PTC);
	134	break;
	135
df983a76	136	case CEVA_LS1021A:
d2ebc382 PM	137	if (!ecc_addr)
	138	return -EINVAL;
	139	writel(ECC_DIS_VAL_CH1, ecc_addr);
df983a76 PM	140	writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
	141	writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
	142	writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
	143	writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
	144	writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
	145	writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
df983a76 PM	146	break;
df983a76 PM	147
79ed61e9	148	case CEVA_LS1012A:
822d0608	149	case CEVA_LS1043A:
5fcae597	150	case CEVA_LS1046A:
d2ebc382 PM	151	if (!ecc_addr)
	152	return -EINVAL;
	153	writel(ECC_DIS_VAL_CH2, ecc_addr);
1039d1ac PM	154	/* fallthrough */
1039d1ac PM	155	case CEVA_LS2080A:
aaaffe90 PM	156	writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
aaaffe90 PM	157	writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
aaaffe90 PM	158	break;
aaaffe90 PM	159
d2ebc382	160	case CEVA_LS1028A:
aaaffe90	161	case CEVA_LS1088A:
d2ebc382 PM	162	if (!ecc_addr)
	163	return -EINVAL;
	164	writel(ECC_DIS_VAL_CH3, ecc_addr);
79ed61e9 YT	165	writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
79ed61e9 YT	166	writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
79ed61e9	167	break;
679b994a	168	}
79ed61e9	169
d2ebc382 PM	170	if (priv->flag & FLAG_COHERENT)
	171	writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
	172
679b994a MS	173	return 0;
679b994a MS	174	}
49c4c78e	175
c3898a88	176	static int sata_ceva_bind(struct udevice *dev)
49c4c78e	177	{
c3898a88 MS	178	struct udevice *scsi_dev;
	179
	180	return ahci_bind_scsi(dev, &scsi_dev);
	181	}
49c4c78e	182
c3898a88 MS	183	static int sata_ceva_probe(struct udevice *dev)
	184	{
	185	struct ceva_sata_priv *priv = dev_get_priv(dev);
f6f5451d MS	186	struct phy phy;
	187	int ret;
	188	struct reset_ctl_bulk resets;
	189
	190	ret = generic_phy_get_by_index(dev, 0, &phy);
	191	if (!ret) {
	192	dev_dbg(dev, "Perform PHY initialization\n");
	193	ret = generic_phy_init(&phy);
	194	if (ret)
	195	return ret;
	196	} else if (ret != -ENOENT) {
	197	dev_dbg(dev, "could not get phy (err %d)\n", ret);
	198	return ret;
	199	}
	200
	201	/* reset is optional */
	202	ret = reset_get_bulk(dev, &resets);
	203	if (ret && ret != -ENOTSUPP && ret != -ENOENT) {
	204	dev_dbg(dev, "Getting reset fails (err %d)\n", ret);
	205	return ret;
	206	}
	207
	208	/* Just trigger reset when reset is specified */
	209	if (!ret) {
	210	dev_dbg(dev, "Perform IP reset\n");
	211	ret = reset_deassert_bulk(&resets);
	212	if (ret) {
	213	dev_dbg(dev, "Reset fails (err %d)\n", ret);
	214	reset_release_bulk(&resets);
	215	return ret;
	216	}
	217	}
	218
017ae492	219	if (generic_phy_valid(&phy)) {
f6f5451d MS	220	dev_dbg(dev, "Perform PHY power on\n");
	221	ret = generic_phy_power_on(&phy);
	222	if (ret) {
	223	dev_dbg(dev, "PHY power on failed (err %d)\n", ret);
	224	return ret;
	225	}
	226	}
7cf1afce	227
79ed61e9	228	ceva_init_sata(priv);
cba64a2a	229
c3898a88	230	return ahci_probe_scsi(dev, priv->base);
49c4c78e MS	231	}
	232
	233	static const struct udevice_id sata_ceva_ids[] = {
79ed61e9 YT	234	{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
79ed61e9 YT	235	{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
df983a76	236	{ .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
d2ebc382	237	{ .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
822d0608	238	{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
5fcae597	239	{ .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
aaaffe90	240	{ .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
1039d1ac	241	{ .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
49c4c78e MS	242	{ }
	243	};
	244
d1998a9f	245	static int sata_ceva_of_to_plat(struct udevice *dev)
49c4c78e	246	{
c3898a88	247	struct ceva_sata_priv *priv = dev_get_priv(dev);
d2ebc382 PM	248	struct resource res_regs;
d2ebc382 PM	249	int ret;
49c4c78e	250
79ed61e9 YT	251	if (dev_read_bool(dev, "dma-coherent"))
	252	priv->flag \|= FLAG_COHERENT;
	253
	254	priv->base = dev_read_addr(dev);
c3898a88	255	if (priv->base == FDT_ADDR_T_NONE)
49c4c78e MS	256	return -EINVAL;
49c4c78e MS	257
cde9b147	258	ret = dev_read_resource_byname(dev, "sata-ecc", &res_regs);
d2ebc382 PM	259	if (ret)
	260	priv->ecc_base = 0;
	261	else
	262	priv->ecc_base = res_regs.start;
	263
79ed61e9 YT	264	priv->soc = dev_get_driver_data(dev);
79ed61e9 YT	265
d2ebc382 PM	266	debug("ccsr-sata-base %lx\t ecc-base %lx\n",
	267	priv->base,
	268	priv->ecc_base);
	269
49c4c78e MS	270	return 0;
	271	}
	272
	273	U_BOOT_DRIVER(ceva_host_blk) = {
	274	.name = "ceva_sata",
c3898a88	275	.id = UCLASS_AHCI,
49c4c78e	276	.of_match = sata_ceva_ids,
c3898a88	277	.bind = sata_ceva_bind,
f6ab5a92	278	.ops = &scsi_ops,
41575d8e	279	.priv_auto = sizeof(struct ceva_sata_priv),
49c4c78e	280	.probe = sata_ceva_probe,
d1998a9f	281	.of_to_plat = sata_ceva_of_to_plat,
49c4c78e	282	};