]> Git Repo - J-u-boot.git/blame - include/configs/sandbox.h
Convert CONFIG_I2C_EDID et al to Kconfig
[J-u-boot.git] / include / configs / sandbox.h
CommitLineData
83d290c5 1/* SPDX-License-Identifier: GPL-2.0+ */
c861fbf7
SG
2/*
3 * Copyright (c) 2011 The Chromium OS Authors.
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SG
4 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
1c12bcee 9#ifndef CONFIG_SPL_BUILD
42d3b29d 10#define CONFIG_IO_TRACE
1c12bcee 11#endif
42d3b29d 12
9961a0b6 13#ifndef CONFIG_TIMER
28c860b2 14#define CONFIG_SYS_TIMER_RATE 1000000
9961a0b6 15#endif
28c860b2 16
f4d8de48 17#define CONFIG_HOST_MAX_DEVICES 4
10fc1218 18
b53e94b1 19#define CONFIG_MALLOC_F_ADDR 0x0010000
c861fbf7 20
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SG
21#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
22
c861fbf7 23/* turn on command-line edit/c/auto */
c861fbf7 24
5e74934d 25/* SPI - enable all SPI flash types for testing purposes */
ca9a5019 26
2c072c95
SG
27#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
28
29#define CONFIG_PHYSMEM
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SG
30
31/* Size of our emulated memory */
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HS
32#define SB_CONCAT(x, y) x ## y
33#define SB_TO_UL(s) SB_CONCAT(s, UL)
a733b06b 34#define CONFIG_SYS_SDRAM_BASE 0
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35#define CONFIG_SYS_SDRAM_SIZE \
36 (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
a733b06b 37#define CONFIG_SYS_MONITOR_BASE 0
c861fbf7 38
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SG
39#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
40 115200}
c861fbf7 41
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42#define BOOT_TARGET_DEVICES(func) \
43 func(HOST, host, 1) \
44 func(HOST, host, 0)
45
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46#ifdef __ASSEMBLY__
47#define BOOTENV
48#else
791a9f67 49#include <config_distro_bootcmd.h>
e676f439 50#endif
c861fbf7 51
1f5bc524
JH
52#define CONFIG_KEEP_SERVERADDR
53#define CONFIG_UDP_CHECKSUM
1f5bc524 54#define CONFIG_TIMESTAMP
f3e0c374 55#define CONFIG_BOOTP_SERVERIP
c861fbf7 56
ad0e4639 57#ifndef SANDBOX_NO_SDL
2c072c95 58#define CONFIG_SANDBOX_SDL
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SG
59#endif
60
61/* LCD and keyboard require SDL support */
62#ifdef CONFIG_SANDBOX_SDL
2c072c95 63#define LCD_BPP LCD_COLOR16
0156444c 64#define CONFIG_LCD_BMP_RLE8
2c072c95 65
ad0e4639
SG
66#define CONFIG_KEYBOARD
67
460a7172 68#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
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69 "stdout=serial,vidconsole\0" \
70 "stderr=serial,vidconsole\0"
ad0e4639 71#else
3ea143ab 72#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
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SG
73 "stdout=serial,vidconsole\0" \
74 "stderr=serial,vidconsole\0"
ad0e4639 75#endif
c861fbf7 76
3ea143ab 77#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
ff98da06 78 "eth2addr=00:00:11:22:33:48\0" \
be1a6e94 79 "eth3addr=00:00:11:22:33:45\0" \
ff98da06 80 "eth4addr=00:00:11:22:33:48\0" \
be1a6e94
MW
81 "eth5addr=00:00:11:22:33:46\0" \
82 "eth6addr=00:00:11:22:33:47\0" \
3ea143ab
JH
83 "ipaddr=1.2.3.4\0"
84
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85#define MEM_LAYOUT_ENV_SETTINGS \
86 "bootm_size=0x10000000\0" \
87 "kernel_addr_r=0x1000000\0" \
88 "fdt_addr_r=0xc00000\0" \
89 "ramdisk_addr_r=0x2000000\0" \
90 "scriptaddr=0x1000\0" \
91 "pxefile_addr_r=0x2000\0"
92
93#define CONFIG_EXTRA_ENV_SETTINGS \
94 SANDBOX_SERIAL_SETTINGS \
95 SANDBOX_ETH_SETTINGS \
96 BOOTENV \
97 MEM_LAYOUT_ENV_SETTINGS
3ea143ab 98
1c12bcee 99#ifndef CONFIG_SPL_BUILD
74c6dc14
SG
100#define CONFIG_SYS_IDE_MAXBUS 1
101#define CONFIG_SYS_ATA_IDE0_OFFSET 0
102#define CONFIG_SYS_IDE_MAXDEVICE 2
103#define CONFIG_SYS_ATA_BASE_ADDR 0x100
104#define CONFIG_SYS_ATA_DATA_OFFSET 0
105#define CONFIG_SYS_ATA_REG_OFFSET 1
106#define CONFIG_SYS_ATA_ALT_OFFSET 2
107#define CONFIG_SYS_ATA_STRIDE 4
1c12bcee 108#endif
74c6dc14 109
e8c0a250
SG
110#define CONFIG_SCSI_AHCI_PLAT
111#define CONFIG_SYS_SCSI_MAX_DEVICE 2
112#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
113#define CONFIG_SYS_SCSI_MAX_LUN 4
114
199a1201
SG
115#define CONFIG_SYS_SATA_MAX_DEVICE 2
116
c861fbf7 117#endif
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