[J-u-boot.git] / include / configs / MPC8315ERDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
 *
 * Dave Liu <[email protected]>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH		0x00000000
#define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */

#define CONFIG_HWCONFIG

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * Arbiter Setup
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of two chips HY5PS12621BFP-C4 from HYNIX
 */
#define CONFIG_SYS_DDR_SIZE		128 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (6 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_32)
				/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2	0x00000000

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00140000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00040000
#define CONFIG_FSL_ELBC		1

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT	135

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

/*
 * NAND Flash on the Local Bus
 */

#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE		0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE		0xE0600000
#endif

#define CONFIG_MTD_PARTITION

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_NAND_FSL_ELBC		1
#define CONFIG_SYS_NAND_BLOCK_SIZE	16384
#define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */

#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000

#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
					| BR_PS_16	/* 16 bit port */ \
					| BR_MS_GPCM	/* MSEL = GPCM */ \
					| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
					| OR_UPM_XAM \
					| OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV2 \
					| OR_GPCM_XACS \
					| OR_GPCM_SCY_15 \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EHTR_SET \
					| OR_GPCM_EAD)
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
				| BR_PS_8		/* 8 bit port */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V)			/* valid */
#define CONFIG_SYS_OR1_PRELIM \
				(OR_AM_32KB \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR)
				/* 0xFFFF8396 */

/* Still needed for spl_minimal.c */
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM

#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
	!defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Board info - revision and where boot from
 */
#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
#define CONFIG_SYS_PCI_IO_BASE		0x00000000
#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */

#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000

#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

#define CONFIG_SYS_PCIE2_BASE		0xC0000000
#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE

#define CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */

#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_SCCR_USBDRCM		3

#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_PHY_TYPE	"utmi"
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

/*
 * TSEC
 */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC1"

/*
 * SATA
 */
#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET	0x18000
#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET	0x19000
#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA

#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#endif

/*
 * Environment
 */
#if !defined(CONFIG_SYS_RAMBOOT)
	#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000
#else
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */
#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_128M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
				| BATU_BL_8M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_32M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U

/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U

#define CONFIG_SYS_IBAT6L	0
#define CONFIG_SYS_IBAT6U	0
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U

#define CONFIG_SYS_IBAT7L	0
#define CONFIG_SYS_IBAT7U	0
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=ramfs.83xx\0"					\
	"fdtaddr=780000\0"						\
	"fdtfile=mpc8315erdb.dtb\0"					\
	"usb_phy_type=utmi\0"						\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
8bd522ce	2	/*
e8d3ca8b	3	* Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
8bd522ce DL	4	*
8bd522ce DL	5	* Dave Liu <[email protected]>
8bd522ce DL	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
f1c574d4 SW	11	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	12	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	13	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	14	#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
	15	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
	16
f1c574d4 SW	17	#ifndef CONFIG_SYS_MONITOR_BASE
	18	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	19	#endif
	20
8bd522ce DL	21	/*
	22	* High Level Configuration Options
	23	*/
	24	#define CONFIG_E300 1 /* E300 family */
8bd522ce	25
8bd522ce DL	26	/*
	27	* System IO Config
	28	*/
6d0f6bcf JCPV	29	#define CONFIG_SYS_SICRH 0x00000000
6d0f6bcf JCPV	30	#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
8bd522ce	31
b8b71ffb	32	#define CONFIG_HWCONFIG
8bd522ce DL	33
	34	/*
	35	* IMMR new address
	36	*/
6d0f6bcf	37	#define CONFIG_SYS_IMMR 0xE0000000
8bd522ce DL	38
	39	/*
	40	* Arbiter Setup
	41	*/
6d0f6bcf	42	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
6f681b73 JH	43	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
6f681b73 JH	44	#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
8bd522ce DL	45
	46	/*
	47	* DDR Setup
	48	*/
6d0f6bcf JCPV	49	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
	50	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	51	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	52	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
6f681b73	53	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
8bd522ce DL	54	\| DDRCDR_PZ_LOZ \
	55	\| DDRCDR_NZ_LOZ \
	56	\| DDRCDR_ODT \
6f681b73	57	\| DDRCDR_Q_DRN)
8bd522ce DL	58	/* 0x7b880001 */
	59	/*
	60	* Manually set up DDR parameters
	61	* consist of two chips HY5PS12621BFP-C4 from HYNIX
	62	*/
6d0f6bcf JCPV	63	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
6d0f6bcf JCPV	64	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
6f681b73	65	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
2fef4020 JH	66	\| CSCONFIG_ODT_RD_NEVER \
2fef4020 JH	67	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
6f681b73 JH	68	\| CSCONFIG_ROW_BIT_13 \
6f681b73 JH	69	\| CSCONFIG_COL_BIT_10)
8bd522ce	70	/* 0x80010102 */
6d0f6bcf	71	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
6f681b73 JH	72	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	73	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	74	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	75	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	76	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	77	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	78	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	79	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
8bd522ce	80	/* 0x00220802 */
6f681b73 JH	81	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	82	\| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	83	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	84	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	85	\| (6 << TIMING_CFG1_REFREC_SHIFT) \
	86	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	87	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	88	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
2f2a5c37	89	/* 0x27256222 */
6f681b73 JH	90	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	91	\| (4 << TIMING_CFG2_CPO_SHIFT) \
	92	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	93	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	94	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	95	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	96	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
2f2a5c37	97	/* 0x121048c5 */
6f681b73 JH	98	#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
6f681b73 JH	99	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
8bd522ce	100	/* 0x03600100 */
6f681b73	101	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
8bd522ce	102	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
2fef4020	103	\| SDRAM_CFG_DBW_32)
8bd522ce	104	/* 0x43080000 */
6d0f6bcf	105	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
6f681b73 JH	106	#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
6f681b73 JH	107	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
8bd522ce	108	/* ODT 150ohm CL=3, AL=1 on SDRAM */
6f681b73	109	#define CONFIG_SYS_DDR_MODE2 0x00000000
8bd522ce DL	110
	111	/*
	112	* Memory test
	113	*/
6d0f6bcf JCPV	114	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	115	#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
	116	#define CONFIG_SYS_MEMTEST_END 0x00140000
8bd522ce DL	117
	118	/*
	119	* The reserved memory
	120	*/
16c8c170	121	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
6f681b73	122	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
8bd522ce DL	123
	124	/*
	125	* Initial RAM Base Address Setup
	126	*/
6d0f6bcf JCPV	127	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	128	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
553f0982	129	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
6f681b73 JH	130	#define CONFIG_SYS_GBL_DATA_OFFSET \
6f681b73 JH	131	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
8bd522ce DL	132
	133	/*
	134	* Local Bus Configuration & Clock Setup
	135	*/
c7190f02 KP	136	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	137	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
6d0f6bcf	138	#define CONFIG_SYS_LBC_LBCR 0x00040000
0914f483	139	#define CONFIG_FSL_ELBC 1
8bd522ce DL	140
	141	/*
	142	* FLASH on the Local Bus
	143	*/
6d0f6bcf	144	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
8bd522ce	145
6d0f6bcf	146	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
6f681b73	147	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
8bd522ce	148
6f681b73 JH	149	/* Window base at flash base */
6f681b73 JH	150	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	151	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_8MB)
8bd522ce	152
6d0f6bcf	153	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
6f681b73 JH	154	/* 127 64KB sectors and 8 8KB top sectors per device */
6f681b73 JH	155	#define CONFIG_SYS_MAX_FLASH_SECT 135
8bd522ce	156
6d0f6bcf JCPV	157	#undef CONFIG_SYS_FLASH_CHECKSUM
	158	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	159	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
8bd522ce DL	160
	161	/*
	162	* NAND Flash on the Local Bus
	163	*/
2e95004d AV	164
	165	#ifdef CONFIG_NAND_SPL
	166	#define CONFIG_SYS_NAND_BASE 0xFFF00000
	167	#else
	168	#define CONFIG_SYS_NAND_BASE 0xE0600000
	169	#endif
	170
e8d3ca8b	171	#define CONFIG_MTD_PARTITION
e8d3ca8b	172
6d0f6bcf	173	#define CONFIG_SYS_MAX_NAND_DEVICE 1
1ac5744e	174	#define CONFIG_NAND_FSL_ELBC 1
7d6a0982 JH	175	#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
7d6a0982 JH	176	#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
2e95004d AV	177
	178	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	179	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	180	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	181	#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
	182	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
8bd522ce	183
7577cb19 MS	184	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
	185	\| BR_PS_16 /* 16 bit port */ \
	186	\| BR_MS_GPCM /* MSEL = GPCM */ \
	187	\| BR_V) /* valid */
	188	#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
	189	\| OR_UPM_XAM \
	190	\| OR_GPCM_CSNT \
	191	\| OR_GPCM_ACS_DIV2 \
	192	\| OR_GPCM_XACS \
	193	\| OR_GPCM_SCY_15 \
	194	\| OR_GPCM_TRLX_SET \
	195	\| OR_GPCM_EHTR_SET \
	196	\| OR_GPCM_EAD)
	197	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
7d6a0982	198	\| BR_DECC_CHK_GEN /* Use HW ECC */ \
6f681b73	199	\| BR_PS_8 /* 8 bit port */ \
8bd522ce	200	\| BR_MS_FCM /* MSEL = FCM */ \
6f681b73	201	\| BR_V) /* valid */
7577cb19 MS	202	#define CONFIG_SYS_OR1_PRELIM \
7577cb19 MS	203	(OR_AM_32KB \
8bd522ce DL	204	\| OR_FCM_CSCT \
	205	\| OR_FCM_CST \
	206	\| OR_FCM_CHT \
	207	\| OR_FCM_SCY_1 \
	208	\| OR_FCM_TRLX \
6f681b73	209	\| OR_FCM_EHTR)
8bd522ce DL	210	/* 0xFFFF8396 */
8bd522ce DL	211
7577cb19 MS	212	/* Still needed for spl_minimal.c */
	213	#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
	214	#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
2e95004d	215
6d0f6bcf	216	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
7d6a0982	217	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
8bd522ce	218
2e95004d AV	219	#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
	220	#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
	221
	222	#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
	223	!defined(CONFIG_NAND_SPL)
	224	#define CONFIG_SYS_RAMBOOT
	225	#else
	226	#undef CONFIG_SYS_RAMBOOT
	227	#endif
	228
8bd522ce DL	229	/*
	230	* Serial Port
	231	*/
6d0f6bcf JCPV	232	#define CONFIG_SYS_NS16550_SERIAL
6d0f6bcf JCPV	233	#define CONFIG_SYS_NS16550_REG_SIZE 1
0f06f57c	234	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
8bd522ce	235
6d0f6bcf	236	#define CONFIG_SYS_BAUDRATE_TABLE \
6f681b73	237	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
8bd522ce	238
6d0f6bcf JCPV	239	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	240	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
8bd522ce	241
8bd522ce	242	/* I2C */
00f792e0 HS	243	#define CONFIG_SYS_I2C
	244	#define CONFIG_SYS_I2C_FSL
	245	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	246	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	247	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	248	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
8bd522ce DL	249
	250	/*
	251	* Board info - revision and where boot from
	252	*/
6d0f6bcf	253	#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
8bd522ce DL	254
	255	/*
	256	* Config on-board RTC
	257	*/
	258	#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
6d0f6bcf	259	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
8bd522ce DL	260
	261	/*
	262	* General PCI
	263	* Addresses are mapped 1-1.
	264	*/
6f681b73 JH	265	#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
	266	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
	267	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
6d0f6bcf JCPV	268	#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
	269	#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
	270	#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
	271	#define CONFIG_SYS_PCI_IO_BASE 0x00000000
	272	#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
	273	#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
	274
	275	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
	276	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
	277	#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
8bd522ce	278
8f11e34b AV	279	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	280	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
	281	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
	282	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	283	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
	284	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
	285	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	286	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
	287	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	288
	289	#define CONFIG_SYS_PCIE2_BASE 0xC0000000
	290	#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
	291	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
	292	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
	293	#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
	294	#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
	295	#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
	296	#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
	297	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
	298
842033e6	299	#define CONFIG_PCI_INDIRECT_BRIDGE
be9b56df	300	#define CONFIG_PCIE
8bd522ce	301
8bd522ce DL	302	#define CONFIG_EEPRO100
8bd522ce DL	303	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	304	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
8bd522ce	305
25f5f0d4	306	#define CONFIG_HAS_FSL_DR_USB
6823e9b0 VM	307	#define CONFIG_SYS_SCCR_USBDRCM 3
6823e9b0 VM	308
6823e9b0	309	#define CONFIG_USB_EHCI_FSL
6f681b73	310	#define CONFIG_USB_PHY_TYPE "utmi"
6823e9b0	311	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
25f5f0d4	312
8bd522ce DL	313	/*
	314	* TSEC
	315	*/
6d0f6bcf	316	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
6f681b73	317	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
6d0f6bcf	318	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
6f681b73	319	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
8bd522ce DL	320
	321	/*
	322	* TSEC ethernet configuration
	323	*/
8bd522ce DL	324	#define CONFIG_TSEC1 1
	325	#define CONFIG_TSEC1_NAME "eTSEC0"
	326	#define CONFIG_TSEC2 1
	327	#define CONFIG_TSEC2_NAME "eTSEC1"
	328	#define TSEC1_PHY_ADDR 0
	329	#define TSEC2_PHY_ADDR 1
	330	#define TSEC1_PHYIDX 0
	331	#define TSEC2_PHYIDX 0
	332	#define TSEC1_FLAGS TSEC_GIGABIT
	333	#define TSEC2_FLAGS TSEC_GIGABIT
	334
	335	/* Options are: eTSEC[0-1] */
	336	#define CONFIG_ETHPRIME "eTSEC1"
	337
730e7929 KP	338	/*
	339	* SATA
	340	*/
6d0f6bcf	341	#define CONFIG_SYS_SATA_MAX_DEVICE 2
730e7929	342	#define CONFIG_SATA1
6d0f6bcf	343	#define CONFIG_SYS_SATA1_OFFSET 0x18000
6f681b73 JH	344	#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
6f681b73 JH	345	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
730e7929	346	#define CONFIG_SATA2
6d0f6bcf	347	#define CONFIG_SYS_SATA2_OFFSET 0x19000
6f681b73 JH	348	#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
6f681b73 JH	349	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
730e7929 KP	350
	351	#ifdef CONFIG_FSL_SATA
	352	#define CONFIG_LBA48
730e7929 KP	353	#endif
730e7929 KP	354
8bd522ce DL	355	/*
	356	* Environment
	357	*/
d0fb0fce	358	#if !defined(CONFIG_SYS_RAMBOOT)
6f681b73 JH	359	#define CONFIG_ENV_ADDR \
6f681b73 JH	360	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586 JCPV	361	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
0e8d1586 JCPV	362	#define CONFIG_ENV_SIZE 0x2000
8bd522ce	363	#else
6d0f6bcf	364	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	365	#define CONFIG_ENV_SIZE 0x2000
8bd522ce DL	366	#endif
	367
	368	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	369	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
8bd522ce DL	370
	371	/*
	372	* BOOTP options
	373	*/
	374	#define CONFIG_BOOTP_BOOTFILESIZE
8bd522ce DL	375
	376	/*
	377	* Command line configuration.
	378	*/
8bd522ce	379
8bd522ce DL	380	#undef CONFIG_WATCHDOG /* watchdog disabled */
	381
	382	/*
	383	* Miscellaneous configurable options
	384	*/
6d0f6bcf	385	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
8bd522ce	386
8bd522ce DL	387	/*
8bd522ce DL	388	* For booting Linux, the board info and command line data
9f530d59	389	* have to be in the first 256 MB of memory, since this is
8bd522ce DL	390	* the maximum mapped by the Linux kernel during initialization.
8bd522ce DL	391	*/
6f681b73	392	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
63865278	393	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
8bd522ce DL	394
	395	/*
	396	* Core HID Setup
	397	*/
1a2e203b KP	398	#define CONFIG_SYS_HID0_INIT 0x000000000
	399	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	400	HID0_ENABLE_INSTRUCTION_CACHE \| \
8bd522ce	401	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
6d0f6bcf	402	#define CONFIG_SYS_HID2 HID2_HBE
8bd522ce DL	403
	404	/*
	405	* MMU Setup
	406	*/
31d82672	407	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
8bd522ce DL	408
8bd522ce DL	409	/* DDR: cache cacheable */
6f681b73	410	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	411	\| BATL_PP_RW \
6f681b73 JH	412	\| BATL_MEMCOHERENCE)
	413	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	414	\| BATU_BL_128M \
	415	\| BATU_VS \
	416	\| BATU_VP)
6d0f6bcf JCPV	417	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
6d0f6bcf JCPV	418	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
8bd522ce DL	419
8bd522ce DL	420	/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
6f681b73	421	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
72cd4087	422	\| BATL_PP_RW \
6f681b73 JH	423	\| BATL_CACHEINHIBIT \
	424	\| BATL_GUARDEDSTORAGE)
	425	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
	426	\| BATU_BL_8M \
	427	\| BATU_VS \
	428	\| BATU_VP)
6d0f6bcf JCPV	429	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
6d0f6bcf JCPV	430	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
8bd522ce DL	431
8bd522ce DL	432	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
6f681b73	433	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
72cd4087	434	\| BATL_PP_RW \
6f681b73 JH	435	\| BATL_MEMCOHERENCE)
	436	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
	437	\| BATU_BL_32M \
	438	\| BATU_VS \
	439	\| BATU_VP)
	440	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
72cd4087	441	\| BATL_PP_RW \
6f681b73 JH	442	\| BATL_CACHEINHIBIT \
6f681b73 JH	443	\| BATL_GUARDEDSTORAGE)
6d0f6bcf	444	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
8bd522ce DL	445
8bd522ce DL	446	/* Stack in dcache: cacheable, no memory coherence */
72cd4087	447	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
6f681b73 JH	448	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
	449	\| BATU_BL_128K \
	450	\| BATU_VS \
	451	\| BATU_VP)
6d0f6bcf JCPV	452	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
6d0f6bcf JCPV	453	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
8bd522ce DL	454
8bd522ce DL	455	/* PCI MEM space: cacheable */
6f681b73	456	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
72cd4087	457	\| BATL_PP_RW \
6f681b73 JH	458	\| BATL_MEMCOHERENCE)
	459	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
	460	\| BATU_BL_256M \
	461	\| BATU_VS \
	462	\| BATU_VP)
6d0f6bcf JCPV	463	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
6d0f6bcf JCPV	464	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
8bd522ce DL	465
8bd522ce DL	466	/* PCI MMIO space: cache-inhibit and guarded */
6f681b73	467	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
72cd4087	468	\| BATL_PP_RW \
6f681b73 JH	469	\| BATL_CACHEINHIBIT \
	470	\| BATL_GUARDEDSTORAGE)
	471	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
	472	\| BATU_BL_256M \
	473	\| BATU_VS \
	474	\| BATU_VP)
6d0f6bcf JCPV	475	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	476	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	477
	478	#define CONFIG_SYS_IBAT6L 0
	479	#define CONFIG_SYS_IBAT6U 0
	480	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	481	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	482
	483	#define CONFIG_SYS_IBAT7L 0
	484	#define CONFIG_SYS_IBAT7U 0
	485	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	486	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
8bd522ce	487
8bd522ce DL	488	#if defined(CONFIG_CMD_KGDB)
8bd522ce DL	489	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
8bd522ce DL	490	#endif
	491
	492	/*
	493	* Environment Configuration
	494	*/
	495
	496	#define CONFIG_ENV_OVERWRITE
	497
	498	#if defined(CONFIG_TSEC_ENET)
	499	#define CONFIG_HAS_ETH0
8bd522ce	500	#define CONFIG_HAS_ETH1
8bd522ce DL	501	#endif
8bd522ce DL	502
79f516bc	503	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
8bd522ce	504
8bd522ce	505	#define CONFIG_EXTRA_ENV_SETTINGS \
6f681b73 JH	506	"netdev=eth0\0" \
	507	"consoledev=ttyS0\0" \
	508	"ramdiskaddr=1000000\0" \
	509	"ramdiskfile=ramfs.83xx\0" \
	510	"fdtaddr=780000\0" \
	511	"fdtfile=mpc8315erdb.dtb\0" \
	512	"usb_phy_type=utmi\0" \
	513	""
8bd522ce DL	514
8bd522ce DL	515	#define CONFIG_NFSBOOTCOMMAND \
6f681b73 JH	516	"setenv bootargs root=/dev/nfs rw " \
	517	"nfsroot=$serverip:$rootpath " \
	518	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	519	"$netdev:off " \
	520	"console=$consoledev,$baudrate $othbootargs;" \
	521	"tftp $loadaddr $bootfile;" \
	522	"tftp $fdtaddr $fdtfile;" \
	523	"bootm $loadaddr - $fdtaddr"
8bd522ce DL	524
8bd522ce DL	525	#define CONFIG_RAMBOOTCOMMAND \
6f681b73 JH	526	"setenv bootargs root=/dev/ram rw " \
	527	"console=$consoledev,$baudrate $othbootargs;" \
	528	"tftp $ramdiskaddr $ramdiskfile;" \
	529	"tftp $loadaddr $bootfile;" \
	530	"tftp $fdtaddr $fdtfile;" \
	531	"bootm $loadaddr $ramdiskaddr $fdtaddr"
8bd522ce	532
8bd522ce DL	533	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	534
	535	#endif /* __CONFIG_H */