projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 3335786a SR |
2 | /* |
| 3 | * Copyright (C) 2015-2016 Marvell International Ltd. | |
| 3335786a SR |
4 | */ |
| 5 | ||
| 6 | #include <common.h> | |
| 7 | #include <fdtdec.h> | |
| 8 | #include <asm/io.h> | |
| 9 | #include <asm/arch/cpu.h> | |
| 10 | #include <asm/arch/soc.h> | |
| 11 | ||
| 12 | #include "comphy_a3700.h" | |
| 13 | ||
| 14 | DECLARE_GLOBAL_DATA_PTR; | |
| 15 | ||
| 16 | struct sgmii_phy_init_data_fix { | |
| 17 | u16 addr; | |
| 18 | u16 value; | |
| 19 | }; | |
| 20 | ||
| 21 | /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ | |
| 22 | static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = { | |
| 23 | {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000}, | |
| 24 | {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030}, | |
| 25 | {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC}, | |
| 26 | {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA}, | |
| 27 | {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550}, | |
| 28 | {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0}, | |
| 29 | {0x104, 0x0C10} | |
| 30 | }; | |
| 31 | ||
| 32 | /* 40M1G25 mode init data */ | |
| 33 | static u16 sgmii_phy_init[512] = { | |
| 34 | /* 0 1 2 3 4 5 6 7 */ | |
| 35 | /*-----------------------------------------------------------*/ | |
| 36 | /* 8 9 A B C D E F */ | |
| 37 | 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ | |
| 38 | 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ | |
| 39 | 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ | |
| 40 | 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ | |
| 41 | 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ | |
| 42 | 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ | |
| 43 | 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ | |
| 44 | 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ | |
| 45 | 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ | |
| 46 | 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ | |
| 47 | 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ | |
| 48 | 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ | |
| 49 | 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ | |
| 50 | 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ | |
| 51 | 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ | |
| 52 | 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ | |
| 53 | 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ | |
| 54 | 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ | |
| 55 | 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ | |
| 56 | 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ | |
| 57 | 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ | |
| 58 | 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ | |
| 59 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ | |
| 60 | 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ | |
| 61 | 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ | |
| 62 | 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ | |
| 63 | 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ | |
| 64 | 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ | |
| 65 | 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ | |
| 66 | 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ | |
| 67 | 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ | |
| 68 | 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ | |
| 69 | 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ | |
| 70 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ | |
| 71 | 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ | |
| 72 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ | |
| 73 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ | |
| 74 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ | |
| 75 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ | |
| 76 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ | |
| 77 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ | |
| 78 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ | |
| 79 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ | |
| 80 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ | |
| 81 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ | |
| 82 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ | |
| 83 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ | |
| 84 | 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ | |
| 85 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ | |
| 86 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ | |
| 87 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ | |
| 88 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ | |
| 89 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ | |
| 90 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ | |
| 91 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ | |
| 92 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ | |
| 93 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ | |
| 94 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ | |
| 95 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ | |
| 96 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ | |
| 97 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ | |
| 98 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ | |
| 99 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ | |
| 100 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ | |
| 101 | }; | |
| 102 | ||
| 103 | /* | |
| 104 | * comphy_poll_reg | |
| 105 | * | |
| 106 | * return: 1 on success, 0 on timeout | |
| 107 | */ | |
| 108 | static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u32 timeout, | |
| 109 | u8 op_type) | |
| 110 | { | |
| 111 | u32 rval = 0xDEAD; | |
| 112 | ||
| 113 | for (; timeout > 0; timeout--) { | |
| 114 | if (op_type == POLL_16B_REG) | |
| 115 | rval = readw(addr); /* 16 bit */ | |
| 116 | else | |
| 117 | rval = readl(addr) ; /* 32 bit */ | |
| 118 | ||
| 119 | if ((rval & mask) == val) | |
| 120 | return 1; | |
| 121 | ||
| 122 | udelay(10000); | |
| 123 | } | |
| 124 | ||
| 125 | debug("Time out waiting (%p = %#010x)\n", addr, rval); | |
| 126 | return 0; | |
| 127 | } | |
| 128 | ||
| 129 | /* | |
| 130 | * comphy_pcie_power_up | |
| 131 | * | |
| 132 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) | |
| 133 | */ | |
| 134 | static int comphy_pcie_power_up(u32 speed, u32 invert) | |
| 135 | { | |
| 136 | int ret; | |
| 137 | ||
| 138 | debug_enter(); | |
| 139 | ||
| 140 | /* | |
| 141 | * 1. Enable max PLL. | |
| 142 | */ | |
| 210f4aae | 143 | reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); |
| 3335786a SR |
144 | |
| 145 | /* | |
| 146 | * 2. Select 20 bit SERDES interface. | |
| 147 | */ | |
| 210f4aae | 148 | reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); |
| 3335786a SR |
149 | |
| 150 | /* | |
| 151 | * 3. Force to use reg setting for PCIe mode | |
| 152 | */ | |
| 210f4aae | 153 | reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); |
| 3335786a SR |
154 | |
| 155 | /* | |
| 156 | * 4. Change RX wait | |
| 157 | */ | |
| 210f4aae | 158 | reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); |
| 3335786a SR |
159 | |
| 160 | /* | |
| 161 | * 5. Enable idle sync | |
| 162 | */ | |
| 210f4aae | 163 | reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); |
| 3335786a SR |
164 | |
| 165 | /* | |
| 166 | * 6. Enable the output of 100M/125M/500M clock | |
| 167 | */ | |
| 210f4aae | 168 | reg_set16(phy_addr(PCIE, MISC_REG0), |
| 3335786a SR |
169 | 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); |
| 170 | ||
| 171 | /* | |
| 172 | * 7. Enable TX | |
| 173 | */ | |
| 210f4aae | 174 | reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); |
| 3335786a SR |
175 | |
| 176 | /* | |
| 177 | * 8. Check crystal jumper setting and program the Power and PLL | |
| 178 | * Control accordingly | |
| 179 | */ | |
| 180 | if (get_ref_clk() == 40) { | |
| 210f4aae MB |
181 | /* 40 MHz */ |
| 182 | reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); | |
| 3335786a | 183 | } else { |
| 210f4aae MB |
184 | /* 25 MHz */ |
| 185 | reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); | |
| 3335786a SR |
186 | } |
| 187 | ||
| 188 | /* | |
| 189 | * 9. Override Speed_PLL value and use MAC PLL | |
| 190 | */ | |
| 210f4aae | 191 | reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, |
| fae82c8f | 192 | 0xFFFF); |
| 3335786a SR |
193 | |
| 194 | /* | |
| 195 | * 10. Check the Polarity invert bit | |
| 196 | */ | |
| 210f4aae MB |
197 | if (invert & PHY_POLARITY_TXD_INVERT) |
| 198 | reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); | |
| 3335786a | 199 | |
| 210f4aae MB |
200 | if (invert & PHY_POLARITY_RXD_INVERT) |
| 201 | reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); | |
| 3335786a SR |
202 | |
| 203 | /* | |
| 204 | * 11. Release SW reset | |
| 205 | */ | |
| 210f4aae | 206 | reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0), |
| 3335786a SR |
207 | rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32, |
| 208 | bf_soft_rst | bf_mode_refdiv); | |
| 209 | ||
| 210 | /* Wait for > 55 us to allow PCLK be enabled */ | |
| 211 | udelay(PLL_SET_DELAY_US); | |
| 212 | ||
| 213 | /* Assert PCLK enabled */ | |
| 210f4aae MB |
214 | ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */ |
| 215 | rb_txdclk_pclk_en, /* value */ | |
| 216 | rb_txdclk_pclk_en, /* mask */ | |
| 217 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 218 | POLL_16B_REG); /* 16bit */ | |
| 3335786a SR |
219 | if (ret == 0) |
| 220 | printf("Failed to lock PCIe PLL\n"); | |
| 221 | ||
| 222 | debug_exit(); | |
| 223 | ||
| 224 | /* Return the status of the PLL */ | |
| 225 | return ret; | |
| 226 | } | |
| 227 | ||
| 228 | /* | |
| 229 | * comphy_sata_power_up | |
| 230 | * | |
| 231 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) | |
| 232 | */ | |
| 233 | static int comphy_sata_power_up(void) | |
| 234 | { | |
| 235 | int ret; | |
| 236 | ||
| 237 | debug_enter(); | |
| 238 | ||
| 239 | /* | |
| 240 | * 0. Swap SATA TX lines | |
| 241 | */ | |
| fae82c8f MB |
242 | reg_set(rh_vsreg_addr, vphy_sync_pattern_reg, 0xFFFFFFFF); |
| 243 | reg_set(rh_vsreg_data, bs_txd_inv, bs_txd_inv); | |
| 3335786a SR |
244 | |
| 245 | /* | |
| 246 | * 1. Select 40-bit data width width | |
| 247 | */ | |
| fae82c8f MB |
248 | reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); |
| 249 | reg_set(rh_vsreg_data, 0x800, bs_phyintf_40bit); | |
| 3335786a SR |
250 | |
| 251 | /* | |
| 252 | * 2. Select reference clock and PHY mode (SATA) | |
| 253 | */ | |
| fae82c8f | 254 | reg_set(rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF); |
| 3335786a | 255 | if (get_ref_clk() == 40) { |
| fae82c8f | 256 | reg_set(rh_vsreg_data, 0x3, 0x00FF); /* 40 MHz */ |
| 3335786a | 257 | } else { |
| fae82c8f | 258 | reg_set(rh_vsreg_data, 0x1, 0x00FF); /* 25 MHz */ |
| 3335786a SR |
259 | } |
| 260 | ||
| 261 | /* | |
| 262 | * 3. Use maximum PLL rate (no power save) | |
| 263 | */ | |
| fae82c8f MB |
264 | reg_set(rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF); |
| 265 | reg_set(rh_vsreg_data, bs_max_pll_rate, bs_max_pll_rate); | |
| 3335786a SR |
266 | |
| 267 | /* | |
| 268 | * 4. Reset reserved bit (??) | |
| 269 | */ | |
| fae82c8f MB |
270 | reg_set(rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF); |
| 271 | reg_set(rh_vsreg_data, 0, bs_phyctrl_frm_pin); | |
| 3335786a SR |
272 | |
| 273 | /* | |
| 274 | * 5. Set vendor-specific configuration (??) | |
| 275 | */ | |
| fae82c8f MB |
276 | reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); |
| 277 | reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); | |
| 3335786a SR |
278 | |
| 279 | /* Wait for > 55 us to allow PLL be enabled */ | |
| 280 | udelay(PLL_SET_DELAY_US); | |
| 281 | ||
| 282 | /* Assert SATA PLL enabled */ | |
| fae82c8f MB |
283 | reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); |
| 284 | ret = comphy_poll_reg(rh_vsreg_data, /* address */ | |
| 285 | bs_pll_ready_tx, /* value */ | |
| 286 | bs_pll_ready_tx, /* mask */ | |
| 287 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 288 | POLL_32B_REG); /* 32bit */ | |
| 3335786a SR |
289 | if (ret == 0) |
| 290 | printf("Failed to lock SATA PLL\n"); | |
| 291 | ||
| 292 | debug_exit(); | |
| 293 | ||
| 294 | return ret; | |
| 295 | } | |
| 296 | ||
| 297 | /* | |
| 298 | * comphy_usb3_power_up | |
| 299 | * | |
| 300 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) | |
| 301 | */ | |
| 302 | static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) | |
| 303 | { | |
| 304 | int ret; | |
| 305 | ||
| 306 | debug_enter(); | |
| 307 | ||
| 308 | /* | |
| 309 | * 1. Power up OTG module | |
| 310 | */ | |
| fae82c8f | 311 | reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); |
| 3335786a SR |
312 | |
| 313 | /* | |
| 314 | * 2. Set counter for 100us pulse in USB3 Host and Device | |
| 315 | * restore default burst size limit (Reference Clock 31:24) | |
| 316 | */ | |
| fae82c8f | 317 | reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns); |
| 3335786a SR |
318 | |
| 319 | ||
| 320 | /* 0xd005c300 = 0x1001 */ | |
| 321 | /* set PRD_TXDEEMPH (3.5db de-emph) */ | |
| 210f4aae | 322 | reg_set16(phy_addr(USB3, LANE_CFG0), 0x1, 0xFF); |
| 3335786a SR |
323 | |
| 324 | /* | |
| 325 | * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in | |
| 326 | * low impedance mode during electrical idle | |
| 327 | */ | |
| 328 | /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */ | |
| 329 | /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */ | |
| 210f4aae | 330 | reg_set16(phy_addr(USB3, LANE_CFG1), 0x0, 0xFFFF); |
| 3335786a SR |
331 | |
| 332 | ||
| 333 | /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ | |
| 210f4aae | 334 | reg_set16(phy_addr(USB3, LANE_CFG4), bf_spread_spectrum_clock_en, 0x80); |
| 3335786a SR |
335 | |
| 336 | /* | |
| 337 | * set Override Margining Controls From the MAC: Use margining signals | |
| 338 | * from lane configuration | |
| 339 | */ | |
| 210f4aae MB |
340 | reg_set16(phy_addr(USB3, TEST_MODE_CTRL), rb_mode_margin_override, |
| 341 | 0xFFFF); | |
| 3335786a SR |
342 | |
| 343 | /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ | |
| 344 | /* set Mode Clock Source = PCLK is generated from REFCLK */ | |
| 210f4aae | 345 | reg_set16(phy_addr(USB3, GLOB_CLK_SRC_LO), 0x0, 0xFF); |
| 3335786a SR |
346 | |
| 347 | /* set G2 Spread Spectrum Clock Amplitude at 4K */ | |
| 210f4aae | 348 | reg_set16(phy_addr(USB3, GEN2_SETTINGS_2), g2_tx_ssc_amp, 0xF000); |
| 3335786a SR |
349 | |
| 350 | /* | |
| 351 | * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register | |
| 352 | * Master Current Select | |
| 353 | */ | |
| 210f4aae | 354 | reg_set16(phy_addr(USB3, GEN2_SETTINGS_3), 0x0, 0xFFFF); |
| 3335786a SR |
355 | |
| 356 | /* | |
| 357 | * 3. Check crystal jumper setting and program the Power and PLL | |
| 358 | * Control accordingly | |
| 359 | */ | |
| 360 | if (get_ref_clk() == 40) { | |
| 210f4aae MB |
361 | /* 40 MHz */ |
| 362 | reg_set16(phy_addr(USB3, PWR_PLL_CTRL), 0xFCA3, 0xFFFF); | |
| 3335786a | 363 | } else { |
| 210f4aae MB |
364 | /* 25 MHz */ |
| 365 | reg_set16(phy_addr(USB3, PWR_PLL_CTRL), 0xFCA2, 0xFFFF); | |
| 3335786a SR |
366 | } |
| 367 | ||
| 368 | /* | |
| 369 | * 4. Change RX wait | |
| 370 | */ | |
| 210f4aae | 371 | reg_set16(phy_addr(USB3, PWR_MGM_TIM1), 0x10C, 0xFFFF); |
| 3335786a SR |
372 | |
| 373 | /* | |
| 374 | * 5. Enable idle sync | |
| 375 | */ | |
| 210f4aae | 376 | reg_set16(phy_addr(USB3, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); |
| 3335786a SR |
377 | |
| 378 | /* | |
| 379 | * 6. Enable the output of 500M clock | |
| 380 | */ | |
| 210f4aae | 381 | reg_set16(phy_addr(USB3, MISC_REG0), 0xA00D | rb_clk500m_en, 0xFFFF); |
| 3335786a SR |
382 | |
| 383 | /* | |
| 384 | * 7. Set 20-bit data width | |
| 385 | */ | |
| 210f4aae | 386 | reg_set16(phy_addr(USB3, DIG_LB_EN), 0x0400, 0xFFFF); |
| 3335786a SR |
387 | |
| 388 | /* | |
| 389 | * 8. Override Speed_PLL value and use MAC PLL | |
| 390 | */ | |
| 210f4aae | 391 | reg_set16(phy_addr(USB3, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, |
| fae82c8f | 392 | 0xFFFF); |
| 3335786a SR |
393 | |
| 394 | /* | |
| 395 | * 9. Check the Polarity invert bit | |
| 396 | */ | |
| 210f4aae MB |
397 | if (invert & PHY_POLARITY_TXD_INVERT) |
| 398 | reg_set16(phy_addr(USB3, SYNC_PATTERN), phy_txd_inv, 0); | |
| 3335786a | 399 | |
| 210f4aae MB |
400 | if (invert & PHY_POLARITY_RXD_INVERT) |
| 401 | reg_set16(phy_addr(USB3, SYNC_PATTERN), phy_rxd_inv, 0); | |
| 3335786a SR |
402 | |
| 403 | /* | |
| 404 | * 10. Release SW reset | |
| 405 | */ | |
| 210f4aae | 406 | reg_set16(phy_addr(USB3, GLOB_PHY_CTRL0), |
| 3335786a SR |
407 | rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20, |
| 408 | 0xFFFF); | |
| 409 | ||
| 410 | /* Wait for > 55 us to allow PCLK be enabled */ | |
| 411 | udelay(PLL_SET_DELAY_US); | |
| 412 | ||
| 413 | /* Assert PCLK enabled */ | |
| 210f4aae | 414 | ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */ |
| fae82c8f MB |
415 | rb_txdclk_pclk_en, /* value */ |
| 416 | rb_txdclk_pclk_en, /* mask */ | |
| 417 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 418 | POLL_16B_REG); /* 16bit */ | |
| 3335786a SR |
419 | if (ret == 0) |
| 420 | printf("Failed to lock USB3 PLL\n"); | |
| 421 | ||
| 422 | /* | |
| 423 | * Set Soft ID for Host mode (Device mode works with Hard ID | |
| 424 | * detection) | |
| 425 | */ | |
| 426 | if (type == PHY_TYPE_USB3_HOST0) { | |
| 427 | /* | |
| 428 | * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) | |
| 429 | * clear BIT1: set SOFT_ID = Host | |
| 430 | * set BIT4: set INT_MODE = ID. Interrupt Mode: enable | |
| 431 | * interrupt by ID instead of using both interrupts | |
| 432 | * of HOST and Device ORed simultaneously | |
| 433 | * INT_MODE=ID in order to avoid unexpected | |
| 434 | * behaviour or both interrupts together | |
| 435 | */ | |
| fae82c8f | 436 | reg_set(USB32_CTRL_BASE, |
| 3335786a SR |
437 | usb32_ctrl_id_mode | usb32_ctrl_int_mode, |
| 438 | usb32_ctrl_id_mode | usb32_ctrl_soft_id | | |
| 439 | usb32_ctrl_int_mode); | |
| 440 | } | |
| 441 | ||
| 442 | debug_exit(); | |
| 443 | ||
| 444 | return ret; | |
| 445 | } | |
| 446 | ||
| 447 | /* | |
| 448 | * comphy_usb2_power_up | |
| 449 | * | |
| 450 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) | |
| 451 | */ | |
| 452 | static int comphy_usb2_power_up(u8 usb32) | |
| 453 | { | |
| 454 | int ret; | |
| 455 | ||
| 456 | debug_enter(); | |
| 457 | ||
| 458 | if (usb32 != 0 && usb32 != 1) { | |
| 459 | printf("invalid usb32 value: (%d), should be either 0 or 1\n", | |
| 460 | usb32); | |
| 461 | debug_exit(); | |
| 462 | return 0; | |
| 463 | } | |
| 464 | ||
| 465 | /* | |
| 466 | * 0. Setup PLL. 40MHz clock uses defaults. | |
| 467 | * See "PLL Settings for Typical REFCLK" table | |
| 468 | */ | |
| 469 | if (get_ref_clk() == 25) { | |
| fae82c8f MB |
470 | reg_set(USB2_PHY_BASE(usb32), 5 | (96 << 16), |
| 471 | 0x3F | (0xFF << 16) | (0x3 << 28)); | |
| 3335786a SR |
472 | } |
| 473 | ||
| 474 | /* | |
| 475 | * 1. PHY pull up and disable USB2 suspend | |
| 476 | */ | |
| fae82c8f | 477 | reg_set(USB2_PHY_CTRL_ADDR(usb32), |
| 3335786a SR |
478 | RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0); |
| 479 | ||
| 480 | if (usb32 != 0) { | |
| 481 | /* | |
| 482 | * 2. Power up OTG module | |
| 483 | */ | |
| fae82c8f | 484 | reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); |
| 3335786a SR |
485 | |
| 486 | /* | |
| 487 | * 3. Configure PHY charger detection | |
| 488 | */ | |
| fae82c8f | 489 | reg_set(USB2_PHY_CHRGR_DET_ADDR, 0, |
| 3335786a SR |
490 | rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto | |
| 491 | rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc); | |
| 492 | } | |
| 493 | ||
| 494 | /* Assert PLL calibration done */ | |
| fae82c8f | 495 | ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), |
| 3335786a SR |
496 | rb_usb2phy_pllcal_done, /* value */ |
| 497 | rb_usb2phy_pllcal_done, /* mask */ | |
| 498 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 499 | POLL_32B_REG); /* 32bit */ | |
| 500 | if (ret == 0) | |
| 501 | printf("Failed to end USB2 PLL calibration\n"); | |
| 502 | ||
| 503 | /* Assert impedance calibration done */ | |
| fae82c8f | 504 | ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), |
| 3335786a SR |
505 | rb_usb2phy_impcal_done, /* value */ |
| 506 | rb_usb2phy_impcal_done, /* mask */ | |
| 507 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 508 | POLL_32B_REG); /* 32bit */ | |
| 509 | if (ret == 0) | |
| 510 | printf("Failed to end USB2 impedance calibration\n"); | |
| 511 | ||
| 512 | /* Assert squetch calibration done */ | |
| fae82c8f | 513 | ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), |
| 3335786a SR |
514 | rb_usb2phy_sqcal_done, /* value */ |
| 515 | rb_usb2phy_sqcal_done, /* mask */ | |
| 516 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 517 | POLL_32B_REG); /* 32bit */ | |
| 518 | if (ret == 0) | |
| 519 | printf("Failed to end USB2 unknown calibration\n"); | |
| 520 | ||
| 521 | /* Assert PLL is ready */ | |
| fae82c8f | 522 | ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32), |
| 3335786a SR |
523 | rb_usb2phy_pll_ready, /* value */ |
| 524 | rb_usb2phy_pll_ready, /* mask */ | |
| 525 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 526 | POLL_32B_REG); /* 32bit */ | |
| 527 | ||
| 528 | if (ret == 0) | |
| 529 | printf("Failed to lock USB2 PLL\n"); | |
| 530 | ||
| 531 | debug_exit(); | |
| 532 | ||
| 533 | return ret; | |
| 534 | } | |
| 535 | ||
| 536 | /* | |
| 537 | * comphy_emmc_power_up | |
| 538 | * | |
| 539 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) | |
| 540 | */ | |
| 541 | static int comphy_emmc_power_up(void) | |
| 542 | { | |
| 543 | debug_enter(); | |
| 544 | ||
| 545 | /* | |
| 546 | * 1. Bus power ON, Bus voltage 1.8V | |
| 547 | */ | |
| fae82c8f | 548 | reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00); |
| 3335786a SR |
549 | |
| 550 | /* | |
| 551 | * 2. Set FIFO parameters | |
| 552 | */ | |
| fae82c8f | 553 | reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF); |
| 3335786a SR |
554 | |
| 555 | /* | |
| 556 | * 3. Set Capabilities 1_2 | |
| 557 | */ | |
| fae82c8f | 558 | reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF); |
| 3335786a SR |
559 | |
| 560 | /* | |
| 561 | * 4. Set Endian | |
| 562 | */ | |
| fae82c8f | 563 | reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0); |
| 3335786a SR |
564 | |
| 565 | /* | |
| 566 | * 4. Init PHY | |
| 567 | */ | |
| fae82c8f MB |
568 | reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000); |
| 569 | reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000); | |
| 3335786a SR |
570 | |
| 571 | /* | |
| 572 | * 5. DLL reset | |
| 573 | */ | |
| fae82c8f MB |
574 | reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0); |
| 575 | reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0); | |
| 3335786a SR |
576 | |
| 577 | debug_exit(); | |
| 578 | ||
| 579 | return 1; | |
| 580 | } | |
| 581 | ||
| 582 | /* | |
| 583 | * comphy_sgmii_power_up | |
| 584 | * | |
| 585 | * return: | |
| 586 | */ | |
| 587 | static void comphy_sgmii_phy_init(u32 lane, u32 speed) | |
| 588 | { | |
| 589 | const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix); | |
| 590 | int addr, fix_idx; | |
| 591 | u16 val; | |
| 592 | ||
| 593 | fix_idx = 0; | |
| 594 | for (addr = 0; addr < 512; addr++) { | |
| 595 | /* | |
| 596 | * All PHY register values are defined in full for 3.125Gbps | |
| 597 | * SERDES speed. The values required for 1.25 Gbps are almost | |
| 598 | * the same and only few registers should be "fixed" in | |
| 599 | * comparison to 3.125 Gbps values. These register values are | |
| 600 | * stored in "sgmii_phy_init_fix" array. | |
| 601 | */ | |
| 602 | if ((speed != PHY_SPEED_1_25G) && | |
| 603 | (sgmii_phy_init_fix[fix_idx].addr == addr)) { | |
| 604 | /* Use new value */ | |
| 605 | val = sgmii_phy_init_fix[fix_idx].value; | |
| 606 | if (fix_idx < fix_arr_sz) | |
| 607 | fix_idx++; | |
| 608 | } else { | |
| 609 | val = sgmii_phy_init[addr]; | |
| 610 | } | |
| 611 | ||
| 63cfff9f | 612 | reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF); |
| 3335786a SR |
613 | } |
| 614 | } | |
| 615 | ||
| 616 | /* | |
| 617 | * comphy_sgmii_power_up | |
| 618 | * | |
| 619 | * return: 1 if PLL locked (OK), 0 otherwise (FAIL) | |
| 620 | */ | |
| 621 | static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) | |
| 622 | { | |
| 623 | int ret; | |
| 624 | ||
| 625 | debug_enter(); | |
| 626 | ||
| 627 | /* | |
| 628 | * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 | |
| 629 | */ | |
| fae82c8f | 630 | reg_set(COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); |
| 3335786a SR |
631 | |
| 632 | /* | |
| 633 | * 2. Reset PHY by setting PHY input port PIN_RESET=1. | |
| 634 | * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep | |
| 635 | * PHY TXP/TXN output to idle state during PHY initialization | |
| 636 | * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. | |
| 637 | */ | |
| fae82c8f | 638 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), |
| 3335786a SR |
639 | rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref, |
| 640 | rb_pin_reset_core | rb_pin_pu_pll | | |
| 641 | rb_pin_pu_rx | rb_pin_pu_tx); | |
| 642 | ||
| 643 | /* | |
| 644 | * 5. Release reset to the PHY by setting PIN_RESET=0. | |
| 645 | */ | |
| fae82c8f | 646 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy); |
| 3335786a SR |
647 | |
| 648 | /* | |
| 649 | * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide | |
| 650 | * COMPHY bit rate | |
| 651 | */ | |
| 652 | if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ | |
| fae82c8f | 653 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), |
| 3335786a SR |
654 | (0x8 << rf_gen_rx_sel_shift) | |
| 655 | (0x8 << rf_gen_tx_sel_shift), | |
| 656 | rf_gen_rx_select | rf_gen_tx_select); | |
| 657 | ||
| 658 | } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ | |
| fae82c8f | 659 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), |
| 3335786a SR |
660 | (0x6 << rf_gen_rx_sel_shift) | |
| 661 | (0x6 << rf_gen_tx_sel_shift), | |
| 662 | rf_gen_rx_select | rf_gen_tx_select); | |
| 663 | } else { | |
| 664 | printf("Unsupported COMPHY speed!\n"); | |
| 665 | return 0; | |
| 666 | } | |
| 667 | ||
| 668 | /* | |
| 669 | * 8. Wait 1mS for bandgap and reference clocks to stabilize; | |
| 670 | * then start SW programming. | |
| 671 | */ | |
| 672 | mdelay(10); | |
| 673 | ||
| 674 | /* 9. Program COMPHY register PHY_MODE */ | |
| 210f4aae | 675 | reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), |
| 63cfff9f | 676 | PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask); |
| 3335786a SR |
677 | |
| 678 | /* | |
| 679 | * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK | |
| 680 | * source | |
| 681 | */ | |
| 210f4aae | 682 | reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel); |
| 3335786a SR |
683 | |
| 684 | /* | |
| 685 | * 11. Set correct reference clock frequency in COMPHY register | |
| 686 | * REF_FREF_SEL. | |
| 687 | */ | |
| 688 | if (get_ref_clk() == 40) { | |
| 210f4aae | 689 | reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), |
| 63cfff9f | 690 | 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); |
| 3335786a SR |
691 | } else { |
| 692 | /* 25MHz */ | |
| 210f4aae | 693 | reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), |
| 63cfff9f | 694 | 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask); |
| 3335786a SR |
695 | } |
| 696 | ||
| 697 | /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */ | |
| 698 | /* | |
| 699 | * This step is mentioned in the flow received from verification team. | |
| 700 | * However the PHY_GEN_MAX value is only meaningful for other | |
| 701 | * interfaces (not SGMII). For instance, it selects SATA speed | |
| 702 | * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps | |
| 703 | */ | |
| 704 | ||
| 705 | /* | |
| 706 | * 13. Program COMPHY register SEL_BITS to set correct parallel data | |
| 707 | * bus width | |
| 708 | */ | |
| 709 | /* 10bit */ | |
| 210f4aae | 710 | reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask); |
| 3335786a SR |
711 | |
| 712 | /* | |
| 713 | * 14. As long as DFE function needs to be enabled in any mode, | |
| 714 | * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F | |
| 715 | * for real chip during COMPHY power on. | |
| 716 | */ | |
| 717 | /* | |
| 718 | * The step 14 exists (and empty) in the original initialization flow | |
| 719 | * obtained from the verification team. According to the functional | |
| 720 | * specification DFE_UPDATE_EN already has the default value 0x3F | |
| 721 | */ | |
| 722 | ||
| 723 | /* | |
| 724 | * 15. Program COMPHY GEN registers. | |
| 725 | * These registers should be programmed based on the lab testing | |
| 726 | * result to achieve optimal performance. Please contact the CEA | |
| 727 | * group to get the related GEN table during real chip bring-up. | |
| 728 | * We only requred to run though the entire registers programming | |
| 729 | * flow defined by "comphy_sgmii_phy_init" when the REF clock is | |
| 730 | * 40 MHz. For REF clock 25 MHz the default values stored in PHY | |
| 731 | * registers are OK. | |
| 732 | */ | |
| 733 | debug("Running C-DPI phy init %s mode\n", | |
| 734 | speed == PHY_SPEED_3_125G ? "2G5" : "1G"); | |
| 735 | if (get_ref_clk() == 40) | |
| 736 | comphy_sgmii_phy_init(lane, speed); | |
| 737 | ||
| 738 | /* | |
| 739 | * 16. [Simulation Only] should not be used for real chip. | |
| 740 | * By pass power up calibration by programming EXT_FORCE_CAL_DONE | |
| 741 | * (R02h[9]) to 1 to shorten COMPHY simulation time. | |
| 742 | */ | |
| 743 | /* | |
| 744 | * 17. [Simulation Only: should not be used for real chip] | |
| 745 | * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX | |
| 746 | * training simulation time. | |
| 747 | */ | |
| 748 | ||
| 749 | /* | |
| 750 | * 18. Check the PHY Polarity invert bit | |
| 751 | */ | |
| 752 | if (invert & PHY_POLARITY_TXD_INVERT) | |
| 210f4aae | 753 | reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); |
| 3335786a SR |
754 | |
| 755 | if (invert & PHY_POLARITY_RXD_INVERT) | |
| 210f4aae | 756 | reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); |
| 3335786a SR |
757 | |
| 758 | /* | |
| 759 | * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 | |
| 760 | * to start PHY power up sequence. All the PHY register | |
| 761 | * programming should be done before PIN_PU_PLL=1. There should be | |
| 762 | * no register programming for normal PHY operation from this point. | |
| 763 | */ | |
| fae82c8f | 764 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), |
| 3335786a SR |
765 | rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx, |
| 766 | rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx); | |
| 767 | ||
| 768 | /* | |
| 769 | * 20. Wait for PHY power up sequence to finish by checking output ports | |
| 770 | * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. | |
| 771 | */ | |
| fae82c8f | 772 | ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ |
| 3335786a SR |
773 | rb_pll_ready_tx | rb_pll_ready_rx, /* value */ |
| 774 | rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ | |
| 775 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 776 | POLL_32B_REG); /* 32bit */ | |
| 777 | if (ret == 0) | |
| 778 | printf("Failed to lock PLL for SGMII PHY %d\n", lane); | |
| 779 | ||
| 780 | /* | |
| 781 | * 21. Set COMPHY input port PIN_TX_IDLE=0 | |
| 782 | */ | |
| fae82c8f | 783 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle); |
| 3335786a SR |
784 | |
| 785 | /* | |
| 786 | * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. | |
| 787 | * to start RX initialization. PIN_RX_INIT_DONE will be cleared to | |
| 788 | * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE | |
| 789 | * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after | |
| 790 | * PIN_RX_INIT_DONE= 1. | |
| 791 | * Please refer to RX initialization part for details. | |
| 792 | */ | |
| fae82c8f | 793 | reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0); |
| 3335786a | 794 | |
| fae82c8f | 795 | ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */ |
| 3335786a SR |
796 | rb_rx_init_done, /* value */ |
| 797 | rb_rx_init_done, /* mask */ | |
| 798 | PLL_LOCK_TIMEOUT, /* timeout */ | |
| 799 | POLL_32B_REG); /* 32bit */ | |
| 800 | if (ret == 0) | |
| 801 | printf("Failed to init RX of SGMII PHY %d\n", lane); | |
| 802 | ||
| 803 | debug_exit(); | |
| 804 | ||
| 805 | return ret; | |
| 806 | } | |
| 807 | ||
| 808 | void comphy_dedicated_phys_init(void) | |
| 809 | { | |
| 810 | int node, usb32, ret = 1; | |
| 811 | const void *blob = gd->fdt_blob; | |
| 812 | ||
| 813 | debug_enter(); | |
| 814 | ||
| 815 | for (usb32 = 0; usb32 <= 1; usb32++) { | |
| 816 | /* | |
| 817 | * There are 2 UTMI PHYs in this SOC. | |
| 818 | * One is independendent and one is paired with USB3 port (OTG) | |
| 819 | */ | |
| 820 | if (usb32 == 0) { | |
| 821 | node = fdt_node_offset_by_compatible( | |
| 822 | blob, -1, "marvell,armada-3700-ehci"); | |
| 823 | } else { | |
| 824 | node = fdt_node_offset_by_compatible( | |
| 825 | blob, -1, "marvell,armada3700-xhci"); | |
| 826 | } | |
| 827 | ||
| 828 | if (node > 0) { | |
| 829 | if (fdtdec_get_is_enabled(blob, node)) { | |
| 830 | ret = comphy_usb2_power_up(usb32); | |
| 831 | if (ret == 0) | |
| 832 | printf("Failed to initialize UTMI PHY\n"); | |
| 833 | else | |
| 834 | debug("UTMI PHY init succeed\n"); | |
| 835 | } else { | |
| 836 | debug("USB%d node is disabled\n", | |
| 837 | usb32 == 0 ? 2 : 3); | |
| 838 | } | |
| 839 | } else { | |
| 840 | debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3); | |
| 841 | } | |
| 842 | } | |
| 843 | ||
| 844 | node = fdt_node_offset_by_compatible(blob, -1, | |
| 845 | "marvell,armada-3700-ahci"); | |
| 846 | if (node > 0) { | |
| 847 | if (fdtdec_get_is_enabled(blob, node)) { | |
| 848 | ret = comphy_sata_power_up(); | |
| 849 | if (ret == 0) | |
| 850 | printf("Failed to initialize SATA PHY\n"); | |
| 851 | else | |
| 852 | debug("SATA PHY init succeed\n"); | |
| 853 | } else { | |
| 854 | debug("SATA node is disabled\n"); | |
| 855 | } | |
| 856 | } else { | |
| 857 | debug("No SATA node in DT\n"); | |
| 858 | } | |
| 859 | ||
| 860 | node = fdt_node_offset_by_compatible(blob, -1, | |
| 14319908 | 861 | "marvell,armada-8k-sdhci"); |
| 3335786a | 862 | if (node <= 0) { |
| 14319908 SR |
863 | node = fdt_node_offset_by_compatible( |
| 864 | blob, -1, "marvell,armada-3700-sdhci"); | |
| 3335786a SR |
865 | } |
| 866 | ||
| 867 | if (node > 0) { | |
| 868 | if (fdtdec_get_is_enabled(blob, node)) { | |
| 869 | ret = comphy_emmc_power_up(); | |
| 870 | if (ret == 0) | |
| 871 | printf("Failed to initialize SDIO/eMMC PHY\n"); | |
| 872 | else | |
| 873 | debug("SDIO/eMMC PHY init succeed\n"); | |
| 874 | } else { | |
| 875 | debug("SDIO/eMMC node is disabled\n"); | |
| 876 | } | |
| 877 | } else { | |
| 878 | debug("No SDIO/eMMC node in DT\n"); | |
| 879 | } | |
| 880 | ||
| 881 | debug_exit(); | |
| 882 | } | |
| 883 | ||
| 884 | int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, | |
| 885 | struct comphy_map *serdes_map) | |
| 886 | { | |
| 887 | struct comphy_map *comphy_map; | |
| 888 | u32 comphy_max_count = chip_cfg->comphy_lanes_count; | |
| 889 | u32 lane, ret = 0; | |
| 890 | ||
| 891 | debug_enter(); | |
| 892 | ||
| 893 | for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count; | |
| 894 | lane++, comphy_map++) { | |
| 895 | debug("Initialize serdes number %d\n", lane); | |
| 896 | debug("Serdes type = 0x%x invert=%d\n", | |
| 897 | comphy_map->type, comphy_map->invert); | |
| 898 | ||
| 899 | switch (comphy_map->type) { | |
| 900 | case PHY_TYPE_UNCONNECTED: | |
| 901 | continue; | |
| 902 | break; | |
| 903 | ||
| 904 | case PHY_TYPE_PEX0: | |
| 905 | ret = comphy_pcie_power_up(comphy_map->speed, | |
| 906 | comphy_map->invert); | |
| 907 | break; | |
| 908 | ||
| 909 | case PHY_TYPE_USB3_HOST0: | |
| 910 | case PHY_TYPE_USB3_DEVICE: | |
| 911 | ret = comphy_usb3_power_up(comphy_map->type, | |
| 912 | comphy_map->speed, | |
| 913 | comphy_map->invert); | |
| 914 | break; | |
| 915 | ||
| 916 | case PHY_TYPE_SGMII0: | |
| 917 | case PHY_TYPE_SGMII1: | |
| 918 | ret = comphy_sgmii_power_up(lane, comphy_map->speed, | |
| 919 | comphy_map->invert); | |
| 920 | break; | |
| 921 | ||
| 922 | default: | |
| 923 | debug("Unknown SerDes type, skip initialize SerDes %d\n", | |
| 924 | lane); | |
| 925 | ret = 1; | |
| 926 | break; | |
| 927 | } | |
| 928 | if (ret == 0) | |
| 929 | printf("PLL is not locked - Failed to initialize lane %d\n", | |
| 930 | lane); | |
| 931 | } | |
| 932 | ||
| 933 | debug_exit(); | |
| 934 | return ret; | |
| 935 | } |