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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
5b845b66 | 2 | /* |
5da627a4 WD |
3 | * (C) Copyright 2003 |
4 | * Steven Scholz, imc Measurement & Control, [email protected] | |
5 | * | |
5b845b66 WD |
6 | * (C) Copyright 2002 |
7 | * Rich Ireland, Enterasys Networks, [email protected]. | |
5b845b66 WD |
8 | */ |
9 | ||
6c62e8ff AD |
10 | #define LOG_CATEGORY UCLASS_FPGA |
11 | ||
5b845b66 WD |
12 | /* |
13 | * Altera FPGA support | |
14 | */ | |
15 | #include <common.h> | |
fda915a4 | 16 | #include <errno.h> |
5da627a4 | 17 | #include <ACEX1K.h> |
f7ae49fc | 18 | #include <log.h> |
3c735e74 | 19 | #include <stratixII.h> |
5b845b66 | 20 | |
2012f238 MV |
21 | static const struct altera_fpga { |
22 | enum altera_family family; | |
23 | const char *name; | |
24 | int (*load)(Altera_desc *, const void *, size_t); | |
25 | int (*dump)(Altera_desc *, const void *, size_t); | |
26 | int (*info)(Altera_desc *); | |
27 | } altera_fpga[] = { | |
28 | #if defined(CONFIG_FPGA_ACEX1K) | |
29 | { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, | |
30 | { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, | |
31 | #elif defined(CONFIG_FPGA_CYCLON2) | |
32 | { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, | |
33 | { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, | |
34 | #endif | |
35 | #if defined(CONFIG_FPGA_STRATIX_II) | |
36 | { Altera_StratixII, "StratixII", StratixII_load, | |
37 | StratixII_dump, StratixII_info }, | |
38 | #endif | |
ff9c4c53 SR |
39 | #if defined(CONFIG_FPGA_STRATIX_V) |
40 | { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, | |
41 | #endif | |
230fe9b2 PM |
42 | #if defined(CONFIG_FPGA_SOCFPGA) |
43 | { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, | |
44 | #endif | |
d2170168 CHA |
45 | #if defined(CONFIG_FPGA_INTEL_SDM_MAILBOX) |
46 | { Intel_FPGA_SDM_Mailbox, "Intel SDM Mailbox", intel_sdm_mb_load, NULL, | |
47 | NULL }, | |
48 | #endif | |
2012f238 MV |
49 | }; |
50 | ||
54c96b18 MV |
51 | static int altera_validate(Altera_desc *desc, const char *fn) |
52 | { | |
53 | if (!desc) { | |
54 | printf("%s: NULL descriptor!\n", fn); | |
fda915a4 | 55 | return -EINVAL; |
54c96b18 MV |
56 | } |
57 | ||
58 | if ((desc->family < min_altera_type) || | |
59 | (desc->family > max_altera_type)) { | |
60 | printf("%s: Invalid family type, %d\n", fn, desc->family); | |
fda915a4 | 61 | return -EINVAL; |
54c96b18 MV |
62 | } |
63 | ||
64 | if ((desc->iface < min_altera_iface_type) || | |
65 | (desc->iface > max_altera_iface_type)) { | |
66 | printf("%s: Invalid Interface type, %d\n", fn, desc->iface); | |
fda915a4 | 67 | return -EINVAL; |
54c96b18 MV |
68 | } |
69 | ||
70 | if (!desc->size) { | |
71 | printf("%s: NULL part size\n", fn); | |
fda915a4 | 72 | return -EINVAL; |
54c96b18 MV |
73 | } |
74 | ||
fda915a4 | 75 | return 0; |
54c96b18 | 76 | } |
5da627a4 | 77 | |
2012f238 MV |
78 | static const struct altera_fpga * |
79 | altera_desc_to_fpga(Altera_desc *desc, const char *fn) | |
5b845b66 | 80 | { |
2012f238 | 81 | int i; |
5da627a4 | 82 | |
2012f238 MV |
83 | if (altera_validate(desc, fn)) { |
84 | printf("%s: Invalid device descriptor\n", fn); | |
85 | return NULL; | |
4a4c0a5e MV |
86 | } |
87 | ||
2012f238 MV |
88 | for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) { |
89 | if (desc->family == altera_fpga[i].family) | |
90 | break; | |
91 | } | |
5da627a4 | 92 | |
2012f238 MV |
93 | if (i == ARRAY_SIZE(altera_fpga)) { |
94 | printf("%s: Unsupported family type, %d\n", fn, desc->family); | |
95 | return NULL; | |
5da627a4 WD |
96 | } |
97 | ||
2012f238 | 98 | return &altera_fpga[i]; |
5b845b66 WD |
99 | } |
100 | ||
2012f238 | 101 | int altera_load(Altera_desc *desc, const void *buf, size_t bsize) |
5b845b66 | 102 | { |
2012f238 | 103 | const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); |
5da627a4 | 104 | |
2012f238 | 105 | if (!fpga) |
4a4c0a5e | 106 | return FPGA_FAIL; |
4a4c0a5e | 107 | |
6c62e8ff | 108 | log_debug("Launching the %s Loader...\n", fpga->name); |
2012f238 MV |
109 | if (fpga->load) |
110 | return fpga->load(desc, buf, bsize); | |
111 | return 0; | |
112 | } | |
5da627a4 | 113 | |
2012f238 MV |
114 | int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) |
115 | { | |
116 | const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); | |
5da627a4 | 117 | |
2012f238 MV |
118 | if (!fpga) |
119 | return FPGA_FAIL; | |
120 | ||
6c62e8ff | 121 | log_debug("Launching the %s Reader...\n", fpga->name); |
2012f238 MV |
122 | if (fpga->dump) |
123 | return fpga->dump(desc, buf, bsize); | |
124 | return 0; | |
5b845b66 WD |
125 | } |
126 | ||
4a4c0a5e | 127 | int altera_info(Altera_desc *desc) |
5b845b66 | 128 | { |
2012f238 | 129 | const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); |
5da627a4 | 130 | |
2012f238 | 131 | if (!fpga) |
4a4c0a5e | 132 | return FPGA_FAIL; |
5da627a4 | 133 | |
2012f238 | 134 | printf("Family: \t%s\n", fpga->name); |
5da627a4 | 135 | |
4a4c0a5e MV |
136 | printf("Interface type:\t"); |
137 | switch (desc->iface) { | |
138 | case passive_serial: | |
139 | printf("Passive Serial (PS)\n"); | |
140 | break; | |
141 | case passive_parallel_synchronous: | |
142 | printf("Passive Parallel Synchronous (PPS)\n"); | |
143 | break; | |
144 | case passive_parallel_asynchronous: | |
145 | printf("Passive Parallel Asynchronous (PPA)\n"); | |
146 | break; | |
147 | case passive_serial_asynchronous: | |
148 | printf("Passive Serial Asynchronous (PSA)\n"); | |
149 | break; | |
150 | case altera_jtag_mode: /* Not used */ | |
151 | printf("JTAG Mode\n"); | |
152 | break; | |
153 | case fast_passive_parallel: | |
154 | printf("Fast Passive Parallel (FPP)\n"); | |
155 | break; | |
156 | case fast_passive_parallel_security: | |
157 | printf("Fast Passive Parallel with Security (FPPS)\n"); | |
158 | break; | |
877ec6eb ACH |
159 | case secure_device_manager_mailbox: |
160 | puts("Secure Device Manager (SDM) Mailbox\n"); | |
161 | break; | |
4a4c0a5e MV |
162 | /* Add new interface types here */ |
163 | default: | |
164 | printf("Unsupported interface type, %d\n", desc->iface); | |
165 | } | |
166 | ||
167 | printf("Device Size: \t%zd bytes\n" | |
168 | "Cookie: \t0x%x (%d)\n", | |
169 | desc->size, desc->cookie, desc->cookie); | |
5da627a4 | 170 | |
4a4c0a5e MV |
171 | if (desc->iface_fns) { |
172 | printf("Device Function Table @ 0x%p\n", desc->iface_fns); | |
2012f238 MV |
173 | if (fpga->info) |
174 | fpga->info(desc); | |
5da627a4 | 175 | } else { |
4a4c0a5e | 176 | printf("No Device Function Table.\n"); |
5da627a4 WD |
177 | } |
178 | ||
2012f238 | 179 | return FPGA_SUCCESS; |
5da627a4 | 180 | } |