[J-u-boot.git] / include / configs / vexpress_aemv8a.h

/*
 * Configuration for Versatile Express. Parts were derived from other ARM
 *   configurations.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H

/* We use generic board for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARMV8_SWITCH_TO_EL1
#endif

#define CONFIG_REMAKE_ELF

#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \
    !defined(CONFIG_TARGET_VEXPRESS64_JUNO)
/* Base FVP and Juno not using GICv3 yet */
#define CONFIG_GICV3
#endif

/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/

#define CONFIG_SUPPORT_RAW_INITRD

/* Cache Definitions */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_ICACHE_OFF

#define CONFIG_IDENT_STRING		" vexpress_aemv8a"
#define CONFIG_BOOTP_VCI_STRING		"U-boot.armv8.vexpress_aemv8a"

/* Link Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_TEXT_BASE		0x88000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_TEXT_BASE		0xe0000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#else
#define CONFIG_SYS_TEXT_BASE		0x80000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#endif

/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT

/* CS register bases for the original memory map. */
#define V2M_PA_CS0			0x00000000
#define V2M_PA_CS1			0x14000000
#define V2M_PA_CS2			0x18000000
#define V2M_PA_CS3			0x1c000000
#define V2M_PA_CS4			0x0c000000
#define V2M_PA_CS5			0x10000000

#define V2M_PERIPH_OFFSET(x)		(x << 16)
#define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
#define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
#define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))

#define V2M_BASE			0x80000000

/* Common peripherals relative to CS7. */
#define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
#define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))

#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define V2M_UART0			0x7ff80000
#define V2M_UART1			0x7ff70000
#else /* Not Juno */
#define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
#define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
#define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
#define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
#endif

#define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))

#define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
#define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))

#define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
#define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))

#define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))

#define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))

/* System register offsets. */
#define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
#define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
#define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */

/* Generic Interrupt Controller Definitions */
#ifdef CONFIG_GICV3
#define GICD_BASE			(0x2f000000)
#define GICR_BASE			(0x2f100000)
#else

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define GICD_BASE			(0x2f000000)
#define GICC_BASE			(0x2c000000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define GICD_BASE			(0x2C010000)
#define GICC_BASE			(0x2C02f000)
#else
#define GICD_BASE			(0x2C001000)
#define GICC_BASE			(0x2C002000)
#endif
#endif

#define CONFIG_SYS_MEMTEST_START	V2M_BASE
#define CONFIG_SYS_MEMTEST_END		(V2M_BASE + 0x80000000)

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))

/* Ethernet Configuration */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
/* The real hardware Versatile express uses SMSC9118 */
#define CONFIG_SMC911X			1
#define CONFIG_SMC911X_32_BIT		1
#define CONFIG_SMC911X_BASE		(0x018000000)
#else
/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111			1
#define CONFIG_SMC91111_BASE		(0x01A000000)
#endif

/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK		7273800
#else
#define CONFIG_PL011_CLOCK		24000000
#endif
#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
					 (void *)CONFIG_SYS_SERIAL1}
#define CONFIG_CONS_INDEX		0

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_SERIAL0		V2M_UART0
#define CONFIG_SYS_SERIAL1		V2M_UART1

/* Command line configuration */
#define CONFIG_MENU
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTI
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2048 MB */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1

/* Initial environment variables */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_name=uImage\0"	\
				"kernel_addr_r=0x80000000\0"	\
				"initrd_name=ramdisk.img\0"	\
				"initrd_addr_r=0x88000000\0"	\
				"fdt_name=devtree.dtb\0"		\
				"fdt_addr_r=0x83000000\0"		\
				"fdt_high=0xffffffffffffffff\0"	\
				"initrd_high=0xffffffffffffffff\0"

#define CONFIG_BOOTARGS		"console=ttyAMA0 earlyprintk=pl011,"\
				"0x1c090000 debug user_debug=31 "\
				"loglevel=9"

#define CONFIG_BOOTCOMMAND	"fdt addr $fdt_addr_r; fdt resize; " \
				"fdt chosen $initrd_addr_r $initrd_end; " \
				"bootm $kernel_addr_r - $fdt_addr_r"

#define CONFIG_BOOTDELAY		1

#else

#define CONFIG_EXTRA_ENV_SETTINGS	\
					"kernel_addr_r=0x80000000\0"	\
					"initrd_addr_r=0x88000000\0"	\
					"fdt_addr_r=0x83000000\0"		\
					"fdt_high=0xa0000000\0"

#define CONFIG_BOOTARGS			"console=ttyAMA0,115200n8 root=/dev/ram0"
#define CONFIG_BOOTCOMMAND		"bootm $kernel_addr_r " \
					"$initrd_addr_r:$initrd_size $fdt_addr_r"
#define CONFIG_BOOTDELAY		-1
#endif

/* Do not preserve environment */
#define CONFIG_ENV_IS_NOWHERE		1
#define CONFIG_ENV_SIZE			0x1000

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PROMPT		"VExpress64# "
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS		64	/* max command args */

/* Flash memory is available on the Juno board only */
#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_NO_FLASH
#else
#define CONFIG_CMD_FLASH
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER		1
#define CONFIG_SYS_FLASH_BASE		0x08000000
#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MiB */
#define CONFIG_SYS_MAX_FLASH_BANKS	2

/* Timeout values in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */

/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
#define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */

#endif

#endif /* __VEXPRESS_AEMV8A_H */
Commit	Line	Data
12916829 DF	1	/*
	2	* Configuration for Versatile Express. Parts were derived from other ARM
	3	* configurations.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __VEXPRESS_AEMV8A_H
	9	#define __VEXPRESS_AEMV8A_H
	10
03ca6a39 LW	11	/* We use generic board for v8 Versatile Express */
	12	#define CONFIG_SYS_GENERIC_BOARD
	13
f91afc4d	14	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760	15	#ifndef CONFIG_SEMIHOSTING
f91afc4d	16	#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
261d2760 DR	17	#endif
	18	#define CONFIG_BOARD_LATE_INIT
	19	#define CONFIG_ARMV8_SWITCH_TO_EL1
	20	#endif
	21
12916829 DF	22	#define CONFIG_REMAKE_ELF
12916829 DF	23
ffc10373 LW	24	#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \
ffc10373 LW	25	!defined(CONFIG_TARGET_VEXPRESS64_JUNO)
f91afc4d	26	/* Base FVP and Juno not using GICv3 yet */
c71645ad	27	#define CONFIG_GICV3
261d2760	28	#endif
c71645ad	29
12916829 DF	30	/#define CONFIG_ARMV8_SWITCH_TO_EL1/
12916829 DF	31
12916829 DF	32	#define CONFIG_SUPPORT_RAW_INITRD
	33
	34	/* Cache Definitions */
	35	#define CONFIG_SYS_DCACHE_OFF
	36	#define CONFIG_SYS_ICACHE_OFF
	37
	38	#define CONFIG_IDENT_STRING " vexpress_aemv8a"
	39	#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
	40
	41	/* Link Definitions */
f91afc4d	42	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	43	/* ATF loads u-boot here for BASE_FVP model */
	44	#define CONFIG_SYS_TEXT_BASE 0x88000000
	45	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
ffc10373 LW	46	#elif CONFIG_TARGET_VEXPRESS64_JUNO
	47	#define CONFIG_SYS_TEXT_BASE 0xe0000000
	48	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
261d2760	49	#else
12916829 DF	50	#define CONFIG_SYS_TEXT_BASE 0x80000000
12916829 DF	51	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
261d2760	52	#endif
12916829 DF	53
	54	/* Flat Device Tree Definitions */
	55	#define CONFIG_OF_LIBFDT
	56
12916829 DF	57	/* CS register bases for the original memory map. */
	58	#define V2M_PA_CS0 0x00000000
	59	#define V2M_PA_CS1 0x14000000
	60	#define V2M_PA_CS2 0x18000000
	61	#define V2M_PA_CS3 0x1c000000
	62	#define V2M_PA_CS4 0x0c000000
	63	#define V2M_PA_CS5 0x10000000
	64
	65	#define V2M_PERIPH_OFFSET(x) (x << 16)
	66	#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
	67	#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
	68	#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
	69
	70	#define V2M_BASE 0x80000000
	71
12916829 DF	72	/* Common peripherals relative to CS7. */
	73	#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
	74	#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
	75	#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
	76	#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
	77
ffc10373 LW	78	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	79	#define V2M_UART0 0x7ff80000
	80	#define V2M_UART1 0x7ff70000
	81	#else /* Not Juno */
12916829 DF	82	#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
	83	#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
	84	#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
	85	#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
ffc10373	86	#endif
12916829 DF	87
	88	#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
	89
	90	#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
	91	#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
	92
	93	#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
	94	#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
	95
	96	#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
	97
	98	#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
	99
	100	/* System register offsets. */
	101	#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
	102	#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
	103	#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
	104
	105	/* Generic Timer Definitions */
	106	#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
	107
	108	/* Generic Interrupt Controller Definitions */
c71645ad DF	109	#ifdef CONFIG_GICV3
	110	#define GICD_BASE (0x2f000000)
	111	#define GICR_BASE (0x2f100000)
	112	#else
261d2760	113
f91afc4d	114	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	115	#define GICD_BASE (0x2f000000)
261d2760 DR	116	#define GICC_BASE (0x2c000000)
ffc10373 LW	117	#elif CONFIG_TARGET_VEXPRESS64_JUNO
	118	#define GICD_BASE (0x2C010000)
	119	#define GICC_BASE (0x2C02f000)
261d2760	120	#else
12916829 DF	121	#define GICD_BASE (0x2C001000)
12916829 DF	122	#define GICC_BASE (0x2C002000)
c71645ad	123	#endif
261d2760	124	#endif
12916829 DF	125
	126	#define CONFIG_SYS_MEMTEST_START V2M_BASE
	127	#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000)
	128
	129	/* Size of malloc() pool */
5bcae13e	130	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
12916829	131
b31f9d7a LW	132	/* Ethernet Configuration */
	133	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	134	/* The real hardware Versatile express uses SMSC9118 */
	135	#define CONFIG_SMC911X 1
	136	#define CONFIG_SMC911X_32_BIT 1
	137	#define CONFIG_SMC911X_BASE (0x018000000)
	138	#else
	139	/* The Vexpress64 simulators use SMSC91C111 */
3865ceb7 BS	140	#define CONFIG_SMC91111 1
3865ceb7 BS	141	#define CONFIG_SMC91111_BASE (0x01A000000)
b31f9d7a	142	#endif
12916829 DF	143
	144	/* PL011 Serial Configuration */
	145	#define CONFIG_PL011_SERIAL
ffc10373 LW	146	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	147	#define CONFIG_PL011_CLOCK 7273800
	148	#else
12916829	149	#define CONFIG_PL011_CLOCK 24000000
ffc10373	150	#endif
12916829 DF	151	#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
	152	(void *)CONFIG_SYS_SERIAL1}
	153	#define CONFIG_CONS_INDEX 0
	154
	155	#define CONFIG_BAUDRATE 115200
12916829 DF	156	#define CONFIG_SYS_SERIAL0 V2M_UART0
	157	#define CONFIG_SYS_SERIAL1 V2M_UART1
	158
	159	/* Command line configuration */
	160	#define CONFIG_MENU
	161	/#define CONFIG_MENU_SHOW/
	162	#define CONFIG_CMD_CACHE
	163	#define CONFIG_CMD_BDI
67172528 TR	164	#define CONFIG_CMD_BOOTI
67172528 TR	165	#define CONFIG_CMD_UNZIP
12916829 DF	166	#define CONFIG_CMD_DHCP
	167	#define CONFIG_CMD_PXE
	168	#define CONFIG_CMD_ENV
12916829	169	#define CONFIG_CMD_IMI
ffc10373	170	#define CONFIG_CMD_LOADB
12916829 DF	171	#define CONFIG_CMD_MEMORY
	172	#define CONFIG_CMD_MII
	173	#define CONFIG_CMD_NET
	174	#define CONFIG_CMD_PING
	175	#define CONFIG_CMD_SAVEENV
	176	#define CONFIG_CMD_RUN
	177	#define CONFIG_CMD_BOOTD
	178	#define CONFIG_CMD_ECHO
	179	#define CONFIG_CMD_SOURCE
	180	#define CONFIG_CMD_FAT
	181	#define CONFIG_DOS_PARTITION
	182
	183	/* BOOTP options */
	184	#define CONFIG_BOOTP_BOOTFILESIZE
	185	#define CONFIG_BOOTP_BOOTPATH
	186	#define CONFIG_BOOTP_GATEWAY
	187	#define CONFIG_BOOTP_HOSTNAME
	188	#define CONFIG_BOOTP_PXE
	189	#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
	190
	191	/* Miscellaneous configurable options */
	192	#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
	193
	194	/* Physical Memory Map */
	195	#define CONFIG_NR_DRAM_BANKS 1
	196	#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
	197	#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */
	198	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	199
	200	/* Initial environment variables */
f91afc4d	201	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	202	#define CONFIG_EXTRA_ENV_SETTINGS \
	203	"kernel_name=uImage\0" \
	204	"kernel_addr_r=0x80000000\0" \
	205	"initrd_name=ramdisk.img\0" \
	206	"initrd_addr_r=0x88000000\0" \
	207	"fdt_name=devtree.dtb\0" \
	208	"fdt_addr_r=0x83000000\0" \
	209	"fdt_high=0xffffffffffffffff\0" \
	210	"initrd_high=0xffffffffffffffff\0"
	211
	212	#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\
	213	"0x1c090000 debug user_debug=31 "\
	214	"loglevel=9"
	215
	216	#define CONFIG_BOOTCOMMAND "fdt addr $fdt_addr_r; fdt resize; " \
	217	"fdt chosen $initrd_addr_r $initrd_end; " \
	218	"bootm $kernel_addr_r - $fdt_addr_r"
	219
	220	#define CONFIG_BOOTDELAY 1
	221
	222	#else
	223
12916829	224	#define CONFIG_EXTRA_ENV_SETTINGS \
5bcae13e TR	225	"kernel_addr_r=0x80000000\0" \
	226	"initrd_addr_r=0x88000000\0" \
	227	"fdt_addr_r=0x83000000\0" \
12916829 DF	228	"fdt_high=0xa0000000\0"
12916829 DF	229
b31f9d7a	230	#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0"
261d2760 DR	231	#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \
261d2760 DR	232	"$initrd_addr_r:$initrd_size $fdt_addr_r"
12916829	233	#define CONFIG_BOOTDELAY -1
261d2760	234	#endif
12916829 DF	235
	236	/* Do not preserve environment */
	237	#define CONFIG_ENV_IS_NOWHERE 1
	238	#define CONFIG_ENV_SIZE 0x1000
	239
	240	/* Monitor Command Prompt */
	241	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	242	#define CONFIG_SYS_PROMPT "VExpress64# "
	243	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	244	sizeof(CONFIG_SYS_PROMPT) + 16)
	245	#define CONFIG_SYS_HUSH_PARSER
12916829 DF	246	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
12916829 DF	247	#define CONFIG_SYS_LONGHELP
5bcae13e	248	#define CONFIG_CMDLINE_EDITING
12916829 DF	249	#define CONFIG_SYS_MAXARGS 64 /* max command args */
12916829 DF	250
14f264e6 LW	251	/* Flash memory is available on the Juno board only */
	252	#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
	253	#define CONFIG_SYS_NO_FLASH
	254	#else
	255	#define CONFIG_CMD_FLASH
	256	#define CONFIG_SYS_FLASH_CFI 1
	257	#define CONFIG_FLASH_CFI_DRIVER 1
	258	#define CONFIG_SYS_FLASH_BASE 0x08000000
	259	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
	260	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	261
	262	/* Timeout values in ticks */
	263	#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
	264	#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
	265
	266	/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
	267	#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
	268	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
	269	#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
	270	#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
	271
	272	#endif
	273
12916829	274	#endif /* __VEXPRESS_AEMV8A_H */