projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 21144298 | 2 | /* |
| cb199102 | 3 | * (C) Copyright 2012-2013 |
| 21144298 | 4 | * Texas Instruments, <www.ti.com> |
| 21144298 | 5 | */ |
| da2cc454 NM |
6 | #ifndef PALMAS_H |
| 7 | #define PALMAS_H | |
| 21144298 S |
8 | |
| 9 | #include <common.h> | |
| 10 | #include <i2c.h> | |
| 11 | ||
| e9090fa4 LP |
12 | /* I2C chip addresses, TW6035/37 */ |
| 13 | #define TWL603X_CHIP_P1 0x48 /* Page 1 */ | |
| 14 | #define TWL603X_CHIP_P2 0x49 /* Page 2 */ | |
| 15 | #define TWL603X_CHIP_P3 0x4a /* Page 3 */ | |
| 21144298 | 16 | |
| e9090fa4 LP |
17 | /* TPS659038/39 */ |
| 18 | #define TPS65903X_CHIP_P1 0x58 /* Page 1 */ | |
| 19 | ||
| 20 | /* Page 1 registers (0x1XY translates to page 1, reg addr 0xXY): */ | |
| 21 | ||
| 22 | /* LDO1 control/voltage */ | |
| 23 | #define LDO1_CTRL 0x50 | |
| 24 | #define LDO1_VOLTAGE 0x51 | |
| 25 | ||
| b4b06006 LV |
26 | /* LDO1 control/voltage for LP873x */ |
| 27 | #define LP873X_LDO1_ADDR 0x60 | |
| 28 | #define LP873X_LDO1_CTRL 0x9 | |
| 29 | #define LP873X_LDO1_VOLTAGE 0xa | |
| 30 | #define LP873X_LDO_VOLT_3V0 0x19 | |
| 31 | #define LP873X_LDO_VOLT_1V8 0xa | |
| 32 | #define LP873X_LDO_CTRL_EN (0x1 << 0) | |
| 33 | #define LP873X_LDO_CTRL_EN_PINCTRL (0x1 << 1) | |
| 34 | #define LP873X_LDO_CTRL_RDIS_EN (0x1 << 2) | |
| 35 | ||
| 35fe1cb0 DL |
36 | /* LDO2 control/voltage */ |
| 37 | #define LDO2_CTRL 0x52 | |
| 38 | #define LDO2_VOLTAGE 0x53 | |
| 39 | ||
| cd43b516 LV |
40 | /* LDO2 control/voltage */ |
| 41 | #define LDO4_CTRL 0x5e | |
| 42 | #define LDO4_VOLTAGE 0x5f | |
| 43 | ||
| e9090fa4 | 44 | /* LDO9 control/voltage */ |
| 21144298 S |
45 | #define LDO9_CTRL 0x60 |
| 46 | #define LDO9_VOLTAGE 0x61 | |
| 47 | ||
| e9090fa4 LP |
48 | /* LDOUSB control/voltage */ |
| 49 | #define LDOUSB_CTRL 0x64 | |
| 50 | #define LDOUSB_VOLTAGE 0x65 | |
| 1bd435bc | 51 | #define LDO_CTRL 0x6a |
| e9090fa4 LP |
52 | |
| 53 | /* Control of 32 kHz audio clock */ | |
| 54 | #define CLK32KGAUDIO_CTRL 0xd5 | |
| 55 | ||
| 56 | /* SYSEN2_CTRL for VCC_3v3_AUX supply on the sEVM */ | |
| 57 | #define SYSEN2_CTRL 0xd9 | |
| 58 | ||
| 59 | /* | |
| 60 | * Bit field definitions for LDOx_CTRL, SYSENx_CTRL | |
| 61 | * and some other xxx_CTRL resources: | |
| 62 | */ | |
| 63 | #define LDO9_BYP_EN (1 << 6) /* LDO9 only! */ | |
| 64 | #define RSC_STAT_ON (1 << 4) /* RO status bit! */ | |
| 65 | #define RSC_MODE_SLEEP (1 << 2) | |
| 66 | #define RSC_MODE_ACTIVE (1 << 0) | |
| 67 | ||
| 68 | /* Some LDO voltage values */ | |
| 69 | #define LDO_VOLT_OFF 0 | |
| 70 | #define LDO_VOLT_1V8 0x13 | |
| 71 | #define LDO_VOLT_3V0 0x2b | |
| 72 | #define LDO_VOLT_3V3 0x31 | |
| 73 | /* Request bypass, LDO9 only */ | |
| 74 | #define LDO9_BYPASS 0x3f | |
| 75 | ||
| 76 | /* SMPS7_CTRL */ | |
| 77 | #define SMPS7_CTRL 0x30 | |
| 78 | ||
| 79 | /* SMPS9_CTRL */ | |
| 80 | #define SMPS9_CTRL 0x38 | |
| 81 | #define SMPS9_VOLTAGE 0x3b | |
| 82 | ||
| 1bd435bc DM |
83 | /* SMPS10_CTRL */ |
| 84 | #define SMPS10_CTRL 0x3c | |
| 85 | #define SMPS10_MODE_ACTIVE_D 0x0d | |
| 86 | ||
| e9090fa4 LP |
87 | /* Bit field definitions for SMPSx_CTRL */ |
| 88 | #define SMPS_MODE_ACT_AUTO 1 | |
| 89 | #define SMPS_MODE_ACT_ECO 2 | |
| 90 | #define SMPS_MODE_ACT_FPWM 3 | |
| 91 | #define SMPS_MODE_SLP_AUTO (1 << 2) | |
| 92 | #define SMPS_MODE_SLP_ECO (2 << 2) | |
| 93 | #define SMPS_MODE_SLP_FPWM (3 << 2) | |
| 94 | ||
| 95 | /* | |
| 96 | * Some popular SMPS voltages, all with RANGE=1; note | |
| 97 | * that RANGE cannot be changed on the fly | |
| 98 | */ | |
| 99 | #define SMPS_VOLT_OFF 0 | |
| 100 | #define SMPS_VOLT_1V2 0x90 | |
| 101 | #define SMPS_VOLT_1V8 0xae | |
| 102 | #define SMPS_VOLT_2V1 0xbd | |
| 103 | #define SMPS_VOLT_3V0 0xea | |
| 104 | #define SMPS_VOLT_3V3 0xf9 | |
| 105 | ||
| 106 | /* Backup Battery & VRTC Control */ | |
| 107 | #define BB_VRTC_CTRL 0xa8 | |
| 108 | /* Bit definitions for BB_VRTC_CTRL */ | |
| 109 | #define VRTC_EN_SLP (1 << 6) | |
| 110 | #define VRTC_EN_OFF (1 << 5) | |
| 111 | #define VRTC_PWEN (1 << 4) | |
| 112 | #define BB_LOW_ICHRG (1 << 3) | |
| 113 | #define BB_HIGH_ICHRG (0 << 3) | |
| 114 | #define BB_VSEL_3V0 (0 << 1) | |
| 115 | #define BB_VSEL_2V5 (1 << 1) | |
| 116 | #define BB_VSEL_3V15 (2 << 1) | |
| 117 | #define BB_VSEL_VBAT (3 << 1) | |
| 118 | #define BB_CHRG_EN (1 << 0) | |
| 21144298 | 119 | |
| 2147a169 | 120 | #if !CONFIG_IS_ENABLED(DM_I2C) |
| ff2d57ea NM |
121 | /* |
| 122 | * Functions to read and write from TPS659038/TWL6035/TWL6037 | |
| 123 | * or other Palmas family of TI PMICs | |
| 124 | */ | |
| 125 | static inline int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val) | |
| 126 | { | |
| 127 | return i2c_write(chip_no, reg, 1, &val, 1); | |
| 128 | } | |
| 129 | ||
| 130 | static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) | |
| 131 | { | |
| 132 | return i2c_read(chip_no, reg, 1, val, 1); | |
| 133 | } | |
| fb1b7712 JJH |
134 | #else |
| 135 | int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val); | |
| 136 | int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val); | |
| 137 | #endif | |
| ff2d57ea | 138 | |
| 12733881 | 139 | void palmas_init_settings(void); |
| db4fce8f | 140 | int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage); |
| b4b06006 | 141 | int lp873x_mmc1_poweron_ldo(uint voltage); |
| e9090fa4 LP |
142 | int twl603x_mmc1_set_ldo9(u8 vsel); |
| 143 | int twl603x_audio_power(u8 on); | |
| 144 | int twl603x_enable_bb_charge(u8 bb_fields); | |
| 1bd435bc | 145 | int palmas_enable_ss_ldo(void); |
| da2cc454 NM |
146 | |
| 147 | #endif /* PALMAS_H */ |