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1 | .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
2 | .. sectionauthor:: Udit Kumar <[email protected]> | |
3 | ||
4 | J7200 Platforms | |
5 | =============== | |
6 | ||
7 | Introduction: | |
8 | ------------- | |
9 | The J7200 family of SoCs are part of K3 Multicore SoC architecture platform | |
10 | targeting automotive applications. They are designed as a low power, high | |
11 | performance and highly integrated device architecture, adding significant | |
12 | enhancement on processing power, graphics capability, video and imaging | |
13 | processing, virtualization and coherent memory support. | |
14 | ||
15 | The device is partitioned into three functional domains, each containing | |
16 | specific processing cores and peripherals: | |
17 | ||
18 | 1. Wake-up (WKUP) domain: | |
19 | * Device Management and Security Controller (DMSC) | |
20 | ||
21 | 2. Microcontroller (MCU) domain: | |
22 | * Dual Core ARM Cortex-R5F processor | |
23 | ||
24 | 3. MAIN domain: | |
25 | * Dual core 64-bit ARM Cortex-A72 | |
26 | ||
27 | More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1 | |
28 | ||
29 | Boot Flow: | |
30 | ---------- | |
31 | Below is the pictorial representation of boot flow: | |
32 | ||
33 | .. code-block:: text | |
34 | ||
35 | +------------------------------------------------------------------------+-----------------------+ | |
36 | | DMSC | MCU R5 | A72 | MAIN R5/C7x | | |
37 | +------------------------------------------------------------------------+-----------------------+ | |
38 | | +--------+ | | | | | |
39 | | | Reset | | | | | | |
40 | | +--------+ | | | | | |
41 | | : | | | | | |
42 | | +--------+ | +-----------+ | | | | |
43 | | | *ROM* |----------|-->| Reset rls | | | | | |
44 | | +--------+ | +-----------+ | | | | |
45 | | | | | : | | | | |
46 | | | ROM | | : | | | | |
47 | | |services| | : | | | | |
48 | | | | | +-------------+ | | | | |
49 | | | | | | *R5 ROM* | | | | | |
50 | | | | | +-------------+ | | | | |
51 | | | |<---------|---|Load and auth| | | | | |
52 | | | | | | tiboot3.bin | | | | | |
53 | | | Start | | +-------------+ | | | | |
54 | | | TIFS |<---------|---| Start | | | | | |
55 | | | | | | TIFS | | | | | |
56 | | +--------+ | +-------------+ | | | | |
57 | | : | | | | | | | |
58 | | +---------+ | | Load | | | | | |
59 | | | *TIFS* | | | system | | | | | |
60 | | +---------+ | | Config data | | | | | |
61 | | | |<--------|---| | | | | | |
62 | | | | | +-------------+ | | | | |
63 | | | | | : | | | | |
64 | | | | | : | | | | |
65 | | | | | : | | | | |
66 | | | | | +-------------+ | | | | |
67 | | | | | | *R5 SPL* | | | | | |
68 | | | | | +-------------+ | | | | |
69 | | | | | | DDR | | | | | |
70 | | | | | | config | | | | | |
71 | | | | | +-------------+ | | | | |
72 | | | | | | Load | | | | | |
73 | | | | | | tispl.bin | | | | | |
74 | | | | | +-------------+ | | | | |
75 | | | | | | Load R5 | | | | | |
76 | | | | | | firmware | | | | | |
77 | | | | | +-------------+ | | | | |
78 | | | |<--------|---| Start A72 | | | | | |
79 | | | | | | and jump to | | | | | |
80 | | | | | | DM fw image | | | | | |
81 | | | | | +-------------+ | | | | |
82 | | | | | | +-----------+ | | | |
83 | | | |---------|-----------------------|---->| Reset rls | | | | |
84 | | | | | | +-----------+ | | | |
85 | | | TIFS | | | : | | | |
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86 | | |Services | | | +-------------+ | | |
87 | | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | | |
88 | | | | | | +-------------+ | | | |
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89 | | | | | | : | | |
90 | | | | | | +-----------+ | | | |
91 | | | |<--------|-----------------------|---->| *A72 SPL* | | | | |
92 | | | | | | +-----------+ | | | |
93 | | | | | | | Load | | | | |
94 | | | | | | | u-boot.img| | | | |
95 | | | | | | +-----------+ | | | |
96 | | | | | | : | | | |
97 | | | | | | +-----------+ | | | |
98 | | | |<--------|-----------------------|---->| *U-Boot* | | | | |
99 | | | | | | +-----------+ | | | |
100 | | | | | | | prompt | | | | |
101 | | | | | | +-----------+ | | | |
102 | | | | | | | Load R5 | | | | |
103 | | | | | | | Firmware | | | | |
104 | | | | | | +-----------+ | | | |
105 | | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | | |
106 | | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | | |
107 | | | | | | | Load C7 | | +-----------+ | | |
108 | | | | | | | Firmware | | | | |
109 | | | | | | +-----------+ | | | |
110 | | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | | |
111 | | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | | |
112 | | | | | | | +-----------+ | | |
113 | | | | | | | | | |
114 | | +---------+ | | | | | |
115 | | | | | | | |
116 | +------------------------------------------------------------------------+-----------------------+ | |
117 | ||
118 | - Here DMSC acts as master and provides all the critical services. R5/A72 | |
119 | requests DMSC to get these services done as shown in the above diagram. | |
120 | ||
121 | Sources: | |
122 | -------- | |
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123 | 1. Trusted Firmware-A: |
124 | Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ | |
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125 | Branch: master |
126 | ||
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127 | 2. OP-TEE: |
128 | Tree: https://github.com/OP-TEE/optee_os.git | |
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129 | Branch: master |
130 | ||
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131 | 3. U-Boot: |
132 | Tree: https://source.denx.de/u-boot/u-boot | |
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133 | Branch: master |
134 | ||
1ee652ab | 135 | 4. TI Linux Firmware: |
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136 | Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git |
137 | Branch: ti-linux-firmware | |
138 | ||
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139 | Build procedure: |
140 | ---------------- | |
1ee652ab | 141 | 1. Trusted Firmware-A: |
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142 | |
143 | .. code-block:: bash | |
144 | ||
1ee652ab | 145 | $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed |
db7af510 | 146 | |
1ee652ab | 147 | 2. OP-TEE: |
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148 | |
149 | .. code-block:: bash | |
150 | ||
1ee652ab | 151 | $ make PLATFORM=k3-j7200 CFG_ARM64_core=y |
db7af510 | 152 | |
1ee652ab | 153 | 3. U-Boot: |
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154 | |
155 | * 4.1 R5: | |
156 | ||
157 | .. code-block:: bash | |
158 | ||
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159 | $ make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5 |
160 | $ make CROSS_COMPILE=arm-linux-gnueabihf- \ | |
161 | BINMAN_INDIRS=<path/to/ti-linux-firmware> | |
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162 | |
163 | * 4.2 A72: | |
164 | ||
165 | .. code-block:: bash | |
166 | ||
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167 | $ make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72 |
168 | $ make CROSS_COMPILE=aarch64-linux-gnu- \ | |
169 | BL31=<path/to/trusted-firmware-a/dir>/build/k3/generic/release/bl31.bin \ | |
170 | TEE=<path/to/optee_os/dir>/out/arm-plat-k3/core/tee-raw.bin \ | |
171 | BINMAN_INDIRS=<path/to/ti-linux-firmware> | |
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172 | |
173 | Target Images | |
174 | -------------- | |
175 | Copy the below images to an SD card and boot: | |
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176 | |
177 | - GP | |
178 | ||
179 | * tiboot3-j7200-gp-evm.bin from step 4.1 | |
180 | * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2 | |
181 | ||
182 | - HS-FS | |
183 | ||
184 | * tiboot3-j7200_sr2-hs-fs-evm.bin from step 4.1 | |
185 | * tispl.bin, u-boot.img from step 4.2 | |
186 | ||
187 | - HS-SE | |
188 | ||
189 | * tiboot3-j7200_sr2-hs-evm.bin from step 4.1 | |
190 | * tispl.bin, u-boot.img from step 4.2 | |
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191 | |
192 | Image formats: | |
193 | -------------- | |
194 | ||
195 | - tiboot3.bin: | |
196 | ||
197 | .. code-block:: console | |
198 | ||
199 | +-----------------------+ | |
200 | | X.509 | | |
201 | | Certificate | | |
202 | | +-------------------+ | | |
203 | | | | | | |
204 | | | R5 | | | |
205 | | | u-boot-spl.bin | | | |
206 | | | | | | |
207 | | +-------------------+ | | |
208 | | | | | | |
209 | | | FIT header | | | |
210 | | | +---------------+ | | | |
211 | | | | | | | | |
212 | | | | DTB 1...N | | | | |
213 | | | +---------------+ | | | |
214 | | +-------------------+ | | |
215 | | | | | | |
216 | | | FIT HEADER | | | |
217 | | | +---------------+ | | | |
218 | | | | | | | | |
219 | | | | sysfw.bin | | | | |
220 | | | +---------------+ | | | |
221 | | | | | | | | |
222 | | | | board config | | | | |
223 | | | +---------------+ | | | |
224 | | | | | | | | |
225 | | | | PM config | | | | |
226 | | | +---------------+ | | | |
227 | | | | | | | | |
228 | | | | RM config | | | | |
229 | | | +---------------+ | | | |
230 | | | | | | | | |
231 | | | | Secure config | | | | |
232 | | | +---------------+ | | | |
233 | | +-------------------+ | | |
234 | +-----------------------+ | |
235 | ||
236 | - tispl.bin | |
237 | ||
238 | .. code-block:: console | |
239 | ||
240 | +-----------------------+ | |
241 | | | | |
242 | | FIT HEADER | | |
243 | | +-------------------+ | | |
244 | | | | | | |
1ee652ab | 245 | | | A72 TF-A | | |
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246 | | +-------------------+ | |
247 | | | | | | |
1ee652ab | 248 | | | A72 OP-TEE | | |
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249 | | +-------------------+ | |
250 | | | | | | |
251 | | | R5 DM FW | | | |
252 | | +-------------------+ | | |
253 | | | | | | |
254 | | | A72 SPL | | | |
255 | | +-------------------+ | | |
256 | | | | | | |
257 | | | SPL DTB 1...N | | | |
258 | | +-------------------+ | | |
259 | +-----------------------+ | |
260 | ||
261 | ||
262 | Switch Setting for Boot Mode | |
263 | ---------------------------- | |
264 | ||
265 | Boot Mode pins provide means to select the boot mode and options before the | |
266 | device is powered up. After every POR, they are the main source to populate | |
267 | the Boot Parameter Tables. | |
268 | ||
269 | The following table shows some common boot modes used on J7200 platform. More | |
270 | details can be found in the Technical Reference Manual: | |
271 | https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section. | |
272 | ||
273 | ||
274 | *Boot Modes* | |
275 | ||
276 | ============ ============= ============= | |
277 | Switch Label SW9: 12345678 SW8: 12345678 | |
278 | ============ ============= ============= | |
279 | SD 00000000 10000010 | |
280 | EMMC 01000000 10000000 | |
281 | OSPI 01000000 00000110 | |
282 | UART 01110000 00000000 | |
283 | USB DFU 00100000 10000000 | |
284 | ============ ============= ============= | |
285 | ||
286 | For SW8 and SW9, the switch state in the "ON" position = 1. | |
287 | ||
288 | eMMC: | |
289 | ----- | |
290 | ROM supports booting from eMMC raw read or UDA FS mode. | |
291 | ||
292 | Below is memory layout in case of booting from | |
293 | boot 0/1 partition in raw mode. | |
294 | ||
295 | Current allocated size for tiboot3 size is 1MB, tispl is 2MB. | |
296 | ||
297 | Size of u-boot.img is taken 4MB for refernece, | |
298 | But this is subject to change depending upon atf, optee size | |
299 | ||
300 | .. code-block:: console | |
301 | ||
302 | boot0/1 partition (8 MB) user partition | |
303 | 0x0+----------------------------------+ 0x0+------------------------+ | |
304 | | tiboot3.bin (1 MB) | | | | |
305 | 0x800+----------------------------------+ | | | |
306 | | tispl.bin (2 MB) | | | | |
307 | 0x1800+----------------------------------+ | | | |
308 | | u-boot.img (4MB) | | | | |
309 | 0x3800+----------------------------------+ | | | |
310 | | | | | | |
311 | 0x3900+ environment | | | | |
312 | | | | | | |
313 | 0x3A00+----------------------------------+ +-------------------------+ | |
314 | ||
315 | In case of UDA FS mode booting, following is layout. | |
316 | ||
317 | All boot images tiboot3.bin, tispl and u-boot should be written to | |
318 | fat formatted UDA FS as file. | |
319 | ||
320 | .. code-block:: console | |
321 | ||
322 | boot0/1 partition (8 MB) user partition | |
323 | 0x0+---------------------------------+ 0x0+-------------------------+ | |
324 | | | | tiboot3.bin* | | |
325 | 0x800+----------------------------------+ | | | |
326 | | | | tispl.bin | | |
327 | 0x1800+----------------------------------+ | | | |
328 | | | | u-boot.img | | |
329 | 0x3800+----------------------------------+ | | | |
330 | | | | | | |
331 | 0x3900+ | | environment | | |
332 | | | | | | |
333 | 0x3A00+----------------------------------+ +-------------------------+ | |
334 | ||
335 | ||
336 | ||
337 | In case of booting from eMMC, write above images into raw or UDA FS. | |
338 | and set mmc partconf accordingly. |