[J-u-boot.git] / board / freescale / t102xrdb / t1023_nand_rcw.cfg

#PBL preamble and RCW header for T1023RDB
aa55aa55 010e0100
#SerDes Protocol: 0x77
#Default Core=1200MHz, DDR=1600MT/s with single source clock
0810000c 00000000 00000000 00000000
3b800003 00000012 e8104000 21000000
00000000 00000000 00000000 00022800
00000130 04020200 00000000 00000006
Commit	Line	Data
e8a7f1c3 SL	1	#PBL preamble and RCW header for T1023RDB
	2	aa55aa55 010e0100
	3	#SerDes Protocol: 0x77
47deb4b4 SL	4	#Default Core=1200MHz, DDR=1600MT/s with single source clock
47deb4b4 SL	5	0810000c 00000000 00000000 00000000
e8a7f1c3	6	3b800003 00000012 e8104000 21000000
ff7ea2d1	7	00000000 00000000 00000000 00022800
e8a7f1c3	8	00000130 04020200 00000000 00000006