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[J-u-boot.git] / drivers / usb / musb-new / musb_gadget_ep0.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0
eb81955b
IY		 2/*
3 * MUSB OTG peripheral driver ep0 handling
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 * Copyright (C) 2008-2009 MontaVista Software, Inc. <[email protected]>
eb81955b
IY		 9 */
10
eb81955b 11#ifndef __UBOOT__
f7ae49fc 12#include <log.h>
336d4615 13#include <dm/device_compat.h>
eb81955b
IY		 14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/spinlock.h>
18#include <linux/device.h>
19#include <linux/interrupt.h>
20#else
21#include <common.h>
e010524b
SA		 22#include <dm.h>
23#include <dm/device_compat.h>
1e94b46f 24#include <linux/printk.h>
3721eaf2 25#include <asm/processor.h>
e010524b 26#include "linux-compat.h"
eb81955b
IY		 27#endif
28
29#include "musb_core.h"
30
31/* ep0 is always musb->endpoints[0].ep_in */
32#define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
33
34/*
35 * locking note: we use only the controller lock, for simpler correctness.
36 * It's always held with IRQs blocked.
37 *
38 * It protects the ep0 request queue as well as ep0_state, not just the
39 * controller and indexed registers. And that lock stays held unless it
40 * needs to be dropped to allow reentering this driver ... like upcalls to
41 * the gadget driver, or adjusting endpoint halt status.
42 */
43
44static char *decode_ep0stage(u8 stage)
45{
46 switch (stage) {
47 case MUSB_EP0_STAGE_IDLE: return "idle";
48 case MUSB_EP0_STAGE_SETUP: return "setup";
49 case MUSB_EP0_STAGE_TX: return "in";
50 case MUSB_EP0_STAGE_RX: return "out";
51 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
52 case MUSB_EP0_STAGE_STATUSIN: return "in/status";
53 case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
54 default: return "?";
55 }
56}
57
58/* handle a standard GET_STATUS request
59 * Context: caller holds controller lock
60 */
61static int service_tx_status_request(
62 struct musb *musb,
63 const struct usb_ctrlrequest *ctrlrequest)
64{
65 void __iomem *mbase = musb->mregs;
66 int handled = 1;
67 u8 result[2], epnum = 0;
68 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
69
70 result[1] = 0;
71
72 switch (recip) {
73 case USB_RECIP_DEVICE:
74 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
75 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
76 if (musb->g.is_otg) {
77 result[0] |= musb->g.b_hnp_enable
78 << USB_DEVICE_B_HNP_ENABLE;
79 result[0] |= musb->g.a_alt_hnp_support
80 << USB_DEVICE_A_ALT_HNP_SUPPORT;
81 result[0] |= musb->g.a_hnp_support
82 << USB_DEVICE_A_HNP_SUPPORT;
83 }
84 break;
85
86 case USB_RECIP_INTERFACE:
87 result[0] = 0;
88 break;
89
90 case USB_RECIP_ENDPOINT: {
91 int is_in;
92 struct musb_ep *ep;
93 u16 tmp;
94 void __iomem *regs;
95
96 epnum = (u8) ctrlrequest->wIndex;
97 if (!epnum) {
98 result[0] = 0;
99 break;
100 }
101
102 is_in = epnum & USB_DIR_IN;
103 if (is_in) {
104 epnum &= 0x0f;
105 ep = &musb->endpoints[epnum].ep_in;
106 } else {
107 ep = &musb->endpoints[epnum].ep_out;
108 }
109 regs = musb->endpoints[epnum].regs;
110
111 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
112 handled = -EINVAL;
113 break;
114 }
115
116 musb_ep_select(mbase, epnum);
117 if (is_in)
118 tmp = musb_readw(regs, MUSB_TXCSR)
119 & MUSB_TXCSR_P_SENDSTALL;
120 else
121 tmp = musb_readw(regs, MUSB_RXCSR)
122 & MUSB_RXCSR_P_SENDSTALL;
123 musb_ep_select(mbase, 0);
124
125 result[0] = tmp ? 1 : 0;
126 } break;
127
128 default:
129 /* class, vendor, etc ... delegate */
130 handled = 0;
131 break;
132 }
133
134 /* fill up the fifo; caller updates csr0 */
135 if (handled > 0) {
136 u16 len = le16_to_cpu(ctrlrequest->wLength);
137
138 if (len > 2)
139 len = 2;
140 musb_write_fifo(&musb->endpoints[0], len, result);
141 }
142
143 return handled;
144}
145
146/*
147 * handle a control-IN request, the end0 buffer contains the current request
148 * that is supposed to be a standard control request. Assumes the fifo to
149 * be at least 2 bytes long.
150 *
185f812c 151 * Return: 0 if the request was NOT HANDLED,
eb81955b
IY		 152 * < 0 when error
153 * > 0 when the request is processed
154 *
155 * Context: caller holds controller lock
156 */
157static int
158service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
159{
160 int handled = 0; /* not handled */
161
162 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
163 == USB_TYPE_STANDARD) {
164 switch (ctrlrequest->bRequest) {
165 case USB_REQ_GET_STATUS:
166 handled = service_tx_status_request(musb,
167 ctrlrequest);
168 break;
169
170 /* case USB_REQ_SYNC_FRAME: */
171
172 default:
173 break;
174 }
175 }
176 return handled;
177}
178
179/*
180 * Context: caller holds controller lock
181 */
182static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
183{
184 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
185}
186
187/*
188 * Tries to start B-device HNP negotiation if enabled via sysfs
189 */
190static inline void musb_try_b_hnp_enable(struct musb *musb)
191{
192 void __iomem *mbase = musb->mregs;
193 u8 devctl;
194
195 dev_dbg(musb->controller, "HNP: Setting HR\n");
196 devctl = musb_readb(mbase, MUSB_DEVCTL);
197 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
198}
199
200/*
201 * Handle all control requests with no DATA stage, including standard
202 * requests such as:
203 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
204 * always delegated to the gadget driver
205 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
206 * always handled here, except for class/vendor/... features
207 *
208 * Context: caller holds controller lock
209 */
210static int
211service_zero_data_request(struct musb *musb,
212 struct usb_ctrlrequest *ctrlrequest)
213__releases(musb->lock)
214__acquires(musb->lock)
215{
216 int handled = -EINVAL;
217 void __iomem *mbase = musb->mregs;
218 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
219
220 /* the gadget driver handles everything except what we MUST handle */
221 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
222 == USB_TYPE_STANDARD) {
223 switch (ctrlrequest->bRequest) {
224 case USB_REQ_SET_ADDRESS:
225 /* change it after the status stage */
226 musb->set_address = true;
227 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
228 handled = 1;
229 break;
230
231 case USB_REQ_CLEAR_FEATURE:
232 switch (recip) {
233 case USB_RECIP_DEVICE:
234 if (ctrlrequest->wValue
235 != USB_DEVICE_REMOTE_WAKEUP)
236 break;
237 musb->may_wakeup = 0;
238 handled = 1;
239 break;
240 case USB_RECIP_INTERFACE:
241 break;
242 case USB_RECIP_ENDPOINT:{
243 const u8 epnum =
244 ctrlrequest->wIndex & 0x0f;
245 struct musb_ep *musb_ep;
246 struct musb_hw_ep *ep;
247 struct musb_request *request;
248 void __iomem *regs;
249 int is_in;
250 u16 csr;
251
252 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
253 ctrlrequest->wValue != USB_ENDPOINT_HALT)
254 break;
255
256 ep = musb->endpoints + epnum;
257 regs = ep->regs;
258 is_in = ctrlrequest->wIndex & USB_DIR_IN;
259 if (is_in)
260 musb_ep = &ep->ep_in;
261 else
262 musb_ep = &ep->ep_out;
263 if (!musb_ep->desc)
264 break;
265
266 handled = 1;
267 /* Ignore request if endpoint is wedged */
268 if (musb_ep->wedged)
269 break;
270
271 musb_ep_select(mbase, epnum);
272 if (is_in) {
273 csr = musb_readw(regs, MUSB_TXCSR);
274 csr |= MUSB_TXCSR_CLRDATATOG |
275 MUSB_TXCSR_P_WZC_BITS;
276 csr &= ~(MUSB_TXCSR_P_SENDSTALL |
277 MUSB_TXCSR_P_SENTSTALL |
278 MUSB_TXCSR_TXPKTRDY);
279 musb_writew(regs, MUSB_TXCSR, csr);
280 } else {
281 csr = musb_readw(regs, MUSB_RXCSR);
282 csr |= MUSB_RXCSR_CLRDATATOG |
283 MUSB_RXCSR_P_WZC_BITS;
284 csr &= ~(MUSB_RXCSR_P_SENDSTALL |
285 MUSB_RXCSR_P_SENTSTALL);
286 musb_writew(regs, MUSB_RXCSR, csr);
287 }
288
289 /* Maybe start the first request in the queue */
290 request = next_request(musb_ep);
291 if (!musb_ep->busy && request) {
292 dev_dbg(musb->controller, "restarting the request\n");
293 musb_ep_restart(musb, request);
294 }
295
296 /* select ep0 again */
297 musb_ep_select(mbase, 0);
298 } break;
299 default:
300 /* class, vendor, etc ... delegate */
301 handled = 0;
302 break;
303 }
304 break;
305
306 case USB_REQ_SET_FEATURE:
307 switch (recip) {
308 case USB_RECIP_DEVICE:
309 handled = 1;
310 switch (ctrlrequest->wValue) {
311 case USB_DEVICE_REMOTE_WAKEUP:
312 musb->may_wakeup = 1;
313 break;
314 case USB_DEVICE_TEST_MODE:
315 if (musb->g.speed != USB_SPEED_HIGH)
316 goto stall;
317 if (ctrlrequest->wIndex & 0xff)
318 goto stall;
319
320 switch (ctrlrequest->wIndex >> 8) {
321 case 1:
322 pr_debug("TEST_J\n");
323 /* TEST_J */
324 musb->test_mode_nr =
325 MUSB_TEST_J;
326 break;
327 case 2:
328 /* TEST_K */
329 pr_debug("TEST_K\n");
330 musb->test_mode_nr =
331 MUSB_TEST_K;
332 break;
333 case 3:
334 /* TEST_SE0_NAK */
335 pr_debug("TEST_SE0_NAK\n");
336 musb->test_mode_nr =
337 MUSB_TEST_SE0_NAK;
338 break;
339 case 4:
340 /* TEST_PACKET */
341 pr_debug("TEST_PACKET\n");
342 musb->test_mode_nr =
343 MUSB_TEST_PACKET;
344 break;
345
346 case 0xc0:
347 /* TEST_FORCE_HS */
348 pr_debug("TEST_FORCE_HS\n");
349 musb->test_mode_nr =
350 MUSB_TEST_FORCE_HS;
351 break;
352 case 0xc1:
353 /* TEST_FORCE_FS */
354 pr_debug("TEST_FORCE_FS\n");
355 musb->test_mode_nr =
356 MUSB_TEST_FORCE_FS;
357 break;
358 case 0xc2:
359 /* TEST_FIFO_ACCESS */
360 pr_debug("TEST_FIFO_ACCESS\n");
361 musb->test_mode_nr =
362 MUSB_TEST_FIFO_ACCESS;
363 break;
364 case 0xc3:
365 /* TEST_FORCE_HOST */
366 pr_debug("TEST_FORCE_HOST\n");
367 musb->test_mode_nr =
368 MUSB_TEST_FORCE_HOST;
369 break;
370 default:
371 goto stall;
372 }
373
374 /* enter test mode after irq */
375 if (handled > 0)
376 musb->test_mode = true;
377 break;
378 case USB_DEVICE_B_HNP_ENABLE:
379 if (!musb->g.is_otg)
380 goto stall;
381 musb->g.b_hnp_enable = 1;
382 musb_try_b_hnp_enable(musb);
383 break;
384 case USB_DEVICE_A_HNP_SUPPORT:
385 if (!musb->g.is_otg)
386 goto stall;
387 musb->g.a_hnp_support = 1;
388 break;
389 case USB_DEVICE_A_ALT_HNP_SUPPORT:
390 if (!musb->g.is_otg)
391 goto stall;
392 musb->g.a_alt_hnp_support = 1;
393 break;
394 case USB_DEVICE_DEBUG_MODE:
395 handled = 0;
396 break;
397stall:
398 default:
399 handled = -EINVAL;
400 break;
401 }
402 break;
403
404 case USB_RECIP_INTERFACE:
405 break;
406
407 case USB_RECIP_ENDPOINT:{
408 const u8 epnum =
409 ctrlrequest->wIndex & 0x0f;
410 struct musb_ep *musb_ep;
411 struct musb_hw_ep *ep;
412 void __iomem *regs;
413 int is_in;
414 u16 csr;
415
416 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
417 ctrlrequest->wValue != USB_ENDPOINT_HALT)
418 break;
419
420 ep = musb->endpoints + epnum;
421 regs = ep->regs;
422 is_in = ctrlrequest->wIndex & USB_DIR_IN;
423 if (is_in)
424 musb_ep = &ep->ep_in;
425 else
426 musb_ep = &ep->ep_out;
427 if (!musb_ep->desc)
428 break;
429
430 musb_ep_select(mbase, epnum);
431 if (is_in) {
432 csr = musb_readw(regs, MUSB_TXCSR);
433 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
434 csr |= MUSB_TXCSR_FLUSHFIFO;
435 csr |= MUSB_TXCSR_P_SENDSTALL
436 | MUSB_TXCSR_CLRDATATOG
437 | MUSB_TXCSR_P_WZC_BITS;
438 musb_writew(regs, MUSB_TXCSR, csr);
439 } else {
440 csr = musb_readw(regs, MUSB_RXCSR);
441 csr |= MUSB_RXCSR_P_SENDSTALL
442 | MUSB_RXCSR_FLUSHFIFO
443 | MUSB_RXCSR_CLRDATATOG
444 | MUSB_RXCSR_P_WZC_BITS;
445 musb_writew(regs, MUSB_RXCSR, csr);
446 }
447
448 /* select ep0 again */
449 musb_ep_select(mbase, 0);
450 handled = 1;
451 } break;
452
453 default:
454 /* class, vendor, etc ... delegate */
455 handled = 0;
456 break;
457 }
458 break;
459 default:
460 /* delegate SET_CONFIGURATION, etc */
461 handled = 0;
462 }
463 } else
464 handled = 0;
465 return handled;
466}
467
468/* we have an ep0out data packet
469 * Context: caller holds controller lock
470 */
471static void ep0_rxstate(struct musb *musb)
472{
473 void __iomem *regs = musb->control_ep->regs;
474 struct musb_request *request;
475 struct usb_request *req;
476 u16 count, csr;
477
478 request = next_ep0_request(musb);
479 req = &request->request;
480
481 /* read packet and ack; or stall because of gadget driver bug:
482 * should have provided the rx buffer before setup() returned.
483 */
484 if (req) {
485 void *buf = req->buf + req->actual;
486 unsigned len = req->length - req->actual;
487
488 /* read the buffer */
489 count = musb_readb(regs, MUSB_COUNT0);
490 if (count > len) {
491 req->status = -EOVERFLOW;
492 count = len;
493 }
494 musb_read_fifo(&musb->endpoints[0], count, buf);
495 req->actual += count;
496 csr = MUSB_CSR0_P_SVDRXPKTRDY;
497 if (count < 64 || req->actual == req->length) {
498 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
499 csr |= MUSB_CSR0_P_DATAEND;
500 } else
501 req = NULL;
502 } else
503 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
504
505
506 /* Completion handler may choose to stall, e.g. because the
507 * message just received holds invalid data.
508 */
509 if (req) {
510 musb->ackpend = csr;
511 musb_g_ep0_giveback(musb, req);
512 if (!musb->ackpend)
513 return;
514 musb->ackpend = 0;
515 }
516 musb_ep_select(musb->mregs, 0);
517 musb_writew(regs, MUSB_CSR0, csr);
518}
519
520/*
521 * transmitting to the host (IN), this code might be called from IRQ
522 * and from kernel thread.
523 *
524 * Context: caller holds controller lock
525 */
526static void ep0_txstate(struct musb *musb)
527{
528 void __iomem *regs = musb->control_ep->regs;
529 struct musb_request *req = next_ep0_request(musb);
530 struct usb_request *request;
531 u16 csr = MUSB_CSR0_TXPKTRDY;
532 u8 *fifo_src;
533 u8 fifo_count;
534
535 if (!req) {
536 /* WARN_ON(1); */
537 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
538 return;
539 }
540
541 request = &req->request;
542
543 /* load the data */
544 fifo_src = (u8 *) request->buf + request->actual;
545 fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
546 request->length - request->actual);
547 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
548 request->actual += fifo_count;
549
550 /* update the flags */
551 if (fifo_count < MUSB_MAX_END0_PACKET
552 || (request->actual == request->length
553 && !request->zero)) {
554 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
555 csr |= MUSB_CSR0_P_DATAEND;
556 } else
557 request = NULL;
558
ab2f5c12
HS		 559 /* send it out, triggering a "txpktrdy cleared" irq */
560 musb_ep_select(musb->mregs, 0);
561 musb_writew(regs, MUSB_CSR0, csr);
562
eb81955b
IY		 563 /* report completions as soon as the fifo's loaded; there's no
564 * win in waiting till this last packet gets acked. (other than
565 * very precise fault reporting, needed by USB TMC; possible with
566 * this hardware, but not usable from portable gadget drivers.)
567 */
568 if (request) {
569 musb->ackpend = csr;
570 musb_g_ep0_giveback(musb, request);
571 if (!musb->ackpend)
572 return;
573 musb->ackpend = 0;
574 }
eb81955b
IY		 575}
576
577/*
578 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
579 * Fields are left in USB byte-order.
580 *
581 * Context: caller holds controller lock.
582 */
583static void
584musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
585{
586 struct musb_request *r;
587 void __iomem *regs = musb->control_ep->regs;
588
589 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
590
591 /* NOTE: earlier 2.6 versions changed setup packets to host
592 * order, but now USB packets always stay in USB byte order.
593 */
594 dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
595 req->bRequestType,
596 req->bRequest,
597 le16_to_cpu(req->wValue),
598 le16_to_cpu(req->wIndex),
599 le16_to_cpu(req->wLength));
600
601 /* clean up any leftover transfers */
602 r = next_ep0_request(musb);
603 if (r)
604 musb_g_ep0_giveback(musb, &r->request);
605
606 /* For zero-data requests we want to delay the STATUS stage to
607 * avoid SETUPEND errors. If we read data (OUT), delay accepting
608 * packets until there's a buffer to store them in.
609 *
610 * If we write data, the controller acts happier if we enable
611 * the TX FIFO right away, and give the controller a moment
612 * to switch modes...
613 */
614 musb->set_address = false;
615 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
616 if (req->wLength == 0) {
617 if (req->bRequestType & USB_DIR_IN)
618 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
619 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
620 } else if (req->bRequestType & USB_DIR_IN) {
621 musb->ep0_state = MUSB_EP0_STAGE_TX;
622 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
623 while ((musb_readw(regs, MUSB_CSR0)
624 & MUSB_CSR0_RXPKTRDY) != 0)
625 cpu_relax();
626 musb->ackpend = 0;
627 } else
628 musb->ep0_state = MUSB_EP0_STAGE_RX;
629}
630
631static int
632forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
633__releases(musb->lock)
634__acquires(musb->lock)
635{
636 int retval;
637 if (!musb->gadget_driver)
638 return -EOPNOTSUPP;
639 spin_unlock(&musb->lock);
640 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
641 spin_lock(&musb->lock);
642 return retval;
643}
644
645/*
646 * Handle peripheral ep0 interrupt
647 *
648 * Context: irq handler; we won't re-enter the driver that way.
649 */
650irqreturn_t musb_g_ep0_irq(struct musb *musb)
651{
652 u16 csr;
653 u16 len;
654 void __iomem *mbase = musb->mregs;
655 void __iomem *regs = musb->endpoints[0].regs;
656 irqreturn_t retval = IRQ_NONE;
657
658 musb_ep_select(mbase, 0); /* select ep0 */
659 csr = musb_readw(regs, MUSB_CSR0);
660 len = musb_readb(regs, MUSB_COUNT0);
661
662 dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
663 csr, len,
664 musb_readb(mbase, MUSB_FADDR),
665 decode_ep0stage(musb->ep0_state));
666
667 if (csr & MUSB_CSR0_P_DATAEND) {
668 /*
669 * If DATAEND is set we should not call the callback,
670 * hence the status stage is not complete.
671 */
672 return IRQ_HANDLED;
673 }
674
675 /* I sent a stall.. need to acknowledge it now.. */
676 if (csr & MUSB_CSR0_P_SENTSTALL) {
677 musb_writew(regs, MUSB_CSR0,
678 csr & ~MUSB_CSR0_P_SENTSTALL);
679 retval = IRQ_HANDLED;
680 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
681 csr = musb_readw(regs, MUSB_CSR0);
682 }
683
684 /* request ended "early" */
685 if (csr & MUSB_CSR0_P_SETUPEND) {
686 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
687 retval = IRQ_HANDLED;
688 /* Transition into the early status phase */
689 switch (musb->ep0_state) {
690 case MUSB_EP0_STAGE_TX:
691 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
692 break;
693 case MUSB_EP0_STAGE_RX:
694 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
695 break;
696 default:
697 ERR("SetupEnd came in a wrong ep0stage %s\n",
698 decode_ep0stage(musb->ep0_state));
699 }
700 csr = musb_readw(regs, MUSB_CSR0);
701 /* NOTE: request may need completion */
702 }
703
704 /* docs from Mentor only describe tx, rx, and idle/setup states.
705 * we need to handle nuances around status stages, and also the
706 * case where status and setup stages come back-to-back ...
707 */
708 switch (musb->ep0_state) {
709
710 case MUSB_EP0_STAGE_TX:
711 /* irq on clearing txpktrdy */
712 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
713 ep0_txstate(musb);
714 retval = IRQ_HANDLED;
715 }
716 break;
717
718 case MUSB_EP0_STAGE_RX:
719 /* irq on set rxpktrdy */
720 if (csr & MUSB_CSR0_RXPKTRDY) {
721 ep0_rxstate(musb);
722 retval = IRQ_HANDLED;
723 }
724 break;
725
726 case MUSB_EP0_STAGE_STATUSIN:
727 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
728
729 /* update address (if needed) only @ the end of the
730 * status phase per usb spec, which also guarantees
731 * we get 10 msec to receive this irq... until this
732 * is done we won't see the next packet.
733 */
734 if (musb->set_address) {
735 musb->set_address = false;
736 musb_writeb(mbase, MUSB_FADDR, musb->address);
737 }
738
739 /* enter test mode if needed (exit by reset) */
740 else if (musb->test_mode) {
741 dev_dbg(musb->controller, "entering TESTMODE\n");
742
743 if (MUSB_TEST_PACKET == musb->test_mode_nr)
744 musb_load_testpacket(musb);
745
746 musb_writeb(mbase, MUSB_TESTMODE,
747 musb->test_mode_nr);
748 }
749 /* FALLTHROUGH */
750
751 case MUSB_EP0_STAGE_STATUSOUT:
752 /* end of sequence #1: write to host (TX state) */
753 {
754 struct musb_request *req;
755
756 req = next_ep0_request(musb);
757 if (req)
758 musb_g_ep0_giveback(musb, &req->request);
759 }
760
761 /*
762 * In case when several interrupts can get coalesced,
763 * check to see if we've already received a SETUP packet...
764 */
765 if (csr & MUSB_CSR0_RXPKTRDY)
766 goto setup;
767
768 retval = IRQ_HANDLED;
769 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
770 break;
771
772 case MUSB_EP0_STAGE_IDLE:
773 /*
774 * This state is typically (but not always) indiscernible
775 * from the status states since the corresponding interrupts
776 * tend to happen within too little period of time (with only
777 * a zero-length packet in between) and so get coalesced...
778 */
779 retval = IRQ_HANDLED;
780 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
781 /* FALLTHROUGH */
782
783 case MUSB_EP0_STAGE_SETUP:
784setup:
785 if (csr & MUSB_CSR0_RXPKTRDY) {
786 struct usb_ctrlrequest setup;
787 int handled = 0;
788
789 if (len != 8) {
790 ERR("SETUP packet len %d != 8 ?\n", len);
791 break;
792 }
793 musb_read_setup(musb, &setup);
794 retval = IRQ_HANDLED;
795
796 /* sometimes the RESET won't be reported */
797 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
798 u8 power;
799
800 printk(KERN_NOTICE "%s: peripheral reset "
801 "irq lost!\n",
802 musb_driver_name);
803 power = musb_readb(mbase, MUSB_POWER);
804 musb->g.speed = (power & MUSB_POWER_HSMODE)
805 ? USB_SPEED_HIGH : USB_SPEED_FULL;
806
807 }
808
809 switch (musb->ep0_state) {
810
811 /* sequence #3 (no data stage), includes requests
812 * we can't forward (notably SET_ADDRESS and the
813 * device/endpoint feature set/clear operations)
814 * plus SET_CONFIGURATION and others we must
815 */
816 case MUSB_EP0_STAGE_ACKWAIT:
817 handled = service_zero_data_request(
818 musb, &setup);
819
820 /*
821 * We're expecting no data in any case, so
822 * always set the DATAEND bit -- doing this
823 * here helps avoid SetupEnd interrupt coming
824 * in the idle stage when we're stalling...
825 */
826 musb->ackpend |= MUSB_CSR0_P_DATAEND;
827
828 /* status stage might be immediate */
829 if (handled > 0)
830 musb->ep0_state =
831 MUSB_EP0_STAGE_STATUSIN;
832 break;
833
834 /* sequence #1 (IN to host), includes GET_STATUS
835 * requests that we can't forward, GET_DESCRIPTOR
836 * and others that we must
837 */
838 case MUSB_EP0_STAGE_TX:
839 handled = service_in_request(musb, &setup);
840 if (handled > 0) {
841 musb->ackpend = MUSB_CSR0_TXPKTRDY
842 | MUSB_CSR0_P_DATAEND;
843 musb->ep0_state =
844 MUSB_EP0_STAGE_STATUSOUT;
845 }
846 break;
847
848 /* sequence #2 (OUT from host), always forward */
849 default: /* MUSB_EP0_STAGE_RX */
850 break;
851 }
852
853 dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
854 handled, csr,
855 decode_ep0stage(musb->ep0_state));
856
857 /* unless we need to delegate this to the gadget
858 * driver, we know how to wrap this up: csr0 has
859 * not yet been written.
860 */
861 if (handled < 0)
862 goto stall;
863 else if (handled > 0)
864 goto finish;
865
866 handled = forward_to_driver(musb, &setup);
867 if (handled < 0) {
868 musb_ep_select(mbase, 0);
869stall:
870 dev_dbg(musb->controller, "stall (%d)\n", handled);
871 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
872 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
873finish:
874 musb_writew(regs, MUSB_CSR0,
875 musb->ackpend);
876 musb->ackpend = 0;
877 }
878 }
879 break;
880
881 case MUSB_EP0_STAGE_ACKWAIT:
882 /* This should not happen. But happens with tusb6010 with
883 * g_file_storage and high speed. Do nothing.
884 */
885 retval = IRQ_HANDLED;
886 break;
887
888 default:
889 /* "can't happen" */
1058eec0 890 assert_noisy(false);
eb81955b
IY		 891 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
892 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
893 break;
894 }
895
896 return retval;
897}
898
899
900static int
901musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
902{
903 /* always enabled */
904 return -EINVAL;
905}
906
907static int musb_g_ep0_disable(struct usb_ep *e)
908{
909 /* always enabled */
910 return -EINVAL;
911}
912
913static int
914musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
915{
916 struct musb_ep *ep;
917 struct musb_request *req;
918 struct musb *musb;
919 int status;
920 unsigned long lockflags;
921 void __iomem *regs;
922
923 if (!e || !r)
924 return -EINVAL;
925
926 ep = to_musb_ep(e);
927 musb = ep->musb;
928 regs = musb->control_ep->regs;
929
930 req = to_musb_request(r);
931 req->musb = musb;
932 req->request.actual = 0;
933 req->request.status = -EINPROGRESS;
934 req->tx = ep->is_in;
935
936 spin_lock_irqsave(&musb->lock, lockflags);
937
938 if (!list_empty(&ep->req_list)) {
939 status = -EBUSY;
940 goto cleanup;
941 }
942
943 switch (musb->ep0_state) {
944 case MUSB_EP0_STAGE_RX: /* control-OUT data */
945 case MUSB_EP0_STAGE_TX: /* control-IN data */
946 case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
947 status = 0;
948 break;
949 default:
950 dev_dbg(musb->controller, "ep0 request queued in state %d\n",
951 musb->ep0_state);
952 status = -EINVAL;
953 goto cleanup;
954 }
955
956 /* add request to the list */
957 list_add_tail(&req->list, &ep->req_list);
958
959 dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
960 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
961 req->request.length);
962
963 musb_ep_select(musb->mregs, 0);
964
965 /* sequence #1, IN ... start writing the data */
966 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
967 ep0_txstate(musb);
968
969 /* sequence #3, no-data ... issue IN status */
970 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
971 if (req->request.length)
972 status = -EINVAL;
973 else {
974 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
975 musb_writew(regs, MUSB_CSR0,
976 musb->ackpend | MUSB_CSR0_P_DATAEND);
977 musb->ackpend = 0;
978 musb_g_ep0_giveback(ep->musb, r);
979 }
980
981 /* else for sequence #2 (OUT), caller provides a buffer
982 * before the next packet arrives. deferred responses
983 * (after SETUP is acked) are racey.
984 */
985 } else if (musb->ackpend) {
986 musb_writew(regs, MUSB_CSR0, musb->ackpend);
987 musb->ackpend = 0;
988 }
989
990cleanup:
991 spin_unlock_irqrestore(&musb->lock, lockflags);
992 return status;
993}
994
995static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
996{
997 /* we just won't support this */
998 return -EINVAL;
999}
1000
1001static int musb_g_ep0_halt(struct usb_ep *e, int value)
1002{
1003 struct musb_ep *ep;
1004 struct musb *musb;
1005 void __iomem *base, *regs;
1006 unsigned long flags;
1007 int status;
1008 u16 csr;
1009
1010 if (!e || !value)
1011 return -EINVAL;
1012
1013 ep = to_musb_ep(e);
1014 musb = ep->musb;
1015 base = musb->mregs;
1016 regs = musb->control_ep->regs;
1017 status = 0;
1018
1019 spin_lock_irqsave(&musb->lock, flags);
1020
1021 if (!list_empty(&ep->req_list)) {
1022 status = -EBUSY;
1023 goto cleanup;
1024 }
1025
1026 musb_ep_select(base, 0);
1027 csr = musb->ackpend;
1028
1029 switch (musb->ep0_state) {
1030
1031 /* Stalls are usually issued after parsing SETUP packet, either
1032 * directly in irq context from setup() or else later.
1033 */
1034 case MUSB_EP0_STAGE_TX: /* control-IN data */
1035 case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
1036 case MUSB_EP0_STAGE_RX: /* control-OUT data */
1037 csr = musb_readw(regs, MUSB_CSR0);
1038 /* FALLTHROUGH */
1039
1040 /* It's also OK to issue stalls during callbacks when a non-empty
1041 * DATA stage buffer has been read (or even written).
1042 */
1043 case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
1044 case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
1045
1046 csr |= MUSB_CSR0_P_SENDSTALL;
1047 musb_writew(regs, MUSB_CSR0, csr);
1048 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1049 musb->ackpend = 0;
1050 break;
1051 default:
1052 dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
1053 status = -EINVAL;
1054 }
1055
1056cleanup:
1057 spin_unlock_irqrestore(&musb->lock, flags);
1058 return status;
1059}
1060
1061const struct usb_ep_ops musb_g_ep0_ops = {
1062 .enable = musb_g_ep0_enable,
1063 .disable = musb_g_ep0_disable,
1064 .alloc_request = musb_alloc_request,
1065 .free_request = musb_free_request,
1066 .queue = musb_g_ep0_queue,
1067 .dequeue = musb_g_ep0_dequeue,
1068 .set_halt = musb_g_ep0_halt,
1069};
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