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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
6173c45b TR |
2 | /* |
3 | * Copyright (C) 2014 NVIDIA Corporation | |
6173c45b TR |
4 | */ |
5 | ||
6 | #define pr_fmt(fmt) "as3722: " fmt | |
7 | ||
8 | #include <common.h> | |
9 | #include <dm.h> | |
10 | #include <errno.h> | |
11 | #include <fdtdec.h> | |
12 | #include <i2c.h> | |
f7ae49fc | 13 | #include <log.h> |
e3f44f5c | 14 | #include <dm/lists.h> |
1e94b46f | 15 | #include <linux/printk.h> |
6173c45b | 16 | #include <power/as3722.h> |
e3f44f5c | 17 | #include <power/pmic.h> |
6173c45b | 18 | |
e3f44f5c | 19 | #define AS3722_NUM_OF_REGS 0x92 |
6173c45b | 20 | |
e3f44f5c | 21 | static int as3722_read(struct udevice *dev, uint reg, uint8_t *buff, int len) |
6173c45b | 22 | { |
e3f44f5c | 23 | int ret; |
6173c45b | 24 | |
e3f44f5c SG |
25 | ret = dm_i2c_read(dev, reg, buff, len); |
26 | if (ret < 0) | |
27 | return ret; | |
6173c45b TR |
28 | |
29 | return 0; | |
30 | } | |
31 | ||
e3f44f5c SG |
32 | static int as3722_write(struct udevice *dev, uint reg, const uint8_t *buff, |
33 | int len) | |
6173c45b | 34 | { |
e3f44f5c | 35 | int ret; |
6173c45b | 36 | |
e3f44f5c SG |
37 | ret = dm_i2c_write(dev, reg, buff, len); |
38 | if (ret < 0) | |
39 | return ret; | |
6173c45b TR |
40 | |
41 | return 0; | |
42 | } | |
43 | ||
e3f44f5c | 44 | static int as3722_read_id(struct udevice *dev, uint *idp, uint *revisionp) |
6173c45b | 45 | { |
e3f44f5c | 46 | int ret; |
6173c45b | 47 | |
e3f44f5c SG |
48 | ret = pmic_reg_read(dev, AS3722_ASIC_ID1); |
49 | if (ret < 0) { | |
c83c436d | 50 | pr_err("failed to read ID1 register: %d\n", ret); |
e3f44f5c | 51 | return ret; |
6173c45b | 52 | } |
e3f44f5c | 53 | *idp = ret; |
6173c45b | 54 | |
e3f44f5c SG |
55 | ret = pmic_reg_read(dev, AS3722_ASIC_ID2); |
56 | if (ret < 0) { | |
c83c436d | 57 | pr_err("failed to read ID2 register: %d\n", ret); |
e3f44f5c | 58 | return ret; |
6173c45b | 59 | } |
e3f44f5c | 60 | *revisionp = ret; |
6173c45b TR |
61 | |
62 | return 0; | |
63 | } | |
64 | ||
e3f44f5c SG |
65 | /* TODO([email protected]): Add proper regulator support to avoid this */ |
66 | int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value) | |
6173c45b | 67 | { |
e3f44f5c | 68 | int ret; |
6173c45b TR |
69 | |
70 | if (sd > 6) | |
71 | return -EINVAL; | |
72 | ||
e3f44f5c SG |
73 | ret = pmic_reg_write(dev, AS3722_SD_VOLTAGE(sd), value); |
74 | if (ret < 0) { | |
c83c436d | 75 | pr_err("failed to write SD%u voltage register: %d\n", sd, ret); |
e3f44f5c | 76 | return ret; |
6173c45b TR |
77 | } |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
e3f44f5c | 82 | int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value) |
6173c45b | 83 | { |
e3f44f5c | 84 | int ret; |
6173c45b TR |
85 | |
86 | if (ldo > 11) | |
87 | return -EINVAL; | |
88 | ||
e3f44f5c SG |
89 | ret = pmic_reg_write(dev, AS3722_LDO_VOLTAGE(ldo), value); |
90 | if (ret < 0) { | |
c83c436d SG |
91 | pr_err("failed to write LDO%u voltage register: %d\n", ldo, |
92 | ret); | |
e3f44f5c | 93 | return ret; |
6173c45b TR |
94 | } |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
e3f44f5c | 99 | static int as3722_probe(struct udevice *dev) |
6173c45b | 100 | { |
e3f44f5c SG |
101 | uint id, revision; |
102 | int ret; | |
6173c45b | 103 | |
e3f44f5c SG |
104 | ret = as3722_read_id(dev, &id, &revision); |
105 | if (ret < 0) { | |
c83c436d | 106 | pr_err("failed to read ID: %d\n", ret); |
e3f44f5c | 107 | return ret; |
6173c45b TR |
108 | } |
109 | ||
e3f44f5c | 110 | if (id != AS3722_DEVICE_ID) { |
c83c436d | 111 | pr_err("unknown device\n"); |
e3f44f5c | 112 | return -ENOENT; |
6173c45b TR |
113 | } |
114 | ||
e3f44f5c | 115 | debug("AS3722 revision %#x found on I2C bus %s\n", revision, dev->name); |
6173c45b TR |
116 | |
117 | return 0; | |
118 | } | |
119 | ||
e3f44f5c SG |
120 | #if CONFIG_IS_ENABLED(PMIC_CHILDREN) |
121 | static const struct pmic_child_info pmic_children_info[] = { | |
122 | { .prefix = "sd", .driver = "as3722_stepdown"}, | |
123 | { .prefix = "ldo", .driver = "as3722_ldo"}, | |
124 | { }, | |
125 | }; | |
6173c45b | 126 | |
e3f44f5c SG |
127 | static int as3722_bind(struct udevice *dev) |
128 | { | |
129 | struct udevice *gpio_dev; | |
130 | ofnode regulators_node; | |
131 | int children; | |
132 | int ret; | |
6173c45b | 133 | |
e3f44f5c SG |
134 | regulators_node = dev_read_subnode(dev, "regulators"); |
135 | if (!ofnode_valid(regulators_node)) { | |
136 | debug("%s: %s regulators subnode not found\n", __func__, | |
137 | dev->name); | |
138 | return -ENXIO; | |
6173c45b TR |
139 | } |
140 | ||
e3f44f5c SG |
141 | children = pmic_bind_children(dev, regulators_node, pmic_children_info); |
142 | if (!children) | |
143 | debug("%s: %s - no child found\n", __func__, dev->name); | |
144 | ret = device_bind_driver(dev, "gpio_as3722", "gpio_as3722", &gpio_dev); | |
145 | if (ret) { | |
146 | debug("%s: Cannot bind GPIOs (ret=%d)\n", __func__, ret); | |
147 | return ret; | |
6173c45b TR |
148 | } |
149 | ||
150 | return 0; | |
151 | } | |
e3f44f5c | 152 | #endif |
6173c45b | 153 | |
e3f44f5c | 154 | static int as3722_reg_count(struct udevice *dev) |
d55b7d4c | 155 | { |
e3f44f5c | 156 | return AS3722_NUM_OF_REGS; |
d55b7d4c SG |
157 | } |
158 | ||
e3f44f5c SG |
159 | static struct dm_pmic_ops as3722_ops = { |
160 | .reg_count = as3722_reg_count, | |
161 | .read = as3722_read, | |
162 | .write = as3722_write, | |
163 | }; | |
164 | ||
165 | static const struct udevice_id as3722_ids[] = { | |
166 | { .compatible = "ams,as3722" }, | |
167 | { } | |
168 | }; | |
169 | ||
170 | U_BOOT_DRIVER(pmic_as3722) = { | |
171 | .name = "as3722_pmic", | |
172 | .id = UCLASS_PMIC, | |
173 | .of_match = as3722_ids, | |
174 | #if CONFIG_IS_ENABLED(PMIC_CHILDREN) | |
175 | .bind = as3722_bind, | |
176 | #endif | |
177 | .probe = as3722_probe, | |
178 | .ops = &as3722_ops, | |
179 | }; |