[J-u-boot.git] / drivers / usb / host / ehci-mx6.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2009 Daniel Mack <[email protected]>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <usb.h>
#include <errno.h>
#include <wait_bit.h>
#include <linux/compiler.h>
#include <usb/ehci-ci.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sys_proto.h>
#include <dm.h>
#include <asm/mach-types.h>
#include <power/regulator.h>
#include <linux/usb/otg.h>

#include "ehci.h"

DECLARE_GLOBAL_DATA_PTR;

#define USB_OTGREGS_OFFSET	0x000
#define USB_H1REGS_OFFSET	0x200
#define USB_H2REGS_OFFSET	0x400
#define USB_H3REGS_OFFSET	0x600
#define USB_OTHERREGS_OFFSET	0x800

#define USB_H1_CTRL_OFFSET	0x04

#define USBPHY_CTRL				0x00000030
#define USBPHY_CTRL_SET				0x00000034
#define USBPHY_CTRL_CLR				0x00000038
#define USBPHY_CTRL_TOG				0x0000003c

#define USBPHY_PWD				0x00000000
#define USBPHY_CTRL_SFTRST			0x80000000
#define USBPHY_CTRL_CLKGATE			0x40000000
#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
#define USBPHY_CTRL_OTG_ID			0x08000000

#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000

#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040

#define USBNC_OFFSET		0x200
#define USBNC_PHY_STATUS_OFFSET	0x23C
#define USBNC_PHYSTATUS_ID_DIG	(1 << 4) /* otg_id status */
#define USBNC_PHYCFG2_ACAENB	(1 << 4) /* otg_id detection enable */
#define UCTRL_PWR_POL		(1 << 9) /* OTG Polarity of Power Pin */
#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */

/* USBCMD */
#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
#define UCMD_RESET		(1 << 1) /* controller reset */

#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
static const unsigned phy_bases[] = {
	USB_PHY0_BASE_ADDR,
#if defined(USB_PHY1_BASE_ADDR)
	USB_PHY1_BASE_ADDR,
#endif
};

static void usb_internal_phy_clock_gate(int index, int on)
{
	void __iomem *phy_reg;

	if (index >= ARRAY_SIZE(phy_bases))
		return;

	phy_reg = (void __iomem *)phy_bases[index];
	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
	writel(USBPHY_CTRL_CLKGATE, phy_reg);
}

static void usb_power_config(int index)
{
#if defined(CONFIG_MX7ULP)
	struct usbphy_regs __iomem *usbphy =
		(struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;

	if (index > 0)
		return;

	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
		   ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
		   &usbphy->usb1_chrg_detect);

	scg_enable_usb_pll(true);

#else
	struct anatop_regs __iomem *anatop =
		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
	void __iomem *chrg_detect;
	void __iomem *pll_480_ctrl_clr;
	void __iomem *pll_480_ctrl_set;

	switch (index) {
	case 0:
		chrg_detect = &anatop->usb1_chrg_detect;
		pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
		pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
		break;
	case 1:
		chrg_detect = &anatop->usb2_chrg_detect;
		pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
		pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
		break;
	default:
		return;
	}
	/*
	 * Some phy and power's special controls
	 * 1. The external charger detector needs to be disabled
	 * or the signal at DP will be poor
	 * 2. The PLL's power and output to usb
	 * is totally controlled by IC, so the Software only needs
	 * to enable them at initializtion.
	 */
	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
		     chrg_detect);

	writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
		     pll_480_ctrl_clr);

	writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
		     ANADIG_USB2_PLL_480_CTRL_POWER |
		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
		     pll_480_ctrl_set);

#endif
}

/* Return 0 : host node, <>0 : device mode */
static int usb_phy_enable(int index, struct usb_ehci *ehci)
{
	void __iomem *phy_reg;
	void __iomem *phy_ctrl;
	void __iomem *usb_cmd;
	int ret;

	if (index >= ARRAY_SIZE(phy_bases))
		return 0;

	phy_reg = (void __iomem *)phy_bases[index];
	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
	usb_cmd = (void __iomem *)&ehci->usbcmd;

	/* Stop then Reset */
	clrbits_le32(usb_cmd, UCMD_RUN_STOP);
	ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
	if (ret)
		return ret;

	setbits_le32(usb_cmd, UCMD_RESET);
	ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
	if (ret)
		return ret;

	/* Reset USBPHY module */
	setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
	udelay(10);

	/* Remove CLKGATE and SFTRST */
	clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
	udelay(10);

	/* Power up the PHY */
	writel(0, phy_reg + USBPHY_PWD);
	/* enable FS/LS device */
	setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
			USBPHY_CTRL_ENUTMILEVEL3);

	return 0;
}

int usb_phy_mode(int port)
{
	void __iomem *phy_reg;
	void __iomem *phy_ctrl;
	u32 val;

	phy_reg = (void __iomem *)phy_bases[port];
	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);

	val = readl(phy_ctrl);

	if (val & USBPHY_CTRL_OTG_ID)
		return USB_INIT_DEVICE;
	else
		return USB_INIT_HOST;
}

#if defined(CONFIG_MX7ULP)
struct usbnc_regs {
	u32 ctrl1;
	u32 ctrl2;
	u32 reserve0[2];
	u32 hsic_ctrl;
};
#else
/* Base address for this IP block is 0x02184800 */
struct usbnc_regs {
	u32	ctrl[4];	/* otg/host1-3 */
	u32	uh2_hsic_ctrl;
	u32	uh3_hsic_ctrl;
	u32	otg_phy_ctrl_0;
	u32	uh1_phy_ctrl_0;
};
#endif

#elif defined(CONFIG_MX7)
struct usbnc_regs {
	u32 ctrl1;
	u32 ctrl2;
	u32 reserve1[10];
	u32 phy_cfg1;
	u32 phy_cfg2;
	u32 reserve2;
	u32 phy_status;
	u32 reserve3[4];
	u32 adp_cfg1;
	u32 adp_cfg2;
	u32 adp_status;
};

static void usb_power_config(int index)
{
	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
			(0x10000 * index) + USBNC_OFFSET);
	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);

	/*
	 * Clear the ACAENB to enable usb_otg_id detection,
	 * otherwise it is the ACA detection enabled.
	 */
	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
}

int usb_phy_mode(int port)
{
	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
			(0x10000 * port) + USBNC_OFFSET);
	void __iomem *status = (void __iomem *)(&usbnc->phy_status);
	u32 val;

	val = readl(status);

	if (val & USBNC_PHYSTATUS_ID_DIG)
		return USB_INIT_DEVICE;
	else
		return USB_INIT_HOST;
}
#endif

static void usb_oc_config(int index)
{
#if defined(CONFIG_MX6)
	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
			USB_OTHERREGS_OFFSET);
	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
			(0x10000 * index) + USBNC_OFFSET);
	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
#endif

#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
	/* mx6qarm2 seems to required a different setting*/
	clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#else
	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#endif

	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);

	/* Set power polarity to high active */
#ifdef CONFIG_MXC_USB_OTG_HACTIVE
	setbits_le32(ctrl, UCTRL_PWR_POL);
#else
	clrbits_le32(ctrl, UCTRL_PWR_POL);
#endif
}

/**
 * board_usb_phy_mode - override usb phy mode
 * @port:	usb host/otg port
 *
 * Target board specific, override usb_phy_mode.
 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
 * left disconnected in this case usb_phy_mode will not be able to identify
 * the phy mode that usb port is used.
 * Machine file overrides board_usb_phy_mode.
 *
 * Return: USB_INIT_DEVICE or USB_INIT_HOST
 */
int __weak board_usb_phy_mode(int port)
{
	return usb_phy_mode(port);
}

/**
 * board_ehci_hcd_init - set usb vbus voltage
 * @port:      usb otg port
 *
 * Target board specific, setup iomux pad to setup supply vbus voltage
 * for usb otg port. Machine board file overrides board_ehci_hcd_init
 *
 * Return: 0 Success
 */
int __weak board_ehci_hcd_init(int port)
{
	return 0;
}

/**
 * board_ehci_power - enables/disables usb vbus voltage
 * @port:      usb otg port
 * @on:        on/off vbus voltage
 *
 * Enables/disables supply vbus voltage for usb otg port.
 * Machine board file overrides board_ehci_power
 *
 * Return: 0 Success
 */
int __weak board_ehci_power(int port, int on)
{
	return 0;
}

int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
{
	int ret;

	enable_usboh3_clk(1);
	mdelay(1);

	/* Do board specific initialization */
	ret = board_ehci_hcd_init(index);
	if (ret)
		return ret;

	usb_power_config(index);
	usb_oc_config(index);

#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
	usb_internal_phy_clock_gate(index, 1);
	usb_phy_enable(index, ehci);
#endif

	return 0;
}

#if !CONFIG_IS_ENABLED(DM_USB)
int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	enum usb_init_type type;
#if defined(CONFIG_MX6)
	u32 controller_spacing = 0x200;
#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
	u32 controller_spacing = 0x10000;
#endif
	struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
		(controller_spacing * index));
	int ret;

	if (index > 3)
		return -EINVAL;

	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
		if (usb_fused((ulong)ehci)) {
			printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
			       (ulong)ehci);
			return	-ENODEV;
		}
	}

	ret = ehci_mx6_common_init(ehci, index);
	if (ret)
		return ret;

	type = board_usb_phy_mode(index);

	if (hccr && hcor) {
		*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
		*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
				HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	}

	if ((type == init) || (type == USB_INIT_DEVICE))
		board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
	if (type != init)
		return -ENODEV;
	if (type == USB_INIT_DEVICE)
		return 0;

	setbits_le32(&ehci->usbmode, CM_HOST);
	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mdelay(10);

	return 0;
}

int ehci_hcd_stop(int index)
{
	return 0;
}
#else
struct ehci_mx6_priv_data {
	struct ehci_ctrl ctrl;
	struct usb_ehci *ehci;
	struct udevice *vbus_supply;
	enum usb_init_type init_type;
	int portnr;
};

static int mx6_init_after_reset(struct ehci_ctrl *dev)
{
	struct ehci_mx6_priv_data *priv = dev->priv;
	enum usb_init_type type = priv->init_type;
	struct usb_ehci *ehci = priv->ehci;
	int ret;

	ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
	if (ret)
		return ret;

#if CONFIG_IS_ENABLED(DM_REGULATOR)
	if (priv->vbus_supply) {
		ret = regulator_set_enable(priv->vbus_supply,
					   (type == USB_INIT_DEVICE) ?
					   false : true);
		if (ret) {
			puts("Error enabling VBUS supply\n");
			return ret;
		}
	}
#endif

	if (type == USB_INIT_DEVICE)
		return 0;

	setbits_le32(&ehci->usbmode, CM_HOST);
	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mdelay(10);

	return 0;
}

static const struct ehci_ops mx6_ehci_ops = {
	.init_after_reset = mx6_init_after_reset
};

static int ehci_usb_phy_mode(struct udevice *dev)
{
	struct usb_platdata *plat = dev_get_platdata(dev);
	void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
	void *__iomem phy_ctrl, *__iomem phy_status;
	const void *blob = gd->fdt_blob;
	int offset = dev_of_offset(dev), phy_off;
	u32 val;

	/*
	 * About fsl,usbphy, Refer to
	 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
	 */
	if (is_mx6() || is_mx7ulp()) {
		phy_off = fdtdec_lookup_phandle(blob,
						offset,
						"fsl,usbphy");
		if (phy_off < 0)
			return -EINVAL;

		addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
						       "reg");
		if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
			return -EINVAL;

		phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
		val = readl(phy_ctrl);

		if (val & USBPHY_CTRL_OTG_ID)
			plat->init_type = USB_INIT_DEVICE;
		else
			plat->init_type = USB_INIT_HOST;
	} else if (is_mx7()) {
		phy_status = (void __iomem *)(addr +
					      USBNC_PHY_STATUS_OFFSET);
		val = readl(phy_status);

		if (val & USBNC_PHYSTATUS_ID_DIG)
			plat->init_type = USB_INIT_DEVICE;
		else
			plat->init_type = USB_INIT_HOST;
	} else {
		return -EINVAL;
	}

	return 0;
}

static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
{
	struct usb_platdata *plat = dev_get_platdata(dev);
	enum usb_dr_mode dr_mode;

	dr_mode = usb_get_dr_mode(dev->node);

	switch (dr_mode) {
	case USB_DR_MODE_HOST:
		plat->init_type = USB_INIT_HOST;
		break;
	case USB_DR_MODE_PERIPHERAL:
		plat->init_type = USB_INIT_DEVICE;
		break;
	case USB_DR_MODE_OTG:
	case USB_DR_MODE_UNKNOWN:
		return ehci_usb_phy_mode(dev);
	};

	return 0;
}

static int ehci_usb_bind(struct udevice *dev)
{
	/*
	 * TODO:
	 * This driver is only partly converted to DT probing and still uses
	 * a tremendous amount of hard-coded addresses. To make things worse,
	 * the driver depends on specific sequential indexing of controllers,
	 * from which it derives offsets in the PHY and ANATOP register sets.
	 *
	 * Here we attempt to calculate these indexes from DT information as
	 * well as we can. The USB controllers on all existing iMX6 SoCs
	 * are placed next to each other, at addresses incremented by 0x200,
	 * and iMX7 their addresses are shifted by 0x10000.
	 * Thus, the index is derived from the multiple of 0x200 (0x10000 for
	 * iMX7) offset from the first controller address.
	 *
	 * However, to complete conversion of this driver to DT probing, the
	 * following has to be done:
	 * - DM clock framework support for iMX must be implemented
	 * - usb_power_config() has to be converted to clock framework
	 *   -> Thus, the ad-hoc "index" variable goes away.
	 * - USB PHY handling has to be factored out into separate driver
	 *   -> Thus, the ad-hoc "index" variable goes away from the PHY
	 *      code, the PHY driver must parse it's address from DT. This
	 *      USB driver must find the PHY driver via DT phandle.
	 *   -> usb_power_config() shall be moved to PHY driver
	 * With these changes in place, the ad-hoc indexing goes away and
	 * the driver is fully converted to DT probing.
	 */
	u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
	fdt_addr_t addr = devfdt_get_addr_index(dev, 0);

	dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;

	return 0;
}

static int ehci_usb_probe(struct udevice *dev)
{
	struct usb_platdata *plat = dev_get_platdata(dev);
	struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
	struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
	enum usb_init_type type = plat->init_type;
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;
	int ret;

	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
		if (usb_fused((ulong)ehci)) {
			printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
			       (ulong)ehci);
			return -ENODEV;
		}
	}

	priv->ehci = ehci;
	priv->portnr = dev->seq;
	priv->init_type = type;

#if CONFIG_IS_ENABLED(DM_REGULATOR)
	ret = device_get_supply_regulator(dev, "vbus-supply",
					  &priv->vbus_supply);
	if (ret)
		debug("%s: No vbus supply\n", dev->name);
#endif
	ret = ehci_mx6_common_init(ehci, priv->portnr);
	if (ret)
		return ret;

#if CONFIG_IS_ENABLED(DM_REGULATOR)
	if (priv->vbus_supply) {
		ret = regulator_set_enable(priv->vbus_supply,
					   (type == USB_INIT_DEVICE) ?
					   false : true);
		if (ret) {
			puts("Error enabling VBUS supply\n");
			return ret;
		}
	}
#endif

	if (priv->init_type == USB_INIT_HOST) {
		setbits_le32(&ehci->usbmode, CM_HOST);
		writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
		setbits_le32(&ehci->portsc, USB_EN);
	}

	mdelay(10);

	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	hcor = (struct ehci_hcor *)((uint32_t)hccr +
			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));

	return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
}

static const struct udevice_id mx6_usb_ids[] = {
	{ .compatible = "fsl,imx27-usb" },
	{ }
};

U_BOOT_DRIVER(usb_mx6) = {
	.name	= "ehci_mx6",
	.id	= UCLASS_USB,
	.of_match = mx6_usb_ids,
	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
	.bind	= ehci_usb_bind,
	.probe	= ehci_usb_probe,
	.remove = ehci_deregister,
	.ops	= &ehci_usb_ops,
	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
	.priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
3f467529 WG	2	/*
	3	* Copyright (c) 2009 Daniel Mack <[email protected]>
	4	* Copyright (C) 2010 Freescale Semiconductor, Inc.
3f467529 WG	5	*/
	6
	7	#include <common.h>
	8	#include <usb.h>
	9	#include <errno.h>
8c25c259	10	#include <wait_bit.h>
3f467529	11	#include <linux/compiler.h>
e162c6b1	12	#include <usb/ehci-ci.h>
3f467529 WG	13	#include <asm/io.h>
	14	#include <asm/arch/imx-regs.h>
	15	#include <asm/arch/clock.h>
552a848e SB	16	#include <asm/mach-imx/iomux-v3.h>
552a848e SB	17	#include <asm/mach-imx/sys_proto.h>
bb42fb4f	18	#include <dm.h>
c62db35d	19	#include <asm/mach-types.h>
fcf9f9f9	20	#include <power/regulator.h>
69535b33	21	#include <linux/usb/otg.h>
3f467529 WG	22
3f467529 WG	23	#include "ehci.h"
3f467529	24
cccbddc3 PF	25	DECLARE_GLOBAL_DATA_PTR;
cccbddc3 PF	26
3f467529 WG	27	#define USB_OTGREGS_OFFSET 0x000
	28	#define USB_H1REGS_OFFSET 0x200
	29	#define USB_H2REGS_OFFSET 0x400
	30	#define USB_H3REGS_OFFSET 0x600
	31	#define USB_OTHERREGS_OFFSET 0x800
	32
	33	#define USB_H1_CTRL_OFFSET 0x04
	34
	35	#define USBPHY_CTRL 0x00000030
	36	#define USBPHY_CTRL_SET 0x00000034
	37	#define USBPHY_CTRL_CLR 0x00000038
	38	#define USBPHY_CTRL_TOG 0x0000003c
	39
	40	#define USBPHY_PWD 0x00000000
	41	#define USBPHY_CTRL_SFTRST 0x80000000
	42	#define USBPHY_CTRL_CLKGATE 0x40000000
	43	#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
	44	#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
d1a52860	45	#define USBPHY_CTRL_OTG_ID 0x08000000
3f467529	46
3f467529 WG	47	#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
	48	#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
	49
3f467529 WG	50	#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
	51	#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
	52	#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
	53	#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
	54
35554fc9	55	#define USBNC_OFFSET 0x200
cccbddc3	56	#define USBNC_PHY_STATUS_OFFSET 0x23C
35554fc9 AA	57	#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
35554fc9 AA	58	#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
9a88180b	59	#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
3f467529 WG	60	#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
	61	#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
	62
	63	/* USBCMD */
3f467529 WG	64	#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
	65	#define UCMD_RESET (1 << 1) /* controller reset */
	66
235f5e15	67	#if defined(CONFIG_MX6) \|\| defined(CONFIG_MX7ULP)
d1a52860 TK	68	static const unsigned phy_bases[] = {
d1a52860 TK	69	USB_PHY0_BASE_ADDR,
235f5e15	70	#if defined(USB_PHY1_BASE_ADDR)
d1a52860	71	USB_PHY1_BASE_ADDR,
235f5e15	72	#endif
d1a52860 TK	73	};
	74
	75	static void usb_internal_phy_clock_gate(int index, int on)
3f467529	76	{
d1a52860 TK	77	void __iomem *phy_reg;
	78
	79	if (index >= ARRAY_SIZE(phy_bases))
	80	return;
3f467529	81
d1a52860	82	phy_reg = (void __iomem *)phy_bases[index];
3f467529	83	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
e38ff30a	84	writel(USBPHY_CTRL_CLKGATE, phy_reg);
3f467529 WG	85	}
3f467529 WG	86
d1a52860	87	static void usb_power_config(int index)
3f467529	88	{
235f5e15 YL	89	#if defined(CONFIG_MX7ULP)
	90	struct usbphy_regs __iomem *usbphy =
	91	(struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
	92
	93	if (index > 0)
	94	return;
	95
	96	writel(ANADIG_USB2_CHRG_DETECT_EN_B \|
	97	ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
	98	&usbphy->usb1_chrg_detect);
	99
	100	scg_enable_usb_pll(true);
	101
	102	#else
3f29d962 WG	103	struct anatop_regs __iomem *anatop =
3f29d962 WG	104	(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
d1a52860 TK	105	void __iomem *chrg_detect;
	106	void __iomem *pll_480_ctrl_clr;
	107	void __iomem *pll_480_ctrl_set;
	108
	109	switch (index) {
	110	case 0:
	111	chrg_detect = &anatop->usb1_chrg_detect;
	112	pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
	113	pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
	114	break;
	115	case 1:
	116	chrg_detect = &anatop->usb2_chrg_detect;
	117	pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
	118	pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
	119	break;
	120	default:
	121	return;
	122	}
3f467529	123	/*
d1a52860	124	* Some phy and power's special controls
3f467529 WG	125	* 1. The external charger detector needs to be disabled
3f467529 WG	126	* or the signal at DP will be poor
d1a52860	127	* 2. The PLL's power and output to usb
3f467529 WG	128	* is totally controlled by IC, so the Software only needs
	129	* to enable them at initializtion.
	130	*/
e38ff30a	131	writel(ANADIG_USB2_CHRG_DETECT_EN_B \|
3f467529	132	ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
d1a52860	133	chrg_detect);
3f467529	134
e38ff30a	135	writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
d1a52860	136	pll_480_ctrl_clr);
3f467529	137
e38ff30a	138	writel(ANADIG_USB2_PLL_480_CTRL_ENABLE \|
3f467529 WG	139	ANADIG_USB2_PLL_480_CTRL_POWER \|
3f467529 WG	140	ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
d1a52860	141	pll_480_ctrl_set);
235f5e15 YL	142
235f5e15 YL	143	#endif
3f467529 WG	144	}
3f467529 WG	145
d1a52860 TK	146	/* Return 0 : host node, <>0 : device mode */
d1a52860 TK	147	static int usb_phy_enable(int index, struct usb_ehci *ehci)
3f467529	148	{
d1a52860 TK	149	void __iomem *phy_reg;
	150	void __iomem *phy_ctrl;
	151	void __iomem *usb_cmd;
f0c89d54	152	int ret;
3f467529	153
d1a52860 TK	154	if (index >= ARRAY_SIZE(phy_bases))
	155	return 0;
	156
	157	phy_reg = (void __iomem *)phy_bases[index];
	158	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
	159	usb_cmd = (void __iomem *)&ehci->usbcmd;
	160
3f467529	161	/* Stop then Reset */
e38ff30a	162	clrbits_le32(usb_cmd, UCMD_RUN_STOP);
48263504	163	ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
f0c89d54 AA	164	if (ret)
f0c89d54 AA	165	return ret;
3f467529	166
e38ff30a	167	setbits_le32(usb_cmd, UCMD_RESET);
48263504	168	ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
f0c89d54 AA	169	if (ret)
f0c89d54 AA	170	return ret;
3f467529 WG	171
3f467529 WG	172	/* Reset USBPHY module */
e38ff30a	173	setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
3f467529 WG	174	udelay(10);
	175
	176	/* Remove CLKGATE and SFTRST */
e38ff30a	177	clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE \| USBPHY_CTRL_SFTRST);
3f467529 WG	178	udelay(10);
	179
	180	/* Power up the PHY */
e38ff30a	181	writel(0, phy_reg + USBPHY_PWD);
3f467529	182	/* enable FS/LS device */
e38ff30a AA	183	setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 \|
e38ff30a AA	184	USBPHY_CTRL_ENUTMILEVEL3);
3f467529	185
229dbba9	186	return 0;
3f467529 WG	187	}
3f467529 WG	188
35554fc9 AA	189	int usb_phy_mode(int port)
	190	{
	191	void __iomem *phy_reg;
	192	void __iomem *phy_ctrl;
	193	u32 val;
	194
	195	phy_reg = (void __iomem *)phy_bases[port];
	196	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
	197
	198	val = readl(phy_ctrl);
	199
	200	if (val & USBPHY_CTRL_OTG_ID)
	201	return USB_INIT_DEVICE;
	202	else
	203	return USB_INIT_HOST;
	204	}
	205
235f5e15 YL	206	#if defined(CONFIG_MX7ULP)
	207	struct usbnc_regs {
	208	u32 ctrl1;
	209	u32 ctrl2;
	210	u32 reserve0[2];
	211	u32 hsic_ctrl;
	212	};
	213	#else
d1a52860 TK	214	/* Base address for this IP block is 0x02184800 */
	215	struct usbnc_regs {
	216	u32 ctrl[4]; /* otg/host1-3 */
	217	u32 uh2_hsic_ctrl;
	218	u32 uh3_hsic_ctrl;
	219	u32 otg_phy_ctrl_0;
	220	u32 uh1_phy_ctrl_0;
	221	};
235f5e15 YL	222	#endif
235f5e15 YL	223
35554fc9 AA	224	#elif defined(CONFIG_MX7)
	225	struct usbnc_regs {
	226	u32 ctrl1;
	227	u32 ctrl2;
	228	u32 reserve1[10];
	229	u32 phy_cfg1;
	230	u32 phy_cfg2;
429ff447	231	u32 reserve2;
35554fc9	232	u32 phy_status;
429ff447	233	u32 reserve3[4];
35554fc9 AA	234	u32 adp_cfg1;
	235	u32 adp_cfg2;
	236	u32 adp_status;
	237	};
	238
	239	static void usb_power_config(int index)
	240	{
	241	struct usbnc_regs usbnc = (struct usbnc_regs )(USB_BASE_ADDR +
	242	(0x10000 * index) + USBNC_OFFSET);
	243	void __iomem phy_cfg2 = (void __iomem )(&usbnc->phy_cfg2);
	244
57de41e9 PF	245	/*
	246	* Clear the ACAENB to enable usb_otg_id detection,
	247	* otherwise it is the ACA detection enabled.
	248	*/
	249	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
35554fc9 AA	250	}
	251
	252	int usb_phy_mode(int port)
	253	{
	254	struct usbnc_regs usbnc = (struct usbnc_regs )(USB_BASE_ADDR +
	255	(0x10000 * port) + USBNC_OFFSET);
	256	void __iomem status = (void __iomem )(&usbnc->phy_status);
	257	u32 val;
	258
	259	val = readl(status);
	260
	261	if (val & USBNC_PHYSTATUS_ID_DIG)
	262	return USB_INIT_DEVICE;
	263	else
	264	return USB_INIT_HOST;
	265	}
	266	#endif
d1a52860 TK	267
d1a52860 TK	268	static void usb_oc_config(int index)
3f467529	269	{
35554fc9	270	#if defined(CONFIG_MX6)
5546ad07	271	struct usbnc_regs usbnc = (struct usbnc_regs )(USB_BASE_ADDR +
d1a52860 TK	272	USB_OTHERREGS_OFFSET);
d1a52860 TK	273	void __iomem ctrl = (void __iomem )(&usbnc->ctrl[index]);
235f5e15	274	#elif defined(CONFIG_MX7) \|\| defined(CONFIG_MX7ULP)
35554fc9 AA	275	struct usbnc_regs usbnc = (struct usbnc_regs )(USB_BASE_ADDR +
	276	(0x10000 * index) + USBNC_OFFSET);
	277	void __iomem ctrl = (void __iomem )(&usbnc->ctrl1);
	278	#endif
3f467529	279
3f467529 WG	280	#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
3f467529 WG	281	/* mx6qarm2 seems to required a different setting*/
e38ff30a	282	clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
3f467529	283	#else
e38ff30a	284	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
3f467529	285	#endif
3f467529	286
e38ff30a	287	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
235f5e15 YL	288
	289	/* Set power polarity to high active */
	290	#ifdef CONFIG_MXC_USB_OTG_HACTIVE
	291	setbits_le32(ctrl, UCTRL_PWR_POL);
	292	#else
	293	clrbits_le32(ctrl, UCTRL_PWR_POL);
	294	#endif
229dbba9 PF	295	}
229dbba9 PF	296
74f0610e	297	/**
79d867c2	298	* board_usb_phy_mode - override usb phy mode
74f0610e AA	299	* @port: usb host/otg port
	300	*
	301	* Target board specific, override usb_phy_mode.
	302	* When usb-otg is used as usb host port, iomux pad usb_otg_id can be
	303	* left disconnected in this case usb_phy_mode will not be able to identify
	304	* the phy mode that usb port is used.
	305	* Machine file overrides board_usb_phy_mode.
	306	*
	307	* Return: USB_INIT_DEVICE or USB_INIT_HOST
	308	*/
229dbba9 PF	309	int __weak board_usb_phy_mode(int port)
	310	{
	311	return usb_phy_mode(port);
	312	}
	313
74f0610e AA	314	/**
	315	* board_ehci_hcd_init - set usb vbus voltage
	316	* @port: usb otg port
	317	*
	318	* Target board specific, setup iomux pad to setup supply vbus voltage
	319	* for usb otg port. Machine board file overrides board_ehci_hcd_init
	320	*
	321	* Return: 0 Success
	322	*/
f22e4fae BT	323	int __weak board_ehci_hcd_init(int port)
	324	{
	325	return 0;
	326	}
	327
74f0610e AA	328	/**
	329	* board_ehci_power - enables/disables usb vbus voltage
	330	* @port: usb otg port
	331	* @on: on/off vbus voltage
	332	*
	333	* Enables/disables supply vbus voltage for usb otg port.
	334	* Machine board file overrides board_ehci_power
	335	*
	336	* Return: 0 Success
	337	*/
d1a52860 TK	338	int __weak board_ehci_power(int port, int on)
	339	{
	340	return 0;
	341	}
	342
bb42fb4f PF	343	int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
	344	{
	345	int ret;
	346
	347	enable_usboh3_clk(1);
	348	mdelay(1);
	349
	350	/* Do board specific initialization */
	351	ret = board_ehci_hcd_init(index);
	352	if (ret)
	353	return ret;
	354
	355	usb_power_config(index);
	356	usb_oc_config(index);
	357
235f5e15	358	#if defined(CONFIG_MX6) \|\| defined(CONFIG_MX7ULP)
bb42fb4f PF	359	usb_internal_phy_clock_gate(index, 1);
	360	usb_phy_enable(index, ehci);
	361	#endif
	362
	363	return 0;
	364	}
	365
fd09c205	366	#if !CONFIG_IS_ENABLED(DM_USB)
127efc4f TK	367	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	368	struct ehci_hccr hccr, struct ehci_hcor hcor)
3f467529	369	{
d1a52860	370	enum usb_init_type type;
35554fc9 AA	371	#if defined(CONFIG_MX6)
35554fc9 AA	372	u32 controller_spacing = 0x200;
235f5e15	373	#elif defined(CONFIG_MX7) \|\| defined(CONFIG_MX7ULP)
35554fc9 AA	374	u32 controller_spacing = 0x10000;
35554fc9 AA	375	#endif
5546ad07	376	struct usb_ehci ehci = (struct usb_ehci )(USB_BASE_ADDR +
35554fc9	377	(controller_spacing * index));
79d867c2	378	int ret;
3f467529	379
d1a52860 TK	380	if (index > 3)
d1a52860 TK	381	return -EINVAL;
3f467529	382
0bd3d911 PF	383	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
	384	if (usb_fused((ulong)ehci)) {
	385	printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
	386	(ulong)ehci);
	387	return -ENODEV;
	388	}
	389	}
	390
bb42fb4f	391	ret = ehci_mx6_common_init(ehci, index);
79d867c2 SA	392	if (ret)
79d867c2 SA	393	return ret;
d1a52860	394
229dbba9	395	type = board_usb_phy_mode(index);
3f467529	396
bb42fb4f PF	397	if (hccr && hcor) {
	398	hccr = (struct ehci_hccr )((uint32_t)&ehci->caplength);
	399	hcor = (struct ehci_hcor )((uint32_t)*hccr +
	400	HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	401	}
3f467529	402
d1a52860 TK	403	if ((type == init) \|\| (type == USB_INIT_DEVICE))
	404	board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
	405	if (type != init)
	406	return -ENODEV;
	407	if (type == USB_INIT_DEVICE)
	408	return 0;
35554fc9	409
d1a52860	410	setbits_le32(&ehci->usbmode, CM_HOST);
e38ff30a	411	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
3f467529 WG	412	setbits_le32(&ehci->portsc, USB_EN);
	413
	414	mdelay(10);
	415
	416	return 0;
	417	}
	418
676ae068	419	int ehci_hcd_stop(int index)
3f467529 WG	420	{
	421	return 0;
	422	}
bb42fb4f PF	423	#else
	424	struct ehci_mx6_priv_data {
	425	struct ehci_ctrl ctrl;
	426	struct usb_ehci *ehci;
fcf9f9f9	427	struct udevice *vbus_supply;
bb42fb4f PF	428	enum usb_init_type init_type;
	429	int portnr;
	430	};
	431
	432	static int mx6_init_after_reset(struct ehci_ctrl *dev)
	433	{
	434	struct ehci_mx6_priv_data *priv = dev->priv;
	435	enum usb_init_type type = priv->init_type;
	436	struct usb_ehci *ehci = priv->ehci;
	437	int ret;
	438
	439	ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
	440	if (ret)
	441	return ret;
	442
921208eb	443	#if CONFIG_IS_ENABLED(DM_REGULATOR)
fcf9f9f9 PF	444	if (priv->vbus_supply) {
	445	ret = regulator_set_enable(priv->vbus_supply,
	446	(type == USB_INIT_DEVICE) ?
	447	false : true);
	448	if (ret) {
	449	puts("Error enabling VBUS supply\n");
	450	return ret;
	451	}
	452	}
921208eb	453	#endif
bb42fb4f PF	454
	455	if (type == USB_INIT_DEVICE)
	456	return 0;
	457
	458	setbits_le32(&ehci->usbmode, CM_HOST);
	459	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	460	setbits_le32(&ehci->portsc, USB_EN);
	461
	462	mdelay(10);
	463
	464	return 0;
	465	}
	466
	467	static const struct ehci_ops mx6_ehci_ops = {
	468	.init_after_reset = mx6_init_after_reset
	469	};
	470
cccbddc3 PF	471	static int ehci_usb_phy_mode(struct udevice *dev)
	472	{
	473	struct usb_platdata *plat = dev_get_platdata(dev);
a821c4af	474	void __iomem addr = (void __iomem)devfdt_get_addr(dev);
cccbddc3 PF	475	void __iomem phy_ctrl, __iomem phy_status;
cccbddc3 PF	476	const void *blob = gd->fdt_blob;
e160f7d4	477	int offset = dev_of_offset(dev), phy_off;
cccbddc3 PF	478	u32 val;
	479
	480	/*
	481	* About fsl,usbphy, Refer to
	482	* Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
	483	*/
235f5e15	484	if (is_mx6() \|\| is_mx7ulp()) {
cccbddc3 PF	485	phy_off = fdtdec_lookup_phandle(blob,
	486	offset,
	487	"fsl,usbphy");
	488	if (phy_off < 0)
	489	return -EINVAL;
	490
	491	addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
	492	"reg");
	493	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
	494	return -EINVAL;
	495
	496	phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
	497	val = readl(phy_ctrl);
	498
	499	if (val & USBPHY_CTRL_OTG_ID)
	500	plat->init_type = USB_INIT_DEVICE;
	501	else
	502	plat->init_type = USB_INIT_HOST;
	503	} else if (is_mx7()) {
	504	phy_status = (void __iomem *)(addr +
	505	USBNC_PHY_STATUS_OFFSET);
	506	val = readl(phy_status);
	507
	508	if (val & USBNC_PHYSTATUS_ID_DIG)
	509	plat->init_type = USB_INIT_DEVICE;
	510	else
	511	plat->init_type = USB_INIT_HOST;
	512	} else {
	513	return -EINVAL;
	514	}
	515
	516	return 0;
	517	}
	518
	519	static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
	520	{
	521	struct usb_platdata *plat = dev_get_platdata(dev);
69535b33	522	enum usb_dr_mode dr_mode;
cccbddc3	523
ac28e59a	524	dr_mode = usb_get_dr_mode(dev->node);
cccbddc3	525
69535b33 AF	526	switch (dr_mode) {
	527	case USB_DR_MODE_HOST:
	528	plat->init_type = USB_INIT_HOST;
	529	break;
	530	case USB_DR_MODE_PERIPHERAL:
	531	plat->init_type = USB_INIT_DEVICE;
	532	break;
	533	case USB_DR_MODE_OTG:
	534	case USB_DR_MODE_UNKNOWN:
	535	return ehci_usb_phy_mode(dev);
	536	};
cccbddc3	537
69535b33	538	return 0;
cccbddc3 PF	539	}
cccbddc3 PF	540
501547ce MV	541	static int ehci_usb_bind(struct udevice *dev)
	542	{
	543	/*
	544	* TODO:
	545	* This driver is only partly converted to DT probing and still uses
	546	* a tremendous amount of hard-coded addresses. To make things worse,
	547	* the driver depends on specific sequential indexing of controllers,
	548	* from which it derives offsets in the PHY and ANATOP register sets.
	549	*
	550	* Here we attempt to calculate these indexes from DT information as
1198a104 IO	551	* well as we can. The USB controllers on all existing iMX6 SoCs
	552	* are placed next to each other, at addresses incremented by 0x200,
	553	* and iMX7 their addresses are shifted by 0x10000.
	554	* Thus, the index is derived from the multiple of 0x200 (0x10000 for
	555	* iMX7) offset from the first controller address.
501547ce MV	556	*
	557	* However, to complete conversion of this driver to DT probing, the
	558	* following has to be done:
	559	* - DM clock framework support for iMX must be implemented
	560	* - usb_power_config() has to be converted to clock framework
	561	* -> Thus, the ad-hoc "index" variable goes away.
	562	* - USB PHY handling has to be factored out into separate driver
	563	* -> Thus, the ad-hoc "index" variable goes away from the PHY
	564	* code, the PHY driver must parse it's address from DT. This
	565	* USB driver must find the PHY driver via DT phandle.
	566	* -> usb_power_config() shall be moved to PHY driver
	567	* With these changes in place, the ad-hoc indexing goes away and
	568	* the driver is fully converted to DT probing.
	569	*/
1198a104 IO	570	u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
1198a104 IO	571	fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
501547ce	572
1198a104	573	dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
501547ce MV	574
	575	return 0;
	576	}
	577
bb42fb4f PF	578	static int ehci_usb_probe(struct udevice *dev)
	579	{
	580	struct usb_platdata *plat = dev_get_platdata(dev);
a821c4af	581	struct usb_ehci ehci = (struct usb_ehci )devfdt_get_addr(dev);
bb42fb4f	582	struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
fcf9f9f9	583	enum usb_init_type type = plat->init_type;
bb42fb4f PF	584	struct ehci_hccr *hccr;
	585	struct ehci_hcor *hcor;
	586	int ret;
	587
0bd3d911 PF	588	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
	589	if (usb_fused((ulong)ehci)) {
	590	printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
	591	(ulong)ehci);
	592	return -ENODEV;
	593	}
	594	}
	595
bb42fb4f PF	596	priv->ehci = ehci;
bb42fb4f PF	597	priv->portnr = dev->seq;
fcf9f9f9 PF	598	priv->init_type = type;
fcf9f9f9 PF	599
921208eb	600	#if CONFIG_IS_ENABLED(DM_REGULATOR)
fcf9f9f9 PF	601	ret = device_get_supply_regulator(dev, "vbus-supply",
	602	&priv->vbus_supply);
	603	if (ret)
	604	debug("%s: No vbus supply\n", dev->name);
921208eb	605	#endif
bb42fb4f PF	606	ret = ehci_mx6_common_init(ehci, priv->portnr);
	607	if (ret)
	608	return ret;
	609
921208eb	610	#if CONFIG_IS_ENABLED(DM_REGULATOR)
fcf9f9f9 PF	611	if (priv->vbus_supply) {
	612	ret = regulator_set_enable(priv->vbus_supply,
	613	(type == USB_INIT_DEVICE) ?
	614	false : true);
	615	if (ret) {
	616	puts("Error enabling VBUS supply\n");
	617	return ret;
	618	}
	619	}
921208eb	620	#endif
bb42fb4f PF	621
	622	if (priv->init_type == USB_INIT_HOST) {
	623	setbits_le32(&ehci->usbmode, CM_HOST);
	624	writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	625	setbits_le32(&ehci->portsc, USB_EN);
	626	}
	627
	628	mdelay(10);
	629
	630	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	631	hcor = (struct ehci_hcor *)((uint32_t)hccr +
	632	HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
	633
	634	return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
	635	}
	636
bb42fb4f PF	637	static const struct udevice_id mx6_usb_ids[] = {
	638	{ .compatible = "fsl,imx27-usb" },
	639	{ }
	640	};
	641
	642	U_BOOT_DRIVER(usb_mx6) = {
	643	.name = "ehci_mx6",
	644	.id = UCLASS_USB,
	645	.of_match = mx6_usb_ids,
cccbddc3	646	.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
501547ce	647	.bind = ehci_usb_bind,
bb42fb4f	648	.probe = ehci_usb_probe,
40527342	649	.remove = ehci_deregister,
bb42fb4f PF	650	.ops = &ehci_usb_ops,
	651	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
	652	.priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
	653	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	654	};
	655	#endif