[J-u-boot.git] / include / configs / PIP405.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************
 * High Level Configuration Options
 * (easy to change)
 ***********************************************************/
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_PIP405		1	/* ...on a PIP405 board		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

/***********************************************************
 * Clock
 ***********************************************************/
#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FDC
#define CONFIG_SCSI
#define CONFIG_CMD_DATE
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP

/**************************************************************
 * I2C Stuff:
 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
 * 0x53.
 * Caution: on the same bus is the SPD (Serial Presens Detect
 * EEPROM of the SDRAM
 * The Atmel EEPROM uses 16Bit addressing.
 ***************************************************************/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		50000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */

#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
					/* 64 byte page write mode using*/
					/* last	6 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

/***************************************************************
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 ***************************************************************/
#define SPD_EEPROM_ADDRESS      0x50

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R

/**************************************************************
 * Environment definitions
 **************************************************************/
#define CONFIG_BAUDRATE		9600	/* STD Baudrate */

/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */

#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */

#define CONFIG_IPADDR		10.0.0.100
#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_PREBOOT
/***************************************************************
 * defines if an overwrite_console function exists
 *************************************************************/
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/***************************************************************
 * defines if the overwrite_console should be stored in the
 * environment
 **************************************************************/
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE

/**************************************************************
 * loads config
 *************************************************************/
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MISC_INIT_R
/***********************************************************
 * Miscellaneous configurable options
 **********************************************************/
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD       691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
					/* resource configuration	*/
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFF80000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_UPDATE_FLASH_SIZE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_FLASH_SHOW_PROGRESS	45

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

/*
 * Init Memory Controller:
 */
#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/

#define CONFIG_BOARD_EARLY_INIT_F

/* Configuration Port location */
#define CONFIG_PORT_ADDR	0xF4000000
#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in On Chip SRAM)
 */
#define CONFIG_SYS_TEMP_STACK_OCM	1
#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/***********************************************************************
 * External peripheral base address
 ***********************************************************************/
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000

/***********************************************************************
 * Last Stage Init
 ***********************************************************************/
#define CONFIG_LAST_STAGE_INIT
/************************************************************
 * Ethernet Stuff
 ***********************************************************/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/
/************************************************************
 * RTC
 ***********************************************************/
#define CONFIG_RTC_MC146818
#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/************************************************************
 * IDE/ATA stuff
 ************************************************************/
#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
#define CONFIG_SYS_ATA_DATA_OFFSET	0	/* data reg offset	*/
#define CONFIG_SYS_ATA_REG_OFFSET	0	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x200	/* alternate register offset */

#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET		/* reset for ide supported...	*/
#define CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
#define CONFIG_SUPPORT_VFAT

/************************************************************
 * ATAPI support (experimental)
 ************************************************************/
#define CONFIG_ATAPI			/* enable ATAPI Support */

/************************************************************
 * SCSI support (experimental) only SYM53C8xx supported
 ************************************************************/
#define CONFIG_SCSI_SYM53C8XX
#define CONFIG_SYS_SCSI_MAX_LUN	8	/* number of supported LUNs */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
#define CONFIG_SYS_SCSI_MAX_DEVICE	CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
#define CONFIG_SYS_SCSI_SPIN_UP_TIME	2

/************************************************************
 * Disk-On-Chip configuration
 ************************************************************/
#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM

/************************************************************
 * DISK Partition support
 ************************************************************/
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */

/************************************************************
 * Video support
 ************************************************************/
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_ONBOARD		/* Video controller is on-board */

/************************************************************
 * USB support
 ************************************************************/
#define CONFIG_USB_UHCI
#define CONFIG_USB_KEYBOARD

/* Enable needed helper functions */
#define CONFIG_SYS_STDIO_DEREGISTER		/* needs stdio_deregister */

/************************************************************
 * Debug support
 ************************************************************/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/************************************************************
 * support BZIP2 compression
 ************************************************************/
#define CONFIG_BZIP2		1

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/***********************************************************
	16	* High Level Configuration Options
	17	* (easy to change)
	18	***********************************************************/
	19	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c609719b	20	#define CONFIG_PIP405 1 /* ...on a PIP405 board */
2ae18241 WD	21
	22	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
	23
c609719b WD	24	/***********************************************************
	25	* Clock
	26	***********************************************************/
	27	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	28
a1aa0bb5 JL	29	/*
	30	* BOOTP options
	31	*/
	32	#define CONFIG_BOOTP_BOOTFILESIZE
	33	#define CONFIG_BOOTP_BOOTPATH
	34	#define CONFIG_BOOTP_GATEWAY
	35	#define CONFIG_BOOTP_HOSTNAME
	36
acf02697 JL	37	/*
	38	* Command line configuration.
	39	*/
acf02697	40	#define CONFIG_CMD_IDE
acf02697	41	#define CONFIG_CMD_PCI
acf02697 JL	42	#define CONFIG_CMD_IRQ
acf02697 JL	43	#define CONFIG_CMD_EEPROM
acf02697 JL	44	#define CONFIG_CMD_REGINFO
acf02697 JL	45	#define CONFIG_CMD_FDC
c649e3c9	46	#define CONFIG_SCSI
acf02697	47	#define CONFIG_CMD_DATE
acf02697	48	#define CONFIG_CMD_SDRAM
acf02697 JL	49	#define CONFIG_CMD_SAVES
	50	#define CONFIG_CMD_BSP
	51
c609719b WD	52	/**************************************************************
	53	* I2C Stuff:
	54	* the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
	55	* 0x53.
	56	* Caution: on the same bus is the SPD (Serial Presens Detect
	57	* EEPROM of the SDRAM
	58	* The Atmel EEPROM uses 16Bit addressing.
	59	***************************************************************/
880540de DE	60	#define CONFIG_SYS_I2C
	61	#define CONFIG_SYS_I2C_PPC4XX
	62	#define CONFIG_SYS_I2C_PPC4XX_CH0
	63	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
	64	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
c609719b	65
6d0f6bcf JCPV	66	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
6d0f6bcf JCPV	67	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
bb1f8b4f	68	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	69	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	70	#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
c609719b	71
6d0f6bcf JCPV	72	#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
6d0f6bcf JCPV	73	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
c609719b WD	74	/* 64 byte page write mode using*/
c609719b WD	75	/* last 6 bits of the address */
6d0f6bcf	76	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b	77
c609719b WD	78	/***************************************************************
	79	* Definitions for Serial Presence Detect EEPROM address
	80	* (to get SDRAM settings)
	81	***************************************************************/
	82	#define SPD_EEPROM_ADDRESS 0x50
	83
c837dcb1	84	#define CONFIG_BOARD_EARLY_INIT_F
21be309b DM	85	#define CONFIG_BOARD_EARLY_INIT_R
21be309b DM	86
c609719b WD	87	/**************************************************************
	88	* Environment definitions
	89	**************************************************************/
	90	#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
	91
c609719b	92	/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
2afbe4ed	93	/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
c609719b	94
3e38691e	95	#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
c609719b WD	96	#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
	97
	98	#define CONFIG_IPADDR 10.0.0.100
	99	#define CONFIG_SERVERIP 10.0.0.1
	100	#define CONFIG_PREBOOT
c609719b WD	101	/***************************************************************
	102	* defines if an overwrite_console function exists
	103	*************************************************************/
6d0f6bcf JCPV	104	#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
6d0f6bcf JCPV	105	#define CONFIG_SYS_CONSOLE_INFO_QUIET
c609719b WD	106	/***************************************************************
	107	* defines if the overwrite_console should be stored in the
	108	* environment
	109	**************************************************************/
6d0f6bcf	110	#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
c609719b WD	111
	112	/**************************************************************
	113	* loads config
	114	*************************************************************/
	115	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	116	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c609719b	117
7205e407	118	#define CONFIG_MISC_INIT_R
c609719b WD	119	/***********************************************************
	120	* Miscellaneous configurable options
	121	**********************************************************/
6d0f6bcf	122	#define CONFIG_SYS_LONGHELP /* undef to save memory */
acf02697	123	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	124	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	125	#else
6d0f6bcf	126	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	127	#endif
6d0f6bcf JCPV	128	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	129	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	130	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
6d0f6bcf JCPV	133	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
c609719b	134
550650dd	135	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
550650dd SR	136	#define CONFIG_SYS_NS16550_SERIAL
	137	#define CONFIG_SYS_NS16550_REG_SIZE 1
	138	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	139
6d0f6bcf JCPV	140	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf JCPV	141	#define CONFIG_SYS_BASE_BAUD 691200
c609719b WD	142
c609719b WD	143	/* The following table includes the supported baudrates */
6d0f6bcf	144	#define CONFIG_SYS_BAUDRATE_TABLE \
c609719b WD	145	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	146	57600, 115200, 230400, 460800, 921600 }
	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
6d0f6bcf JCPV	149	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b	150
c609719b WD	151	/*-----------------------------------------------------------------------
	152	* PCI stuff
	153	*-----------------------------------------------------------------------
	154	*/
	155	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	156	#define PCI_HOST_FORCE 1 /* configure as pci host */
	157	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	158
	159	#define CONFIG_PCI /* include pci support */
842033e6	160	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c609719b WD	161	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
	162	#define CONFIG_PCI_PNP /* pci plug-and-play */
	163	/* resource configuration */
6d0f6bcf JCPV	164	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	165	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	166	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	167	#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	168	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	169	#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
	170	#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
	171	#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
c609719b WD	172
	173	/*-----------------------------------------------------------------------
	174	* Start addresses for the final memory configuration
	175	* (Set up by the startup code)
6d0f6bcf	176	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	177	*/
6d0f6bcf JCPV	178	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	179	#define CONFIG_SYS_FLASH_BASE 0xFFF80000
	180	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	181	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
	182	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
c609719b WD	183
	184	/*
	185	* For booting Linux, the board info and command line data
	186	* have to be in the first 8 MB of memory, since this is
	187	* the maximum mapped by the Linux kernel during initialization.
	188	*/
6d0f6bcf	189	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	190	/*-----------------------------------------------------------------------
	191	* FLASH organization
	192	*/
21be309b DM	193	#define CONFIG_SYS_UPDATE_FLASH_SIZE
	194	#define CONFIG_SYS_FLASH_PROTECTION
	195	#define CONFIG_SYS_FLASH_EMPTY_INFO
	196
	197	#define CONFIG_SYS_FLASH_CFI
	198	#define CONFIG_FLASH_CFI_DRIVER
	199
	200	#define CONFIG_FLASH_SHOW_PROGRESS 45
c609719b	201
21be309b DM	202	#define CONFIG_SYS_MAX_FLASH_BANKS 1
21be309b DM	203	#define CONFIG_SYS_MAX_FLASH_SECT 256
c609719b	204
c609719b WD	205	/*
	206	* Init Memory Controller:
	207	*/
7205e407 WD	208	#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
	209	#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
	210	/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
	211	#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
c609719b	212
c837dcb1	213	#define CONFIG_BOARD_EARLY_INIT_F
c609719b WD	214
	215	/* Configuration Port location */
	216	#define CONFIG_PORT_ADDR 0xF4000000
	217	#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
	218
c609719b WD	219	/*-----------------------------------------------------------------------
	220	* Definitions for initial stack pointer and data area (in On Chip SRAM)
	221	*/
6d0f6bcf JCPV	222	#define CONFIG_SYS_TEMP_STACK_OCM 1
	223	#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
	224	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	225	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
553f0982	226	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
25ddd1fb	227	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	228	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	229
c609719b WD	230	/***********************************************************************
	231	* External peripheral base address
	232	***********************************************************************/
6d0f6bcf	233	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
c609719b WD	234
	235	/***********************************************************************
	236	* Last Stage Init
	237	***********************************************************************/
	238	#define CONFIG_LAST_STAGE_INIT
	239	/************************************************************
	240	* Ethernet Stuff
	241	***********************************************************/
96e21f86	242	#define CONFIG_PPC4xx_EMAC
c609719b WD	243	#define CONFIG_MII 1 /* MII PHY management */
c609719b WD	244	#define CONFIG_PHY_ADDR 1 /* PHY address */
c609719b WD	245	/************************************************************
	246	* RTC
	247	***********************************************************/
	248	#define CONFIG_RTC_MC146818
	249	#undef CONFIG_WATCHDOG /* watchdog disabled */
	250
	251	/************************************************************
	252	* IDE/ATA stuff
	253	************************************************************/
6d0f6bcf JCPV	254	#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
6d0f6bcf JCPV	255	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS2) / max. 2 drives per IDE bus */
c609719b	256
6d0f6bcf JCPV	257	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
	258	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	259	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
	260	#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
	261	#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
	262	#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
c609719b WD	263
	264	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	265	#undef CONFIG_IDE_LED /* no led for ide supported */
	266	#define CONFIG_IDE_RESET /* reset for ide supported... */
	267	#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
7205e407	268	#define CONFIG_SUPPORT_VFAT
c609719b WD	269
	270	/************************************************************
	271	* ATAPI support (experimental)
	272	************************************************************/
	273	#define CONFIG_ATAPI /* enable ATAPI Support */
	274
	275	/************************************************************
	276	* SCSI support (experimental) only SYM53C8xx supported
	277	************************************************************/
	278	#define CONFIG_SCSI_SYM53C8XX
6d0f6bcf JCPV	279	#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
	280	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
	281	#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
	282	#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
c609719b WD	283
	284	/************************************************************
	285	* Disk-On-Chip configuration
	286	************************************************************/
6d0f6bcf JCPV	287	#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	288	#define CONFIG_SYS_DOC_SHORT_TIMEOUT
	289	#define CONFIG_SYS_DOC_SUPPORT_2000
	290	#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
c609719b WD	291
	292	/************************************************************
	293	* DISK Partition support
	294	************************************************************/
	295	#define CONFIG_DOS_PARTITION
	296	#define CONFIG_MAC_PARTITION
	297	#define CONFIG_ISO_PARTITION /* Experimental */
	298
c609719b WD	299	/************************************************************
	300	* Video support
	301	************************************************************/
c609719b WD	302	#define CONFIG_VIDEO_LOGO
c609719b WD	303	#define CONFIG_CONSOLE_EXTRA_INFO
c609719b WD	304	#define CONFIG_VIDEO_SW_CURSOR
	305	#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
	306
	307	/************************************************************
	308	* USB support
	309	************************************************************/
	310	#define CONFIG_USB_UHCI
	311	#define CONFIG_USB_KEYBOARD
c609719b WD	312
c609719b WD	313	/* Enable needed helper functions */
52cb4d4f	314	#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
c609719b WD	315
	316	/************************************************************
	317	* Debug support
	318	************************************************************/
acf02697	319	#if defined(CONFIG_CMD_KGDB)
c609719b	320	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
c609719b WD	321	#endif
c609719b WD	322
a2663ea4 WD	323	/************************************************************
	324	* support BZIP2 compression
	325	************************************************************/
	326	#define CONFIG_BZIP2 1
	327
c609719b	328	#endif /* __CONFIG_H */