[J-u-boot.git] / drivers / mmc / sh_mmcif.c

/*
 * MMCIF driver.
 *
 * Copyright (C)  2011 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */

#include <config.h>
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mmc.h>
#include <malloc.h>
#include <asm/errno.h>
#include <asm/io.h>
#include "sh_mmcif.h"

#define DRIVER_NAME	"sh_mmcif"

static void *mmc_priv(struct mmc *mmc)
{
	return (void *)mmc->priv;
}

static int sh_mmcif_intr(void *dev_id)
{
	struct sh_mmcif_host *host = dev_id;
	u32 state = 0;

	state = sh_mmcif_read(&host->regs->ce_int);
	state &= sh_mmcif_read(&host->regs->ce_int_mask);

	if (state & INT_RBSYE) {
		sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
		sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
		goto end;
	} else if (state & INT_CRSPE) {
		sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
		sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
		/* one more interrupt (INT_RBSYE) */
		if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
			return -EAGAIN;
		goto end;
	} else if (state & INT_BUFREN) {
		sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
		sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
		goto end;
	} else if (state & INT_BUFWEN) {
		sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
		sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
		goto end;
	} else if (state & INT_CMD12DRE) {
		sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
				  INT_BUFRE), &host->regs->ce_int);
		sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
		goto end;
	} else if (state & INT_BUFRE) {
		sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
		sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
		goto end;
	} else if (state & INT_DTRANE) {
		sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
		sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
		goto end;
	} else if (state & INT_CMD12RBE) {
		sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
				&host->regs->ce_int);
		sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
		goto end;
	} else if (state & INT_ERR_STS) {
		/* err interrupts */
		sh_mmcif_write(~state, &host->regs->ce_int);
		sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
		goto err;
	} else
		return -EAGAIN;

err:
	host->sd_error = 1;
	debug("%s: int err state = %08x\n", DRIVER_NAME, state);
end:
	host->wait_int = 1;
	return 0;
}

static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
{
	int timeout = 10000000;

	while (1) {
		timeout--;
		if (timeout < 0) {
			printf("timeout\n");
			return 0;
		}

		if (!sh_mmcif_intr(host))
			break;

		udelay(1);	/* 1 usec */
	}

	return 1;	/* Return value: NOT 0 = complete waiting */
}

static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
{
	int i;

	sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
	sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);

	if (!clk)
		return;
	if (clk == CLKDEV_EMMC_DATA) {
		sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
	} else {
		for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++)
			;
		sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl);
	}
	sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
}

static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
{
	u32 tmp;

	tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
							 CLK_CLEAR);

	sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
	sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
	sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
			&host->regs->ce_clk_ctrl);
	/* byte swap on */
	sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
}

static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
{
	u32 state1, state2;
	int ret, timeout = 10000000;

	host->sd_error = 0;
	host->wait_int = 0;

	state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
	state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
	debug("%s: ERR HOST_STS1 = %08x\n", \
			DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
	debug("%s: ERR HOST_STS2 = %08x\n", \
			DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));

	if (state1 & STS1_CMDSEQ) {
		debug("%s: Forced end of command sequence\n", DRIVER_NAME);
		sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
		sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
		while (1) {
			timeout--;
			if (timeout < 0) {
				printf(DRIVER_NAME": Forceed end of " \
					"command sequence timeout err\n");
				return -EILSEQ;
			}
			if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
								& STS1_CMDSEQ))
				break;
		}
		sh_mmcif_sync_reset(host);
		return -EILSEQ;
	}

	if (state2 & STS2_CRC_ERR)
		ret = -EILSEQ;
	else if (state2 & STS2_TIMEOUT_ERR)
		ret = TIMEOUT;
	else
		ret = -EILSEQ;
	return ret;
}

static int sh_mmcif_single_read(struct sh_mmcif_host *host,
				struct mmc_data *data)
{
	long time;
	u32 blocksize, i;
	unsigned long *p = (unsigned long *)data->dest;

	if ((unsigned long)p & 0x00000001) {
		printf("%s: The data pointer is unaligned.", __func__);
		return -EIO;
	}

	host->wait_int = 0;

	/* buf read enable */
	sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
	time = mmcif_wait_interrupt_flag(host);
	if (time == 0 || host->sd_error != 0)
		return sh_mmcif_error_manage(host);

	host->wait_int = 0;
	blocksize = (BLOCK_SIZE_MASK &
			sh_mmcif_read(&host->regs->ce_block_set)) + 3;
	for (i = 0; i < blocksize / 4; i++)
		*p++ = sh_mmcif_read(&host->regs->ce_data);

	/* buffer read end */
	sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
	time = mmcif_wait_interrupt_flag(host);
	if (time == 0 || host->sd_error != 0)
		return sh_mmcif_error_manage(host);

	host->wait_int = 0;
	return 0;
}

static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
				struct mmc_data *data)
{
	long time;
	u32 blocksize, i, j;
	unsigned long *p = (unsigned long *)data->dest;

	if ((unsigned long)p & 0x00000001) {
		printf("%s: The data pointer is unaligned.", __func__);
		return -EIO;
	}

	host->wait_int = 0;
	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
	for (j = 0; j < data->blocks; j++) {
		sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
		time = mmcif_wait_interrupt_flag(host);
		if (time == 0 || host->sd_error != 0)
			return sh_mmcif_error_manage(host);

		host->wait_int = 0;
		for (i = 0; i < blocksize / 4; i++)
			*p++ = sh_mmcif_read(&host->regs->ce_data);

		WATCHDOG_RESET();
	}
	return 0;
}

static int sh_mmcif_single_write(struct sh_mmcif_host *host,
				 struct mmc_data *data)
{
	long time;
	u32 blocksize, i;
	const unsigned long *p = (unsigned long *)data->dest;

	if ((unsigned long)p & 0x00000001) {
		printf("%s: The data pointer is unaligned.", __func__);
		return -EIO;
	}

	host->wait_int = 0;
	sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);

	time = mmcif_wait_interrupt_flag(host);
	if (time == 0 || host->sd_error != 0)
		return sh_mmcif_error_manage(host);

	host->wait_int = 0;
	blocksize = (BLOCK_SIZE_MASK &
			sh_mmcif_read(&host->regs->ce_block_set)) + 3;
	for (i = 0; i < blocksize / 4; i++)
		sh_mmcif_write(*p++, &host->regs->ce_data);

	/* buffer write end */
	sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);

	time = mmcif_wait_interrupt_flag(host);
	if (time == 0 || host->sd_error != 0)
		return sh_mmcif_error_manage(host);

	host->wait_int = 0;
	return 0;
}

static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
				struct mmc_data *data)
{
	long time;
	u32 i, j, blocksize;
	const unsigned long *p = (unsigned long *)data->dest;

	if ((unsigned long)p & 0x00000001) {
		printf("%s: The data pointer is unaligned.", __func__);
		return -EIO;
	}

	host->wait_int = 0;
	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
	for (j = 0; j < data->blocks; j++) {
		sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);

		time = mmcif_wait_interrupt_flag(host);

		if (time == 0 || host->sd_error != 0)
			return sh_mmcif_error_manage(host);

		host->wait_int = 0;
		for (i = 0; i < blocksize / 4; i++)
			sh_mmcif_write(*p++, &host->regs->ce_data);

		WATCHDOG_RESET();
	}
	return 0;
}

static void sh_mmcif_get_response(struct sh_mmcif_host *host,
					struct mmc_cmd *cmd)
{
	if (cmd->resp_type & MMC_RSP_136) {
		cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
		cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
		cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
		cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
		debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
			 cmd->response[1], cmd->response[2], cmd->response[3]);
	} else {
		cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
	}
}

static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
					struct mmc_cmd *cmd)
{
	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
}

static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
				struct mmc_data *data, struct mmc_cmd *cmd)
{
	u32 tmp = 0;
	u32 opc = cmd->cmdidx;

	/* Response Type check */
	switch (cmd->resp_type) {
	case MMC_RSP_NONE:
		tmp |= CMD_SET_RTYP_NO;
		break;
	case MMC_RSP_R1:
	case MMC_RSP_R1b:
	case MMC_RSP_R3:
		tmp |= CMD_SET_RTYP_6B;
		break;
	case MMC_RSP_R2:
		tmp |= CMD_SET_RTYP_17B;
		break;
	default:
		printf(DRIVER_NAME": Not support type response.\n");
		break;
	}

	/* RBSY */
	if (opc == MMC_CMD_SWITCH)
		tmp |= CMD_SET_RBSY;

	/* WDAT / DATW */
	if (host->data) {
		tmp |= CMD_SET_WDAT;
		switch (host->bus_width) {
		case MMC_BUS_WIDTH_1:
			tmp |= CMD_SET_DATW_1;
			break;
		case MMC_BUS_WIDTH_4:
			tmp |= CMD_SET_DATW_4;
			break;
		case MMC_BUS_WIDTH_8:
			tmp |= CMD_SET_DATW_8;
			break;
		default:
			printf(DRIVER_NAME": Not support bus width.\n");
			break;
		}
	}
	/* DWEN */
	if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
	    opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
		tmp |= CMD_SET_DWEN;
	/* CMLTE/CMD12EN */
	if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
	    opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
		tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
		sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
	}
	/* RIDXC[1:0] check bits */
	if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
	    opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
		tmp |= CMD_SET_RIDXC_BITS;
	/* RCRC7C[1:0] check bits */
	if (opc == MMC_CMD_SEND_OP_COND)
		tmp |= CMD_SET_CRC7C_BITS;
	/* RCRC7C[1:0] internal CRC7 */
	if (opc == MMC_CMD_ALL_SEND_CID ||
		opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
		tmp |= CMD_SET_CRC7C_INTERNAL;

	return opc = ((opc << 24) | tmp);
}

static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
				struct mmc_data *data, u16 opc)
{
	u32 ret;

	switch (opc) {
	case MMC_CMD_READ_MULTIPLE_BLOCK:
		ret = sh_mmcif_multi_read(host, data);
		break;
	case MMC_CMD_WRITE_MULTIPLE_BLOCK:
		ret = sh_mmcif_multi_write(host, data);
		break;
	case MMC_CMD_WRITE_SINGLE_BLOCK:
		ret = sh_mmcif_single_write(host, data);
		break;
	case MMC_CMD_READ_SINGLE_BLOCK:
	case MMC_CMD_SEND_EXT_CSD:
		ret = sh_mmcif_single_read(host, data);
		break;
	default:
		printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
		ret = -EINVAL;
		break;
	}
	return ret;
}

static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
				struct mmc_data *data, struct mmc_cmd *cmd)
{
	long time;
	int ret = 0, mask = 0;
	u32 opc = cmd->cmdidx;

	if (opc == MMC_CMD_STOP_TRANSMISSION) {
		/* MMCIF sends the STOP command automatically */
		if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
			sh_mmcif_bitset(MASK_MCMD12DRE,
					&host->regs->ce_int_mask);
		else
			sh_mmcif_bitset(MASK_MCMD12RBE,
					&host->regs->ce_int_mask);

		time = mmcif_wait_interrupt_flag(host);
		if (time == 0 || host->sd_error != 0)
			return sh_mmcif_error_manage(host);

		sh_mmcif_get_cmd12response(host, cmd);
		return 0;
	}
	if (opc == MMC_CMD_SWITCH)
		mask = MASK_MRBSYE;
	else
		mask = MASK_MCRSPE;

	mask |=	MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
		MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
		MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
		MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;

	if (host->data) {
		sh_mmcif_write(0, &host->regs->ce_block_set);
		sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
	}
	opc = sh_mmcif_set_cmd(host, data, cmd);

	sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
	sh_mmcif_write(mask, &host->regs->ce_int_mask);

	debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
	/* set arg */
	sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
	host->wait_int = 0;
	/* set cmd */
	sh_mmcif_write(opc, &host->regs->ce_cmd_set);

	time = mmcif_wait_interrupt_flag(host);
	if (time == 0)
		return sh_mmcif_error_manage(host);

	if (host->sd_error) {
		switch (cmd->cmdidx) {
		case MMC_CMD_ALL_SEND_CID:
		case MMC_CMD_SELECT_CARD:
		case MMC_CMD_APP_CMD:
			ret = TIMEOUT;
			break;
		default:
			printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
			ret = sh_mmcif_error_manage(host);
			break;
		}
		host->sd_error = 0;
		host->wait_int = 0;
		return ret;
	}

	/* if no response */
	if (!(opc & 0x00C00000))
		return 0;

	if (host->wait_int == 1) {
		sh_mmcif_get_response(host, cmd);
		host->wait_int = 0;
	}
	if (host->data)
		ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
	host->last_cmd = cmd->cmdidx;

	return ret;
}

static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
			    struct mmc_data *data)
{
	struct sh_mmcif_host *host = mmc_priv(mmc);
	int ret;

	WATCHDOG_RESET();

	switch (cmd->cmdidx) {
	case MMC_CMD_APP_CMD:
		return TIMEOUT;
	case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
		if (data)
			/* ext_csd */
			break;
		else
			/* send_if_cond cmd (not support) */
			return TIMEOUT;
	default:
		break;
	}
	host->sd_error = 0;
	host->data = data;
	ret = sh_mmcif_start_cmd(host, data, cmd);
	host->data = NULL;

	return ret;
}

static void sh_mmcif_set_ios(struct mmc *mmc)
{
	struct sh_mmcif_host *host = mmc_priv(mmc);

	if (mmc->clock)
		sh_mmcif_clock_control(host, mmc->clock);

	if (mmc->bus_width == 8)
		host->bus_width = MMC_BUS_WIDTH_8;
	else if (mmc->bus_width == 4)
		host->bus_width = MMC_BUS_WIDTH_4;
	else
		host->bus_width = MMC_BUS_WIDTH_1;

	debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
}

static int sh_mmcif_init(struct mmc *mmc)
{
	struct sh_mmcif_host *host = mmc_priv(mmc);

	sh_mmcif_sync_reset(host);
	sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
	return 0;
}

int mmcif_mmc_init(void)
{
	int ret = 0;
	struct mmc *mmc;
	struct sh_mmcif_host *host = NULL;

	mmc = malloc(sizeof(struct mmc));
	if (!mmc)
		ret = -ENOMEM;
	memset(mmc, 0, sizeof(*mmc));
	host = malloc(sizeof(struct sh_mmcif_host));
	if (!host)
		ret = -ENOMEM;
	memset(host, 0, sizeof(*host));

	mmc->f_min = CLKDEV_MMC_INIT;
	mmc->f_max = CLKDEV_EMMC_DATA;
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
			 MMC_MODE_8BIT | MMC_MODE_HC;
	memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
	mmc->send_cmd = sh_mmcif_request;
	mmc->set_ios = sh_mmcif_set_ios;
	mmc->init = sh_mmcif_init;
	mmc->getcd = NULL;
	host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
	host->clk = CONFIG_SH_MMCIF_CLK;
	mmc->priv = host;

	mmc_register(mmc);

	return ret;
}
Commit	Line	Data
afb35666 YS	1	/*
	2	* MMCIF driver.
	3	*
	4	* Copyright (C) 2011 Renesas Solutions Corp.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10
	11	#include <config.h>
	12	#include <common.h>
	13	#include <watchdog.h>
	14	#include <command.h>
	15	#include <mmc.h>
	16	#include <malloc.h>
	17	#include <asm/errno.h>
	18	#include <asm/io.h>
	19	#include "sh_mmcif.h"
	20
	21	#define DRIVER_NAME "sh_mmcif"
	22
	23	static void mmc_priv(struct mmc mmc)
	24	{
	25	return (void *)mmc->priv;
	26	}
	27
	28	static int sh_mmcif_intr(void *dev_id)
	29	{
	30	struct sh_mmcif_host *host = dev_id;
	31	u32 state = 0;
	32
	33	state = sh_mmcif_read(&host->regs->ce_int);
	34	state &= sh_mmcif_read(&host->regs->ce_int_mask);
	35
	36	if (state & INT_RBSYE) {
	37	sh_mmcif_write(~(INT_RBSYE \| INT_CRSPE), &host->regs->ce_int);
	38	sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
	39	goto end;
	40	} else if (state & INT_CRSPE) {
	41	sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
	42	sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
	43	/* one more interrupt (INT_RBSYE) */
	44	if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
	45	return -EAGAIN;
	46	goto end;
	47	} else if (state & INT_BUFREN) {
	48	sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
	49	sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
	50	goto end;
	51	} else if (state & INT_BUFWEN) {
	52	sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
	53	sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
	54	goto end;
	55	} else if (state & INT_CMD12DRE) {
	56	sh_mmcif_write(~(INT_CMD12DRE \| INT_CMD12RBE \| INT_CMD12CRE \|
	57	INT_BUFRE), &host->regs->ce_int);
	58	sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
	59	goto end;
	60	} else if (state & INT_BUFRE) {
	61	sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
	62	sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
	63	goto end;
	64	} else if (state & INT_DTRANE) {
65	sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
66	sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
67	goto end;
68	} else if (state & INT_CMD12RBE) {
69	sh_mmcif_write(~(INT_CMD12RBE \| INT_CMD12CRE),
70	&host->regs->ce_int);
71	sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
72	goto end;
73	} else if (state & INT_ERR_STS) {
74	/* err interrupts */
75	sh_mmcif_write(~state, &host->regs->ce_int);
76	sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
77	goto err;
78	} else
79	return -EAGAIN;
80
81	err:
82	host->sd_error = 1;
83	debug("%s: int err state = %08x\n", DRIVER_NAME, state);
84	end:
85	host->wait_int = 1;
86	return 0;
87	}
88
89	static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
90	{
91	int timeout = 10000000;
92
93	while (1) {
94	timeout--;
95	if (timeout < 0) {
96	printf("timeout\n");
97	return 0;
98	}
99
100	if (!sh_mmcif_intr(host))
101	break;
102
103	udelay(1); /* 1 usec */
104	}
105
106	return 1; /* Return value: NOT 0 = complete waiting */
107	}
108
109	static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
110	{
111	int i;
112
113	sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
114	sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
115
116	if (!clk)
117	return;
118	if (clk == CLKDEV_EMMC_DATA) {
119	sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
120	} else {
121	for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++)
122	;
123	sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl);
124	}
125	sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
126	}
127
128	static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
129	{
130	u32 tmp;
131
132	tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE \|
133	CLK_CLEAR);
134
135	sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
136	sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
137	sh_mmcif_bitset(tmp \| SRSPTO_256 \| SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29,
138	&host->regs->ce_clk_ctrl);
139	/* byte swap on */
140	sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
141	}
142
143	static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
144	{
145	u32 state1, state2;
146	int ret, timeout = 10000000;
147
148	host->sd_error = 0;
149	host->wait_int = 0;
150
151	state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
152	state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
153	debug("%s: ERR HOST_STS1 = %08x\n", \
154	DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
155	debug("%s: ERR HOST_STS2 = %08x\n", \
156	DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
157
158	if (state1 & STS1_CMDSEQ) {
159	debug("%s: Forced end of command sequence\n", DRIVER_NAME);
160	sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
161	sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
162	while (1) {
163	timeout--;
164	if (timeout < 0) {
165	printf(DRIVER_NAME": Forceed end of " \
166	"command sequence timeout err\n");
167	return -EILSEQ;
168	}
169	if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
170	& STS1_CMDSEQ))
171	break;
172	}
173	sh_mmcif_sync_reset(host);
174	return -EILSEQ;
175	}
176
177	if (state2 & STS2_CRC_ERR)
178	ret = -EILSEQ;
179	else if (state2 & STS2_TIMEOUT_ERR)
180	ret = TIMEOUT;
181	else
182	ret = -EILSEQ;
183	return ret;
184	}
185
186	static int sh_mmcif_single_read(struct sh_mmcif_host *host,
187	struct mmc_data *data)
188	{
189	long time;
190	u32 blocksize, i;
191	unsigned long p = (unsigned long )data->dest;
192
193	if ((unsigned long)p & 0x00000001) {
194	printf("%s: The data pointer is unaligned.", __func__);
195	return -EIO;
196	}
197
198	host->wait_int = 0;
199
200	/* buf read enable */
201	sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
202	time = mmcif_wait_interrupt_flag(host);
203	if (time == 0 \|\| host->sd_error != 0)
204	return sh_mmcif_error_manage(host);
205
206	host->wait_int = 0;
207	blocksize = (BLOCK_SIZE_MASK &
208	sh_mmcif_read(&host->regs->ce_block_set)) + 3;
209	for (i = 0; i < blocksize / 4; i++)
210	*p++ = sh_mmcif_read(&host->regs->ce_data);
211
212	/* buffer read end */
213	sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
214	time = mmcif_wait_interrupt_flag(host);
215	if (time == 0 \|\| host->sd_error != 0)
216	return sh_mmcif_error_manage(host);
217
218	host->wait_int = 0;
219	return 0;
220	}
221
222	static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
223	struct mmc_data *data)
224	{
225	long time;
226	u32 blocksize, i, j;
227	unsigned long p = (unsigned long )data->dest;
228
229	if ((unsigned long)p & 0x00000001) {
230	printf("%s: The data pointer is unaligned.", __func__);
231	return -EIO;
232	}
233
234	host->wait_int = 0;
235	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
236	for (j = 0; j < data->blocks; j++) {
237	sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
238	time = mmcif_wait_interrupt_flag(host);
239	if (time == 0 \|\| host->sd_error != 0)
240	return sh_mmcif_error_manage(host);
241
242	host->wait_int = 0;
243	for (i = 0; i < blocksize / 4; i++)
244	*p++ = sh_mmcif_read(&host->regs->ce_data);
245
246	WATCHDOG_RESET();
247	}
248	return 0;
249	}
250
251	static int sh_mmcif_single_write(struct sh_mmcif_host *host,
252	struct mmc_data *data)
253	{
254	long time;
255	u32 blocksize, i;
256	const unsigned long p = (unsigned long )data->dest;
257
258	if ((unsigned long)p & 0x00000001) {
259	printf("%s: The data pointer is unaligned.", __func__);
260	return -EIO;
261	}
262
263	host->wait_int = 0;
264	sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
265
266	time = mmcif_wait_interrupt_flag(host);
267	if (time == 0 \|\| host->sd_error != 0)
268	return sh_mmcif_error_manage(host);
269
270	host->wait_int = 0;
271	blocksize = (BLOCK_SIZE_MASK &
272	sh_mmcif_read(&host->regs->ce_block_set)) + 3;
273	for (i = 0; i < blocksize / 4; i++)
274	sh_mmcif_write(*p++, &host->regs->ce_data);
275
276	/* buffer write end */
277	sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
278
279	time = mmcif_wait_interrupt_flag(host);
280	if (time == 0 \|\| host->sd_error != 0)
281	return sh_mmcif_error_manage(host);
282
283	host->wait_int = 0;
284	return 0;
285	}
286
287	static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
288	struct mmc_data *data)
289	{
290	long time;
291	u32 i, j, blocksize;
292	const unsigned long p = (unsigned long )data->dest;
293
294	if ((unsigned long)p & 0x00000001) {
295	printf("%s: The data pointer is unaligned.", __func__);
296	return -EIO;
297	}
298
299	host->wait_int = 0;
300	blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
301	for (j = 0; j < data->blocks; j++) {
302	sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
303
304	time = mmcif_wait_interrupt_flag(host);
305
306	if (time == 0 \|\| host->sd_error != 0)
307	return sh_mmcif_error_manage(host);
308
309	host->wait_int = 0;
310	for (i = 0; i < blocksize / 4; i++)
311	sh_mmcif_write(*p++, &host->regs->ce_data);
312
313	WATCHDOG_RESET();
314	}
315	return 0;
316	}
317
318	static void sh_mmcif_get_response(struct sh_mmcif_host *host,
319	struct mmc_cmd *cmd)
320	{
321	if (cmd->resp_type & MMC_RSP_136) {
322	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
323	cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
324	cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
325	cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
326	debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
327	cmd->response[1], cmd->response[2], cmd->response[3]);
328	} else {
329	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
330	}
331	}
332
333	static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
334	struct mmc_cmd *cmd)
335	{
336	cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
337	}
338
339	static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
340	struct mmc_data data, struct mmc_cmd cmd)
341	{
342	u32 tmp = 0;
343	u32 opc = cmd->cmdidx;
344
345	/* Response Type check */
346	switch (cmd->resp_type) {
347	case MMC_RSP_NONE:
348	tmp \|= CMD_SET_RTYP_NO;
349	break;
350	case MMC_RSP_R1:
351	case MMC_RSP_R1b:
352	case MMC_RSP_R3:
353	tmp \|= CMD_SET_RTYP_6B;
354	break;
355	case MMC_RSP_R2:
356	tmp \|= CMD_SET_RTYP_17B;
357	break;
358	default:
359	printf(DRIVER_NAME": Not support type response.\n");
360	break;
361	}
362
363	/* RBSY */
364	if (opc == MMC_CMD_SWITCH)
365	tmp \|= CMD_SET_RBSY;
366
367	/* WDAT / DATW */
368	if (host->data) {
369	tmp \|= CMD_SET_WDAT;
370	switch (host->bus_width) {
371	case MMC_BUS_WIDTH_1:
372	tmp \|= CMD_SET_DATW_1;
373	break;
374	case MMC_BUS_WIDTH_4:
375	tmp \|= CMD_SET_DATW_4;
376	break;
377	case MMC_BUS_WIDTH_8:
378	tmp \|= CMD_SET_DATW_8;
379	break;
380	default:
381	printf(DRIVER_NAME": Not support bus width.\n");
382	break;
383	}
384	}
385	/* DWEN */
386	if (opc == MMC_CMD_WRITE_SINGLE_BLOCK \|\|
387	opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
388	tmp \|= CMD_SET_DWEN;
389	/* CMLTE/CMD12EN */
390	if (opc == MMC_CMD_READ_MULTIPLE_BLOCK \|\|
391	opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
392	tmp \|= CMD_SET_CMLTE \| CMD_SET_CMD12EN;
393	sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
394	}
395	/* RIDXC[1:0] check bits */
396	if (opc == MMC_CMD_SEND_OP_COND \|\| opc == MMC_CMD_ALL_SEND_CID \|\|
397	opc == MMC_CMD_SEND_CSD \|\| opc == MMC_CMD_SEND_CID)
398	tmp \|= CMD_SET_RIDXC_BITS;
399	/* RCRC7C[1:0] check bits */
400	if (opc == MMC_CMD_SEND_OP_COND)
401	tmp \|= CMD_SET_CRC7C_BITS;
402	/* RCRC7C[1:0] internal CRC7 */
403	if (opc == MMC_CMD_ALL_SEND_CID \|\|
404	opc == MMC_CMD_SEND_CSD \|\| opc == MMC_CMD_SEND_CID)
405	tmp \|= CMD_SET_CRC7C_INTERNAL;
406
407	return opc = ((opc << 24) \| tmp);
408	}
409
410	static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
411	struct mmc_data *data, u16 opc)
412	{
413	u32 ret;
414
415	switch (opc) {
416	case MMC_CMD_READ_MULTIPLE_BLOCK:
417	ret = sh_mmcif_multi_read(host, data);
418	break;
419	case MMC_CMD_WRITE_MULTIPLE_BLOCK:
420	ret = sh_mmcif_multi_write(host, data);
421	break;
422	case MMC_CMD_WRITE_SINGLE_BLOCK:
423	ret = sh_mmcif_single_write(host, data);
424	break;
425	case MMC_CMD_READ_SINGLE_BLOCK:
426	case MMC_CMD_SEND_EXT_CSD:
427	ret = sh_mmcif_single_read(host, data);
428	break;
429	default:
430	printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
431	ret = -EINVAL;
432	break;
433	}
434	return ret;
435	}
436
437	static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
438	struct mmc_data data, struct mmc_cmd cmd)
439	{
440	long time;
441	int ret = 0, mask = 0;
442	u32 opc = cmd->cmdidx;
443
444	if (opc == MMC_CMD_STOP_TRANSMISSION) {
445	/* MMCIF sends the STOP command automatically */
446	if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
447	sh_mmcif_bitset(MASK_MCMD12DRE,
448	&host->regs->ce_int_mask);
449	else
450	sh_mmcif_bitset(MASK_MCMD12RBE,
451	&host->regs->ce_int_mask);
452
453	time = mmcif_wait_interrupt_flag(host);
454	if (time == 0 \|\| host->sd_error != 0)
455	return sh_mmcif_error_manage(host);
456
457	sh_mmcif_get_cmd12response(host, cmd);
458	return 0;
459	}
460	if (opc == MMC_CMD_SWITCH)
461	mask = MASK_MRBSYE;
462	else
463	mask = MASK_MCRSPE;
464
465	mask \|= MASK_MCMDVIO \| MASK_MBUFVIO \| MASK_MWDATERR \|
466	MASK_MRDATERR \| MASK_MRIDXERR \| MASK_MRSPERR \|
467	MASK_MCCSTO \| MASK_MCRCSTO \| MASK_MWDATTO \|
468	MASK_MRDATTO \| MASK_MRBSYTO \| MASK_MRSPTO;
469
470	if (host->data) {
471	sh_mmcif_write(0, &host->regs->ce_block_set);
472	sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
473	}
474	opc = sh_mmcif_set_cmd(host, data, cmd);
475
476	sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
477	sh_mmcif_write(mask, &host->regs->ce_int_mask);
478
479	debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
480	/* set arg */
481	sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
482	host->wait_int = 0;
483	/* set cmd */
484	sh_mmcif_write(opc, &host->regs->ce_cmd_set);
485
486	time = mmcif_wait_interrupt_flag(host);
487	if (time == 0)
488	return sh_mmcif_error_manage(host);
489
490	if (host->sd_error) {
491	switch (cmd->cmdidx) {
492	case MMC_CMD_ALL_SEND_CID:
493	case MMC_CMD_SELECT_CARD:
494	case MMC_CMD_APP_CMD:
495	ret = TIMEOUT;
496	break;
497	default:
498	printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
499	ret = sh_mmcif_error_manage(host);
500	break;
501	}
502	host->sd_error = 0;
503	host->wait_int = 0;
504	return ret;
505	}
506
507	/* if no response */
508	if (!(opc & 0x00C00000))
509	return 0;
510
511	if (host->wait_int == 1) {
512	sh_mmcif_get_response(host, cmd);
513	host->wait_int = 0;
514	}
515	if (host->data)
516	ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
517	host->last_cmd = cmd->cmdidx;
518
519	return ret;
520	}
521
522	static int sh_mmcif_request(struct mmc mmc, struct mmc_cmd cmd,
523	struct mmc_data *data)
524	{
525	struct sh_mmcif_host *host = mmc_priv(mmc);
526	int ret;
527
528	WATCHDOG_RESET();
529
530	switch (cmd->cmdidx) {
531	case MMC_CMD_APP_CMD:
532	return TIMEOUT;
533	case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
534	if (data)
535	/* ext_csd */
536	break;
537	else
538	/* send_if_cond cmd (not support) */
539	return TIMEOUT;
540	default:
541	break;
542	}
543	host->sd_error = 0;
544	host->data = data;
545	ret = sh_mmcif_start_cmd(host, data, cmd);
546	host->data = NULL;
547
548	return ret;
549	}
550
551	static void sh_mmcif_set_ios(struct mmc *mmc)
552	{
553	struct sh_mmcif_host *host = mmc_priv(mmc);
554
555	if (mmc->clock)
556	sh_mmcif_clock_control(host, mmc->clock);
557
558	if (mmc->bus_width == 8)
559	host->bus_width = MMC_BUS_WIDTH_8;
560	else if (mmc->bus_width == 4)
561	host->bus_width = MMC_BUS_WIDTH_4;
562	else
563	host->bus_width = MMC_BUS_WIDTH_1;
564
565	debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
566	}
567
568	static int sh_mmcif_init(struct mmc *mmc)
569	{
570	struct sh_mmcif_host *host = mmc_priv(mmc);
571
572	sh_mmcif_sync_reset(host);
573	sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
574	return 0;
575	}
576
577	int mmcif_mmc_init(void)
578	{
579	int ret = 0;
580	struct mmc *mmc;
581	struct sh_mmcif_host *host = NULL;
582
583	mmc = malloc(sizeof(struct mmc));
584	if (!mmc)
585	ret = -ENOMEM;
586	memset(mmc, 0, sizeof(*mmc));
587	host = malloc(sizeof(struct sh_mmcif_host));
588	if (!host)
589	ret = -ENOMEM;
590	memset(host, 0, sizeof(*host));
591
592	mmc->f_min = CLKDEV_MMC_INIT;
593	mmc->f_max = CLKDEV_EMMC_DATA;
594	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
595	mmc->host_caps = MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT \|
97a7b992	596	MMC_MODE_8BIT \| MMC_MODE_HC;
afb35666 YS	597	memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
	598	mmc->send_cmd = sh_mmcif_request;
	599	mmc->set_ios = sh_mmcif_set_ios;
	600	mmc->init = sh_mmcif_init;
48972d90	601	mmc->getcd = NULL;
afb35666 YS	602	host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
	603	host->clk = CONFIG_SH_MMCIF_CLK;
	604	mmc->priv = host;
	605
	606	mmc_register(mmc);
	607
	608	return ret;
	609	}