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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
3 | * Copyright (C) 2013 Samsung Electronics | |
4 | * Sanghee Kim <[email protected]> | |
5 | * Piotr Wilczek <[email protected]> | |
6 | * | |
7 | * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. | |
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8 | */ |
9 | ||
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10 | #ifndef __CONFIG_TRATS2_H |
11 | #define __CONFIG_TRATS2_H | |
4d6c9671 | 12 | |
4c7bb1d2 | 13 | #include <configs/exynos4-common.h> |
4d6c9671 | 14 | |
1ecab0f3 | 15 | #define CONFIG_TIZEN /* TIZEN lib */ |
4d6c9671 | 16 | |
c4e96dbf | 17 | #define CONFIG_SYS_L2CACHE_OFF |
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18 | #ifndef CONFIG_SYS_L2CACHE_OFF |
19 | #define CONFIG_SYS_L2_PL310 | |
20 | #define CONFIG_SYS_PL310_BASE 0x10502000 | |
21 | #endif | |
22 | ||
1ecab0f3 | 23 | /* TRATS2 has 4 banks of DRAM */ |
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24 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
25 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
26 | #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ | |
27 | /* memtest works on */ | |
28 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
29 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
30 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
4d6c9671 | 31 | |
4d6c9671 | 32 | /* select serial console configuration */ |
4d6c9671 | 33 | |
1ecab0f3 | 34 | /* Console configuration */ |
4d6c9671 | 35 | |
1018b0a5 | 36 | #define CONFIG_BOOTCOMMAND "run autoboot" |
232ed3ca | 37 | #define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" |
4d6c9671 | 38 | |
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39 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ |
40 | - GENERATED_GBL_DATA_SIZE) | |
4d6c9671 | 41 | |
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42 | #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ |
43 | ||
44 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
45 | ||
1ecab0f3 PW |
46 | #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV |
47 | #define CONFIG_ENV_SIZE 4096 | |
48 | #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ | |
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49 | |
50 | #define CONFIG_ENV_OVERWRITE | |
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51 | |
52 | /* Tizen - partitions definitions */ | |
18f3e0eb | 53 | #define PARTS_CSA "csa-mmc" |
4d6c9671 | 54 | #define PARTS_BOOT "boot" |
18f3e0eb | 55 | #define PARTS_QBOOT "qboot" |
dca36684 | 56 | #define PARTS_CSC "csc" |
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57 | #define PARTS_ROOT "platform" |
58 | #define PARTS_DATA "data" | |
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59 | #define PARTS_UMS "ums" |
60 | ||
61 | #define PARTS_DEFAULT \ | |
a5e15bbb | 62 | "uuid_disk=${uuid_gpt_disk};" \ |
dca36684 | 63 | "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ |
18f3e0eb PM |
64 | "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ |
65 | "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ | |
4d6c9671 | 66 | "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ |
dca36684 | 67 | "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ |
18f3e0eb | 68 | "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ |
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69 | "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ |
70 | ||
09f98010 | 71 | #define CONFIG_DFU_ALT \ |
b7d4259a | 72 | "u-boot raw 0x80 0x800;" \ |
dcb7eb66 ŁM |
73 | "/uImage ext4 0 2;" \ |
74 | "/modem.bin ext4 0 2;" \ | |
75 | "/exynos4412-trats2.dtb ext4 0 2;" \ | |
18f3e0eb | 76 | ""PARTS_CSA" part 0 1;" \ |
cdd15bce | 77 | ""PARTS_BOOT" part 0 2;" \ |
18f3e0eb PM |
78 | ""PARTS_QBOOT" part 0 3;" \ |
79 | ""PARTS_CSC" part 0 4;" \ | |
cdd15bce ŁM |
80 | ""PARTS_ROOT" part 0 5;" \ |
81 | ""PARTS_DATA" part 0 6;" \ | |
a0afc6f3 | 82 | ""PARTS_UMS" part 0 7;" \ |
1018b0a5 ŁM |
83 | "params.bin raw 0x38 0x8;" \ |
84 | "/Image.itb ext4 0 2\0" | |
09f98010 | 85 | |
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86 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
87 | "bootk=" \ | |
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88 | "run loaduimage;" \ |
89 | "if run loaddtb; then " \ | |
90 | "bootm 0x40007FC0 - ${fdtaddr};" \ | |
91 | "fi;" \ | |
92 | "bootm 0x40007FC0;\0" \ | |
4d6c9671 | 93 | "updatebackup=" \ |
188c42b3 JC |
94 | "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ |
95 | " mmc dev 0 0\0" \ | |
4d6c9671 | 96 | "updatebootb=" \ |
188c42b3 | 97 | "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ |
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98 | "mmcboot=" \ |
99 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
100 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ | |
425e26de | 101 | "run bootk\0" \ |
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102 | "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ |
103 | "boottrace=setenv opts initcall_debug; run bootcmd\0" \ | |
104 | "verify=n\0" \ | |
105 | "rootfstype=ext4\0" \ | |
232ed3ca | 106 | "console=" CONFIG_DEFAULT_CONSOLE "\0" \ |
4d6c9671 | 107 | "kernelname=uImage\0" \ |
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108 | "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ |
109 | "${kernelname}\0" \ | |
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110 | "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ |
111 | "${fdtfile}\0" \ | |
a5e15bbb | 112 | "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ |
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113 | "mmcbootpart=2\0" \ |
114 | "mmcrootpart=5\0" \ | |
115 | "opts=always_resume=1\0" \ | |
116 | "partitions=" PARTS_DEFAULT \ | |
09f98010 | 117 | "dfu_alt_info=" CONFIG_DFU_ALT \ |
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118 | "uartpath=ap\0" \ |
119 | "usbpath=ap\0" \ | |
120 | "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ | |
121 | "consoleoff=set console console=ram; save; reset\0" \ | |
122 | "spladdr=0x40000100\0" \ | |
123 | "splsize=0x200\0" \ | |
124 | "splfile=falcon.bin\0" \ | |
125 | "spl_export=" \ | |
126 | "setexpr spl_imgsize ${splsize} + 8 ;" \ | |
127 | "setenv spl_imgsize 0x${spl_imgsize};" \ | |
128 | "setexpr spl_imgaddr ${spladdr} - 8 ;" \ | |
129 | "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ | |
130 | "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ | |
131 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
132 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ | |
133 | "spl export atags 0x40007FC0;" \ | |
134 | "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ | |
135 | "mw.l ${spl_addr_tmp} ${splsize};" \ | |
136 | "ext4write mmc ${mmcdev}:${mmcbootpart}" \ | |
137 | " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ | |
138 | "setenv spl_imgsize;" \ | |
139 | "setenv spl_imgaddr;" \ | |
140 | "setenv spl_addr_tmp;\0" \ | |
1018b0a5 | 141 | CONFIG_EXTRA_ENV_ITB \ |
4d6c9671 | 142 | "fdtaddr=40800000\0" \ |
4d6c9671 | 143 | |
519fdde9 | 144 | /* GPT */ |
4d6c9671 | 145 | |
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146 | /* Security subsystem - enable hw_rand() */ |
147 | #define CONFIG_EXYNOS_ACE_SHA | |
e0021706 | 148 | |
679549d1 PM |
149 | /* Common misc for Samsung */ |
150 | #define CONFIG_MISC_COMMON | |
151 | ||
f64236a9 PM |
152 | /* Download menu - Samsung common */ |
153 | #define CONFIG_LCD_MENU | |
f64236a9 PM |
154 | |
155 | /* Download menu - definitions for check keys */ | |
156 | #ifndef __ASSEMBLY__ | |
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157 | |
158 | #define KEY_PWR_PMIC_NAME "MAX77686_PMIC" | |
159 | #define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 | |
160 | #define KEY_PWR_STATUS_MASK (1 << 0) | |
161 | #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 | |
162 | #define KEY_PWR_INTERRUPT_MASK (1 << 1) | |
163 | ||
9b97b727 AS |
164 | #define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 |
165 | #define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 | |
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166 | #endif /* __ASSEMBLY__ */ |
167 | ||
168 | /* LCD console */ | |
169 | #define LCD_BPP LCD_COLOR16 | |
f64236a9 | 170 | |
4d6c9671 | 171 | /* LCD */ |
2df21cb3 | 172 | #define CONFIG_BMP_16BPP |
4d6c9671 | 173 | #define CONFIG_FB_ADDR 0x52504000 |
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174 | #define CONFIG_EXYNOS_MIPI_DSIM |
175 | #define CONFIG_VIDEO_BMP_GZIP | |
903afe18 | 176 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) |
4d6c9671 | 177 | |
4d6c9671 | 178 | #endif /* __CONFIG_H */ |