[J-u-boot.git] / include / configs / sh7757lcr.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the sh7757lcr board
 *
 * Copyright (C) 2011 Renesas Solutions Corp.
 */

#ifndef __SH7757LCR_H
#define __SH7757LCR_H

#define CONFIG_CPU_SH7757	1
#define CONFIG_SH7757LCR_DDR_ECC	1

#define CONFIG_DISPLAY_BOARDINFO
#undef	CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define SH7757LCR_SDRAM_BASE		(0x80000000)
#define SH7757LCR_SDRAM_SIZE		(240 * 1024 * 1024)
#define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
#define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)

#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_CONS_SCIF2	1

#define CONFIG_SYS_MEMTEST_START	(SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					 224 * 1024 * 1024)
#undef	CONFIG_SYS_MEMTEST_SCRATCH
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE		(SH7757LCR_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
					 (128 + 16) * 1024 * 1024)

#define CONFIG_SYS_MONITOR_BASE		0x00000000
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

#define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
#define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
#define SH7757LCR_ETHERNET_MAC_BASE	SH7757LCR_ETHERNET_MAC_BASE_SPI
#define SH7757LCR_ETHERNET_MAC_SIZE	17
#define SH7757LCR_ETHERNET_NUM_CH	2

/* Gigabit Ether */
#define SH7757LCR_GIGA_ETHERNET_NUM_CH	2

/* SPI */
#define CONFIG_SH_SPI_BASE		0xfe002000

/* MMCIF */
#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
#define CONFIG_SH_MMCIF_CLK		48000000

/* SH7757 board */
#define SH7757LCR_SDRAM_PHYS_TOP	0x40000000
#define SH7757LCR_GRA_OFFSET		0x1f000000
#define SH7757LCR_PCIEBRG_ADDR_B0	0x000a0000
#define SH7757LCR_PCIEBRG_SIZE_B0	(64 * 1024)
#define SH7757LCR_PCIEBRG_ADDR		0x00090000
#define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)

/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_ADDR		(0x00080000)
#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS				\
		"netboot=bootp; bootm\0"

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	48000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV	4
#endif	/* __SH7757LCR_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
8e9c897b YS	2	/*
	3	* Configuation settings for the sh7757lcr board
	4	*
	5	* Copyright (C) 2011 Renesas Solutions Corp.
8e9c897b YS	6	*/
	7
	8	#ifndef __SH7757LCR_H
	9	#define __SH7757LCR_H
	10
8e9c897b	11	#define CONFIG_CPU_SH7757 1
3ed81645	12	#define CONFIG_SH7757LCR_DDR_ECC 1
8e9c897b	13
18a40e84	14	#define CONFIG_DISPLAY_BOARDINFO
8e9c897b YS	15	#undef CONFIG_SHOW_BOOT_PROGRESS
	16
	17	/* MEMORY */
	18	#define SH7757LCR_SDRAM_BASE (0x80000000)
	19	#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
	20	#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
	21	#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
	22
8e9c897b	23	#define CONFIG_SYS_PBSIZE 256
8e9c897b YS	24	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	25
	26	/* SCIF */
8e9c897b	27	#define CONFIG_CONS_SCIF2 1
8e9c897b YS	28
	29	#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
	30	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	31	224 * 1024 * 1024)
8e9c897b YS	32	#undef CONFIG_SYS_MEMTEST_SCRATCH
	33	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	34
	35	#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
	36	#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
	37	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
	38	(128 + 16) * 1024 * 1024)
	39
	40	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	41	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	42	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	43	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	44
8e9c897b	45	/* Ether */
8e9c897b YS	46	#define CONFIG_SH_ETHER_USE_PORT 0
	47	#define CONFIG_SH_ETHER_PHY_ADDR 1
	48	#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
0c2a37a5 YS	49	#define CONFIG_BITBANGMII
0c2a37a5 YS	50	#define CONFIG_BITBANGMII_MULTI
a80a6619	51	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
8e9c897b YS	52
	53	#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
	54	#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
	55	#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
	56	#define SH7757LCR_ETHERNET_MAC_SIZE 17
	57	#define SH7757LCR_ETHERNET_NUM_CH 2
8e9c897b YS	58
	59	/* Gigabit Ether */
	60	#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
	61
	62	/* SPI */
8e9c897b	63	#define CONFIG_SH_SPI_BASE 0xfe002000
8e9c897b	64
566f63d5	65	/* MMCIF */
566f63d5 YS	66	#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
	67	#define CONFIG_SH_MMCIF_CLK 48000000
	68
8e9c897b YS	69	/* SH7757 board */
	70	#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
	71	#define SH7757LCR_GRA_OFFSET 0x1f000000
	72	#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
	73	#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
	74	#define SH7757LCR_PCIEBRG_ADDR 0x00090000
	75	#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
	76
	77	/* ENV setting */
	78	#define CONFIG_ENV_IS_EMBEDDED
8e9c897b YS	79	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	80	#define CONFIG_ENV_ADDR (0x00080000)
	81	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
	82	#define CONFIG_ENV_OVERWRITE 1
	83	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	84	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	85	#define CONFIG_EXTRA_ENV_SETTINGS \
	86	"netboot=bootp; bootm\0"
	87
	88	/* Board Clock */
	89	#define CONFIG_SYS_CLK_FREQ 48000000
684a501e NI	90	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	91	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
8e9c897b	92	#define CONFIG_SYS_TMU_CLK_DIV 4
8e9c897b	93	#endif /* __SH7757LCR_H */