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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
3 | * Copyright (C) 2015 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * Configuration settings for the Freescale i.MX7. | |
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6 | */ |
7 | ||
8 | #ifndef __MX7_COMMON_H | |
9 | #define __MX7_COMMON_H | |
10 | ||
11 | #include <linux/sizes.h> | |
12 | #include <asm/arch/imx-regs.h> | |
552a848e | 13 | #include <asm/mach-imx/gpio.h> |
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14 | |
15 | #ifndef CONFIG_MX7 | |
16 | #define CONFIG_MX7 | |
17 | #endif | |
18 | ||
19 | /* Timer settings */ | |
20 | #define CONFIG_MXC_GPT_HCLK | |
1a8150d4 | 21 | #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ |
e4916e85 | 22 | #define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK |
18fb0e3c | 23 | #define CONFIG_SYS_FSL_CLK |
1a8150d4 | 24 | |
1ecd2eaa PF |
25 | #define CONFIG_SYS_BOOTM_LEN 0x1000000 |
26 | ||
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27 | /* Enable iomux-lpsr support */ |
28 | #define CONFIG_IOMUX_LPSR | |
1a8150d4 | 29 | |
1a8150d4 | 30 | #define CONFIG_LOADADDR 0x80800000 |
1a8150d4 | 31 | |
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32 | /* allow to overwrite serial and ethaddr */ |
33 | #define CONFIG_ENV_OVERWRITE | |
1a8150d4 | 34 | |
1a8150d4 | 35 | /* Miscellaneous configurable options */ |
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36 | #define CONFIG_SYS_CBSIZE 512 |
37 | #define CONFIG_SYS_MAXARGS 32 | |
1a8150d4 | 38 | |
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39 | /* UART */ |
40 | #define CONFIG_MXC_UART | |
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41 | |
42 | /* MMC */ | |
1a8150d4 | 43 | #define CONFIG_BOUNCE_BUFFER |
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44 | #define CONFIG_FSL_USDHC |
45 | ||
46 | /* Fuses */ | |
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47 | #define CONFIG_MXC_OCOTP |
48 | ||
90ab4be1 | 49 | #define CONFIG_ARMV7_SECURE_BASE 0x00900000 |
90ab4be1 | 50 | |
0ec3d98f AH |
51 | #define CONFIG_ARMV7_PSCI_1_0 |
52 | ||
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53 | /* Secure boot (HAB) support */ |
54 | #ifdef CONFIG_SECURE_BOOT | |
55 | #define CONFIG_CSF_SIZE 0x2000 | |
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56 | #ifdef CONFIG_SPL_BUILD |
57 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
58 | #endif | |
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59 | #endif |
60 | ||
1a8150d4 | 61 | #endif |