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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
938080dc JL |
2 | /* |
3 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
4 | * Jason Liu <[email protected]> | |
5 | * | |
6 | * Configuration settings for Freescale MX53 low cost board. | |
938080dc JL |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
9df82896 FE |
12 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO |
13 | ||
938080dc JL |
14 | #include <asm/arch/imx-regs.h> |
15 | ||
16 | #define CONFIG_CMDLINE_TAG | |
938080dc JL |
17 | #define CONFIG_SETUP_MEMORY_TAGS |
18 | #define CONFIG_INITRD_TAG | |
19 | ||
18fb0e3c | 20 | #define CONFIG_SYS_FSL_CLK |
6ca896f9 | 21 | |
938080dc | 22 | /* Size of malloc() pool */ |
f714b0a9 | 23 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
938080dc | 24 | |
54cd1dee | 25 | #define CONFIG_REVISION_TAG |
938080dc JL |
26 | |
27 | #define CONFIG_MXC_UART | |
40f6fffe | 28 | #define CONFIG_MXC_UART_BASE UART1_BASE |
938080dc JL |
29 | |
30 | /* MMC Configs */ | |
938080dc JL |
31 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
32 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 | |
33 | ||
938080dc | 34 | /* Eth Configs */ |
938080dc JL |
35 | |
36 | #define CONFIG_FEC_MXC | |
37 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
38 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
39 | ||
45cf6ada | 40 | /* USB Configs */ |
45cf6ada | 41 | #define CONFIG_USB_EHCI_MX5 |
45cf6ada WG |
42 | #define CONFIG_MXC_USB_PORT 1 |
43 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
44 | #define CONFIG_MXC_USB_FLAGS 0 | |
45 | ||
e7e33722 | 46 | /* I2C Configs */ |
b089d039 | 47 | #define CONFIG_SYS_I2C |
48 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
49 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
50 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 51 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
e7e33722 FE |
52 | |
53 | /* PMIC Controller */ | |
be3b51aa ŁM |
54 | #define CONFIG_POWER |
55 | #define CONFIG_POWER_I2C | |
2988e866 | 56 | #define CONFIG_DIALOG_POWER |
be3b51aa | 57 | #define CONFIG_POWER_FSL |
913702ca | 58 | #define CONFIG_POWER_FSL_MC13892 |
e7e33722 | 59 | #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 |
5b547f3c | 60 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 |
e7e33722 | 61 | |
938080dc JL |
62 | /* allow to overwrite serial and ethaddr */ |
63 | #define CONFIG_ENV_OVERWRITE | |
938080dc JL |
64 | |
65 | /* Command definition */ | |
938080dc | 66 | |
938080dc | 67 | |
28b119e9 | 68 | #define CONFIG_ETHPRIME "FEC0" |
938080dc | 69 | |
fe51f787 | 70 | #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ |
938080dc JL |
71 | |
72 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
73 | "script=boot.scr\0" \ | |
f28154b5 | 74 | "image=zImage\0" \ |
e0df5353 OS |
75 | "fdt_addr=0x71000000\0" \ |
76 | "boot_fdt=try\0" \ | |
77 | "ip_dyn=yes\0" \ | |
938080dc | 78 | "mmcdev=0\0" \ |
254fd8da OS |
79 | "mmcpart=1\0" \ |
80 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ | |
e0df5353 | 81 | "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ |
938080dc | 82 | "loadbootscript=" \ |
54e0f96f | 83 | "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
938080dc JL |
84 | "bootscript=echo Running bootscript from mmc ...; " \ |
85 | "source\0" \ | |
54e0f96f GG |
86 | "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
87 | "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
938080dc JL |
88 | "mmcboot=echo Booting from mmc ...; " \ |
89 | "run mmcargs; " \ | |
e0df5353 OS |
90 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
91 | "if run loadfdt; then " \ | |
f28154b5 | 92 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
e0df5353 OS |
93 | "else " \ |
94 | "if test ${boot_fdt} = try; then " \ | |
f28154b5 | 95 | "bootz; " \ |
e0df5353 OS |
96 | "else " \ |
97 | "echo WARN: Cannot load the DT; " \ | |
98 | "fi; " \ | |
99 | "fi; " \ | |
100 | "else " \ | |
f28154b5 | 101 | "bootz; " \ |
e0df5353 | 102 | "fi;\0" \ |
938080dc JL |
103 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ |
104 | "root=/dev/nfs " \ | |
105 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
106 | "netboot=echo Booting from net ...; " \ | |
107 | "run netargs; " \ | |
e0df5353 OS |
108 | "if test ${ip_dyn} = yes; then " \ |
109 | "setenv get_cmd dhcp; " \ | |
110 | "else " \ | |
111 | "setenv get_cmd tftp; " \ | |
112 | "fi; " \ | |
f28154b5 | 113 | "${get_cmd} ${image}; " \ |
e0df5353 OS |
114 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
115 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
f28154b5 | 116 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
e0df5353 OS |
117 | "else " \ |
118 | "if test ${boot_fdt} = try; then " \ | |
f28154b5 | 119 | "bootz; " \ |
e0df5353 OS |
120 | "else " \ |
121 | "echo ERROR: Cannot load the DT; " \ | |
122 | "exit; " \ | |
123 | "fi; " \ | |
124 | "fi; " \ | |
125 | "else " \ | |
f28154b5 | 126 | "bootz; " \ |
e0df5353 | 127 | "fi;\0" |
938080dc JL |
128 | |
129 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 130 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
938080dc JL |
131 | "if run loadbootscript; then " \ |
132 | "run bootscript; " \ | |
133 | "else " \ | |
f28154b5 | 134 | "if run loadimage; then " \ |
938080dc JL |
135 | "run mmcboot; " \ |
136 | "else run netboot; " \ | |
137 | "fi; " \ | |
138 | "fi; " \ | |
139 | "else run netboot; fi" | |
140 | ||
141 | #define CONFIG_ARP_TIMEOUT 200UL | |
142 | ||
143 | /* Miscellaneous configurable options */ | |
e0df5353 | 144 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
938080dc | 145 | |
938080dc JL |
146 | #define CONFIG_SYS_MEMTEST_START 0x70000000 |
147 | #define CONFIG_SYS_MEMTEST_END 0x70010000 | |
148 | ||
149 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
150 | ||
938080dc | 151 | /* Physical Memory Map */ |
31c832f9 MV |
152 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
153 | #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) | |
154 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
155 | #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) | |
156 | #define PHYS_SDRAM_SIZE (gd->ram_size) | |
938080dc JL |
157 | |
158 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
159 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
160 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
161 | ||
162 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
163 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
164 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
165 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
166 | ||
e856bdcf | 167 | /* environment organization */ |
938080dc JL |
168 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
169 | #define CONFIG_ENV_SIZE (8 * 1024) | |
938080dc JL |
170 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
171 | ||
f92e4e6c | 172 | #ifdef CONFIG_CMD_SATA |
f92e4e6c SB |
173 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
174 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
175 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR | |
176 | #define CONFIG_LBA48 | |
f92e4e6c SB |
177 | #endif |
178 | ||
f714b0a9 FE |
179 | /* Framebuffer and LCD */ |
180 | #define CONFIG_PREBOOT | |
695af9ab | 181 | #define CONFIG_VIDEO_IPUV3 |
f714b0a9 FE |
182 | #define CONFIG_VIDEO_BMP_RLE8 |
183 | #define CONFIG_SPLASH_SCREEN | |
184 | #define CONFIG_BMP_16BPP | |
185 | #define CONFIG_VIDEO_LOGO | |
186 | ||
938080dc | 187 | #endif /* __CONFIG_H */ |