[J-u-boot.git] / include / configs / mpr2.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for MPR2
 *
 * Copyright (C) 2008
 * Mark Jonas <[email protected]>
 */

#ifndef __MPR2_H
#define __MPR2_H

/* Supported commands */

/* Default environment variables */
#define CONFIG_BOOTFILE		"/boot/zImage"
#define CONFIG_LOADADDR		0x8E000000

/* CPU and platform */
#define CONFIG_CPU_SH7720	1

#define CONFIG_DISPLAY_BOARDINFO

/* U-Boot internals */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)

/* Memory */
#define CONFIG_SYS_SDRAM_BASE		0x8C000000
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Flash */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BASE		0xA0000000
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Clocks */
#define CONFIG_SYS_CLK_FREQ	24000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */

/* UART */
#define CONFIG_CONS_SCIF0	1

#endif	/* __MPR2_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
3313e0e2 MJ	2	/*
	3	* Configuation settings for MPR2
	4	*
	5	* Copyright (C) 2008
	6	* Mark Jonas <[email protected]>
3313e0e2 MJ	7	*/
	8
	9	#ifndef __MPR2_H
	10	#define __MPR2_H
	11
	12	/* Supported commands */
3313e0e2 MJ	13
3313e0e2 MJ	14	/* Default environment variables */
b3f44c21	15	#define CONFIG_BOOTFILE "/boot/zImage"
3313e0e2	16	#define CONFIG_LOADADDR 0x8E000000
3313e0e2 MJ	17
3313e0e2 MJ	18	/* CPU and platform */
3313e0e2	19	#define CONFIG_CPU_SH7720 1
3313e0e2	20
18a40e84 VZ	21	#define CONFIG_DISPLAY_BOARDINFO
18a40e84 VZ	22
3313e0e2	23	/* U-Boot internals */
6d0f6bcf JCPV	24	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
	25	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
	26	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	27	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	28	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
3313e0e2 MJ	29
3313e0e2 MJ	30	/* Memory */
6d0f6bcf JCPV	31	#define CONFIG_SYS_SDRAM_BASE 0x8C000000
	32	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
	33	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	34	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
3313e0e2 MJ	35
3313e0e2 MJ	36	/* Flash */
6d0f6bcf	37	#define CONFIG_SYS_FLASH_CFI
00b1883a	38	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	39	#define CONFIG_SYS_FLASH_EMPTY_INFO
	40	#define CONFIG_SYS_FLASH_BASE 0xA0000000
	41	#define CONFIG_SYS_MAX_FLASH_SECT 256
	42	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	43	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
0e8d1586 JCPV	44	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 JCPV	45	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
6d0f6bcf JCPV	46	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	47	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
	48	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
3313e0e2 MJ	49
	50	/* Clocks */
	51	#define CONFIG_SYS_CLK_FREQ 24000000
684a501e NI	52	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	53	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	54	#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
3313e0e2 MJ	55
3313e0e2 MJ	56	/* UART */
3313e0e2 MJ	57	#define CONFIG_CONS_SCIF0 1
	58
	59	#endif /* __MPR2_H */