[J-u-boot.git] / include / configs / P5020DS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2009-2011 Freescale Semiconductor, Inc.
 */

/*
 * P5020 DS board configuration file
 * Also supports P5010 DS
 */
#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */

#define CONFIG_NAND_FSL_ELBC
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_DPAA_RMAN

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */
#define CONFIG_SRIO2			/* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */

#include "corenet_ds.h"
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
e02aea61 KG	2	/*
e02aea61 KG	3	* Copyright 2009-2011 Freescale Semiconductor, Inc.
e02aea61 KG	4	*/
	5
	6	/*
	7	* P5020 DS board configuration file
3e978f5d	8	* Also supports P5010 DS
e02aea61	9	*/
c6d33901 KG	10	#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
c6d33901 KG	11
c6d33901	12	#define CONFIG_NAND_FSL_ELBC
9760b274	13	#define CONFIG_FSL_SATA_V2
c6d33901	14	#define CONFIG_PCIE3
e02aea61	15	#define CONFIG_PCIE4
6b3a8d00	16	#define CONFIG_SYS_FSL_RAID_ENGINE
4d28db8a	17	#define CONFIG_SYS_DPAA_RMAN
e02aea61	18
11860d88 TT	19	#define CONFIG_SYS_SRIO
	20	#define CONFIG_SRIO1 /* SRIO port 1 */
	21	#define CONFIG_SRIO2 /* SRIO port 2 */
c8b28152	22	#define CONFIG_SRIO_PCIE_BOOT_MASTER
e02aea61 KG	23	#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
	24
	25	#include "corenet_ds.h"