[J-u-boot.git] / common / cmd_eeprom.c

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Support for read and write access to EEPROM like memory devices. This
 * includes regular EEPROM as well as  FRAM (ferroelectic nonvolaile RAM).
 * FRAM devices read and write data at bus speed. In particular, there is no
 * write delay. Also, there is no limit imposed on the number of bytes that can
 * be transferred with a single read or write.
 *
 * Use the following configuration options to ensure no unneeded performance
 * degradation (typical for EEPROM) is incured for FRAM memory:
 *
 * #define CONFIG_SYS_I2C_FRAM
 * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
 *
 */

#include <common.h>
#include <config.h>
#include <command.h>
#include <i2c.h>

extern void eeprom_init  (void);
extern int  eeprom_read  (unsigned dev_addr, unsigned offset,
			  uchar *buffer, unsigned cnt);
extern int  eeprom_write (unsigned dev_addr, unsigned offset,
			  uchar *buffer, unsigned cnt);
#if defined(CONFIG_SYS_EEPROM_WREN)
extern int eeprom_write_enable (unsigned dev_addr, int state);
#endif


#if defined(CONFIG_SYS_EEPROM_X40430)
	/* Maximum number of times to poll for acknowledge after write */
#define MAX_ACKNOWLEDGE_POLLS	10
#endif

/* ------------------------------------------------------------------------- */

#if defined(CONFIG_CMD_EEPROM)
int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	const char *const fmt =
		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";

#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
	if (argc == 6) {
		ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
		ulong addr = simple_strtoul (argv[3], NULL, 16);
		ulong off  = simple_strtoul (argv[4], NULL, 16);
		ulong cnt  = simple_strtoul (argv[5], NULL, 16);
#else
	if (argc == 5) {
		ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
		ulong addr = simple_strtoul (argv[2], NULL, 16);
		ulong off  = simple_strtoul (argv[3], NULL, 16);
		ulong cnt  = simple_strtoul (argv[4], NULL, 16);
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */

# if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		eeprom_init ();
# endif /* !CONFIG_SPI */

		if (strcmp (argv[1], "read") == 0) {
			int rcode;

			printf (fmt, dev_addr, argv[1], addr, off, cnt);

			rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);

			puts ("done\n");
			return rcode;
		} else if (strcmp (argv[1], "write") == 0) {
			int rcode;

			printf (fmt, dev_addr, argv[1], addr, off, cnt);

			rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);

			puts ("done\n");
			return rcode;
		}
	}

	return CMD_RET_USAGE;
}
#endif

/*-----------------------------------------------------------------------
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
 *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
 *   0x00000nxx for EEPROM address selectors and page number at n.
 */

#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
#endif
#endif

int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
	unsigned end = offset + cnt;
	unsigned blk_off;
	int rcode = 0;

	/* Read data until done or would cross a page boundary.
	 * We must write the address again when changing pages
	 * because the next page may be in a different device.
	 */
	while (offset < end) {
		unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
		unsigned maxlen;
#endif

#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
		uchar addr[2];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 8;		/* block number */
		addr[1] = blk_off;		/* block offset */
		alen	= 2;
#else
		uchar addr[3];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 16;		/* block number */
		addr[1] = offset >>  8;		/* upper address octet */
		addr[2] = blk_off;		/* lower address octet */
		alen	= 3;
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

		addr[0] |= dev_addr;		/* insert device address */

		len = end - offset;

		/*
		 * For a FRAM device there is no limit on the number of the
		 * bytes that can be ccessed with the single read or write
		 * operation.
		 */
#if !defined(CONFIG_SYS_I2C_FRAM)
		maxlen = 0x100 - blk_off;
		if (maxlen > I2C_RXTX_LEN)
			maxlen = I2C_RXTX_LEN;
		if (len > maxlen)
			len = maxlen;
#endif

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		spi_read (addr, alen, buffer, len);
#else
		if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
			rcode = 1;
#endif
		buffer += len;
		offset += len;
	}

	return rcode;
}

/*-----------------------------------------------------------------------
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
 *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
 *   0x00000nxx for EEPROM address selectors and page number at n.
 */

int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
	unsigned end = offset + cnt;
	unsigned blk_off;
	int rcode = 0;

#if defined(CONFIG_SYS_EEPROM_X40430)
	uchar	contr_r_addr[2];
	uchar	addr_void[2];
	uchar	contr_reg[2];
	uchar	ctrl_reg_v;
	int	i;
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
	eeprom_write_enable (dev_addr,1);
#endif
	/* Write data until done or would cross a write page boundary.
	 * We must write the address again when changing pages
	 * because the address counter only increments within a page.
	 */

	while (offset < end) {
		unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
		unsigned maxlen;
#endif

#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
		uchar addr[2];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 8;		/* block number */
		addr[1] = blk_off;		/* block offset */
		alen	= 2;
#else
		uchar addr[3];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 16;		/* block number */
		addr[1] = offset >>  8;		/* upper address octet */
		addr[2] = blk_off;		/* lower address octet */
		alen	= 3;
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

		addr[0] |= dev_addr;		/* insert device address */

		len = end - offset;

		/*
		 * For a FRAM device there is no limit on the number of the
		 * bytes that can be accessed with the single read or write
		 * operation.
		 */
#if !defined(CONFIG_SYS_I2C_FRAM)

#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)

#define	EEPROM_PAGE_SIZE	(1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
#define	EEPROM_PAGE_OFFSET(x)	((x) & (EEPROM_PAGE_SIZE - 1))

		maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
#else
		maxlen = 0x100 - blk_off;
#endif
		if (maxlen > I2C_RXTX_LEN)
			maxlen = I2C_RXTX_LEN;

		if (len > maxlen)
			len = maxlen;
#endif

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		spi_write (addr, alen, buffer, len);
#else
#if defined(CONFIG_SYS_EEPROM_X40430)
		/* Get the value of the control register.
		 * Set current address (internal pointer in the x40430)
		 * to 0x1ff.
		 */
		contr_r_addr[0] = 9;
		contr_r_addr[1] = 0xff;
		addr_void[0]    = 0;
		addr_void[1]    = addr[1];
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
		contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
		addr_void[0]    |= CONFIG_SYS_I2C_EEPROM_ADDR;
#endif
		contr_reg[0] = 0xff;
		if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
			rcode = 1;
		}
		ctrl_reg_v = contr_reg[0];

		/* Are any of the eeprom blocks write protected?
		 */
		if (ctrl_reg_v & 0x18) {
			ctrl_reg_v &= ~0x18;   /* reset block protect bits  */
			ctrl_reg_v |=  0x02;   /* set write enable latch    */
			ctrl_reg_v &= ~0x04;   /* clear RWEL                */

			/* Set write enable latch.
			 */
			contr_reg[0] = 0x02;
			if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* Set register write enable latch.
			 */
			contr_reg[0] = 0x06;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* Modify ctrl register.
			 */
			contr_reg[0] = ctrl_reg_v;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* The write (above) is an operation on NV memory.
			 * These can take some time (~5ms), and the device
			 * will not respond to further I2C messages till
			 * it's completed the write.
			 * So poll device for an I2C acknowledge.
			 * When we get one we know we can continue with other
			 * operations.
			 */
			contr_reg[0] = 0;
			for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
				if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
					break;	/* got ack */
#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
				udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
			}
			if (i == MAX_ACKNOWLEDGE_POLLS) {
				puts ("EEPROM poll acknowledge failed\n");
				rcode = 1;
			}
		}

		/* Is the write enable latch on?.
		 */
		else if (!(ctrl_reg_v & 0x02)) {
			/* Set write enable latch.
			 */
			contr_reg[0] = 0x02;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
			       rcode = 1;
			}
		}
		/* Write is enabled ... now write eeprom value.
		 */
#endif
		if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
			rcode = 1;

#endif
		buffer += len;
		offset += len;

#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
	}
#if defined(CONFIG_SYS_EEPROM_WREN)
	eeprom_write_enable (dev_addr,0);
#endif
	return rcode;
}

#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
int
eeprom_probe (unsigned dev_addr, unsigned offset)
{
	unsigned char chip;

	/* Probe the chip address
	 */
#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
	chip = offset >> 8;		/* block number */
#else
	chip = offset >> 16;		/* block number */
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

	chip |= dev_addr;		/* insert device address */

	return (i2c_probe (chip));
}
#endif

/*-----------------------------------------------------------------------
 * Set default values
 */
#ifndef	CONFIG_SYS_I2C_SPEED
#define	CONFIG_SYS_I2C_SPEED	50000
#endif

void eeprom_init  (void)
{

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
	spi_init_f ();
#endif
#if defined(CONFIG_HARD_I2C) || \
    defined(CONFIG_SOFT_I2C)
	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}

/*-----------------------------------------------------------------------
 */

/***************************************************/

#if defined(CONFIG_CMD_EEPROM)

#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
U_BOOT_CMD(
	eeprom,	6,	1,	do_eeprom,
	"EEPROM sub-system",
	"read  devaddr addr off cnt\n"
	"eeprom write devaddr addr off cnt\n"
	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
);
#else /* One EEPROM */
U_BOOT_CMD(
	eeprom,	5,	1,	do_eeprom,
	"EEPROM sub-system",
	"read  addr off cnt\n"
	"eeprom write addr off cnt\n"
	"       - read/write `cnt' bytes at EEPROM offset `off'"
);
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */

#endif
Commit	Line	Data
3863585b WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
3863585b WD	6	*/
3863585b WD	7
d4f5c728	8	/*
	9	* Support for read and write access to EEPROM like memory devices. This
	10	* includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
	11	* FRAM devices read and write data at bus speed. In particular, there is no
e506a006	12	* write delay. Also, there is no limit imposed on the number of bytes that can
d4f5c728	13	* be transferred with a single read or write.
6617aae9	14	*
d4f5c728	15	* Use the following configuration options to ensure no unneeded performance
d4f5c728	16	* degradation (typical for EEPROM) is incured for FRAM memory:
6617aae9	17	*
6d0f6bcf JCPV	18	* #define CONFIG_SYS_I2C_FRAM
6d0f6bcf JCPV	19	* #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
d4f5c728	20	*
	21	*/
	22
3863585b WD	23	#include <common.h>
	24	#include <config.h>
	25	#include <command.h>
	26	#include <i2c.h>
	27
3863585b WD	28	extern void eeprom_init (void);
	29	extern int eeprom_read (unsigned dev_addr, unsigned offset,
	30	uchar *buffer, unsigned cnt);
	31	extern int eeprom_write (unsigned dev_addr, unsigned offset,
	32	uchar *buffer, unsigned cnt);
6d0f6bcf	33	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	34	extern int eeprom_write_enable (unsigned dev_addr, int state);
98f4a3df SR	35	#endif
3863585b WD	36
3863585b WD	37
6d0f6bcf	38	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	39	/* Maximum number of times to poll for acknowledge after write */
	40	#define MAX_ACKNOWLEDGE_POLLS 10
	41	#endif
	42
	43	/* ------------------------------------------------------------------------- */
	44
baa26db4	45	#if defined(CONFIG_CMD_EEPROM)
54841ab5	46	int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
3863585b WD	47	{
	48	const char *const fmt =
	49	"\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
	50
6d0f6bcf	51	#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
3863585b WD	52	if (argc == 6) {
	53	ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
	54	ulong addr = simple_strtoul (argv[3], NULL, 16);
	55	ulong off = simple_strtoul (argv[4], NULL, 16);
	56	ulong cnt = simple_strtoul (argv[5], NULL, 16);
	57	#else
	58	if (argc == 5) {
6d0f6bcf	59	ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
3863585b WD	60	ulong addr = simple_strtoul (argv[2], NULL, 16);
	61	ulong off = simple_strtoul (argv[3], NULL, 16);
	62	ulong cnt = simple_strtoul (argv[4], NULL, 16);
6d0f6bcf	63	#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
3863585b	64
548738b4	65	# if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	66	eeprom_init ();
	67	# endif /* !CONFIG_SPI */
	68
	69	if (strcmp (argv[1], "read") == 0) {
	70	int rcode;
	71
	72	printf (fmt, dev_addr, argv[1], addr, off, cnt);
	73
	74	rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
	75
4b9206ed	76	puts ("done\n");
3863585b WD	77	return rcode;
	78	} else if (strcmp (argv[1], "write") == 0) {
	79	int rcode;
	80
	81	printf (fmt, dev_addr, argv[1], addr, off, cnt);
	82
	83	rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
	84
4b9206ed	85	puts ("done\n");
3863585b WD	86	return rcode;
	87	}
	88	}
	89
4c12eeb8	90	return CMD_RET_USAGE;
3863585b	91	}
90253178	92	#endif
3863585b WD	93
	94	/*-----------------------------------------------------------------------
	95	*
6d0f6bcf	96	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
3863585b WD	97	* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
3863585b WD	98	*
6d0f6bcf	99	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
3863585b WD	100	* 0x00000nxx for EEPROM address selectors and page number at n.
	101	*/
	102
548738b4	103	#if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
6d0f6bcf JCPV	104	#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) \|\| CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 \|\| CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
6d0f6bcf JCPV	105	#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
3863585b WD	106	#endif
	107	#endif
	108
	109	int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
	110	{
	111	unsigned end = offset + cnt;
	112	unsigned blk_off;
	113	int rcode = 0;
	114
	115	/* Read data until done or would cross a page boundary.
	116	* We must write the address again when changing pages
	117	* because the next page may be in a different device.
	118	*/
	119	while (offset < end) {
d4f5c728	120	unsigned alen, len;
6d0f6bcf	121	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	122	unsigned maxlen;
	123	#endif
	124
6d0f6bcf	125	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
3863585b WD	126	uchar addr[2];
	127
	128	blk_off = offset & 0xFF; /* block offset */
	129
	130	addr[0] = offset >> 8; /* block number */
	131	addr[1] = blk_off; /* block offset */
	132	alen = 2;
	133	#else
	134	uchar addr[3];
	135
	136	blk_off = offset & 0xFF; /* block offset */
	137
	138	addr[0] = offset >> 16; /* block number */
	139	addr[1] = offset >> 8; /* upper address octet */
	140	addr[2] = blk_off; /* lower address octet */
	141	alen = 3;
6d0f6bcf	142	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
3863585b WD	143
	144	addr[0] \|= dev_addr; /* insert device address */
	145
d4f5c728	146	len = end - offset;
	147
	148	/*
	149	* For a FRAM device there is no limit on the number of the
	150	* bytes that can be ccessed with the single read or write
	151	* operation.
	152	*/
6d0f6bcf	153	#if !defined(CONFIG_SYS_I2C_FRAM)
3863585b WD	154	maxlen = 0x100 - blk_off;
	155	if (maxlen > I2C_RXTX_LEN)
	156	maxlen = I2C_RXTX_LEN;
3863585b WD	157	if (len > maxlen)
3863585b WD	158	len = maxlen;
d4f5c728	159	#endif
d4f5c728	160
548738b4	161	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	162	spi_read (addr, alen, buffer, len);
	163	#else
	164	if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
	165	rcode = 1;
	166	#endif
	167	buffer += len;
	168	offset += len;
	169	}
d4f5c728	170
3863585b WD	171	return rcode;
	172	}
	173
	174	/*-----------------------------------------------------------------------
	175	*
6d0f6bcf	176	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
3863585b WD	177	* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
3863585b WD	178	*
6d0f6bcf	179	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
3863585b WD	180	* 0x00000nxx for EEPROM address selectors and page number at n.
	181	*/
	182
	183	int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
	184	{
	185	unsigned end = offset + cnt;
	186	unsigned blk_off;
	187	int rcode = 0;
	188
6d0f6bcf	189	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	190	uchar contr_r_addr[2];
	191	uchar addr_void[2];
	192	uchar contr_reg[2];
	193	uchar ctrl_reg_v;
	194	int i;
	195	#endif
	196
6d0f6bcf	197	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	198	eeprom_write_enable (dev_addr,1);
98f4a3df SR	199	#endif
3863585b WD	200	/* Write data until done or would cross a write page boundary.
	201	* We must write the address again when changing pages
	202	* because the address counter only increments within a page.
	203	*/
	204
	205	while (offset < end) {
d4f5c728	206	unsigned alen, len;
6d0f6bcf	207	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	208	unsigned maxlen;
	209	#endif
	210
6d0f6bcf	211	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
3863585b WD	212	uchar addr[2];
	213
	214	blk_off = offset & 0xFF; /* block offset */
	215
	216	addr[0] = offset >> 8; /* block number */
	217	addr[1] = blk_off; /* block offset */
	218	alen = 2;
	219	#else
	220	uchar addr[3];
	221
	222	blk_off = offset & 0xFF; /* block offset */
	223
	224	addr[0] = offset >> 16; /* block number */
	225	addr[1] = offset >> 8; /* upper address octet */
	226	addr[2] = blk_off; /* lower address octet */
	227	alen = 3;
6d0f6bcf	228	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
3863585b WD	229
	230	addr[0] \|= dev_addr; /* insert device address */
	231
d4f5c728	232	len = end - offset;
	233
	234	/*
	235	* For a FRAM device there is no limit on the number of the
f9a78b8d	236	* bytes that can be accessed with the single read or write
d4f5c728	237	* operation.
d4f5c728	238	*/
6d0f6bcf	239	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	240
6d0f6bcf	241	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
3863585b	242
6d0f6bcf	243	#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
3863585b WD	244	#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
	245
	246	maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
	247	#else
	248	maxlen = 0x100 - blk_off;
	249	#endif
	250	if (maxlen > I2C_RXTX_LEN)
	251	maxlen = I2C_RXTX_LEN;
	252
3863585b WD	253	if (len > maxlen)
3863585b WD	254	len = maxlen;
d4f5c728	255	#endif
d4f5c728	256
548738b4	257	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	258	spi_write (addr, alen, buffer, len);
3863585b WD	259	#else
6d0f6bcf	260	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	261	/* Get the value of the control register.
	262	* Set current address (internal pointer in the x40430)
	263	* to 0x1ff.
	264	*/
	265	contr_r_addr[0] = 9;
	266	contr_r_addr[1] = 0xff;
	267	addr_void[0] = 0;
	268	addr_void[1] = addr[1];
6d0f6bcf JCPV	269	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
	270	contr_r_addr[0] \|= CONFIG_SYS_I2C_EEPROM_ADDR;
	271	addr_void[0] \|= CONFIG_SYS_I2C_EEPROM_ADDR;
3863585b WD	272	#endif
	273	contr_reg[0] = 0xff;
	274	if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
	275	rcode = 1;
	276	}
	277	ctrl_reg_v = contr_reg[0];
	278
	279	/* Are any of the eeprom blocks write protected?
	280	*/
	281	if (ctrl_reg_v & 0x18) {
	282	ctrl_reg_v &= ~0x18; /* reset block protect bits */
	283	ctrl_reg_v \|= 0x02; /* set write enable latch */
	284	ctrl_reg_v &= ~0x04; /* clear RWEL */
	285
	286	/* Set write enable latch.
	287	*/
	288	contr_reg[0] = 0x02;
	289	if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
	290	rcode = 1;
	291	}
	292
	293	/* Set register write enable latch.
	294	*/
	295	contr_reg[0] = 0x06;
	296	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	297	rcode = 1;
	298	}
	299
	300	/* Modify ctrl register.
	301	*/
	302	contr_reg[0] = ctrl_reg_v;
	303	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	304	rcode = 1;
	305	}
	306
	307	/* The write (above) is an operation on NV memory.
	308	* These can take some time (~5ms), and the device
	309	* will not respond to further I2C messages till
	310	* it's completed the write.
	311	* So poll device for an I2C acknowledge.
	312	* When we get one we know we can continue with other
	313	* operations.
	314	*/
	315	contr_reg[0] = 0;
	316	for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
aacf9a49	317	if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
3863585b	318	break; /* got ack */
6d0f6bcf JCPV	319	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
6d0f6bcf JCPV	320	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
3863585b WD	321	#endif
	322	}
	323	if (i == MAX_ACKNOWLEDGE_POLLS) {
4b9206ed	324	puts ("EEPROM poll acknowledge failed\n");
3863585b WD	325	rcode = 1;
	326	}
	327	}
	328
	329	/* Is the write enable latch on?.
	330	*/
	331	else if (!(ctrl_reg_v & 0x02)) {
	332	/* Set write enable latch.
	333	*/
	334	contr_reg[0] = 0x02;
	335	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	336	rcode = 1;
	337	}
	338	}
	339	/* Write is enabled ... now write eeprom value.
	340	*/
	341	#endif
	342	if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
	343	rcode = 1;
	344
	345	#endif
	346	buffer += len;
	347	offset += len;
	348
6d0f6bcf JCPV	349	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
6d0f6bcf JCPV	350	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
3863585b WD	351	#endif
3863585b WD	352	}
6d0f6bcf	353	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	354	eeprom_write_enable (dev_addr,0);
98f4a3df SR	355	#endif
3863585b WD	356	return rcode;
	357	}
	358
548738b4	359	#if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
6dd652fa WD	360	int
	361	eeprom_probe (unsigned dev_addr, unsigned offset)
	362	{
	363	unsigned char chip;
	364
	365	/* Probe the chip address
	366	*/
6d0f6bcf	367	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
6dd652fa WD	368	chip = offset >> 8; /* block number */
	369	#else
	370	chip = offset >> 16; /* block number */
6d0f6bcf	371	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
6dd652fa WD	372
	373	chip \|= dev_addr; /* insert device address */
	374
	375	return (i2c_probe (chip));
	376	}
	377	#endif
	378
3863585b WD	379	/*-----------------------------------------------------------------------
	380	* Set default values
	381	*/
6d0f6bcf JCPV	382	#ifndef CONFIG_SYS_I2C_SPEED
6d0f6bcf JCPV	383	#define CONFIG_SYS_I2C_SPEED 50000
3863585b WD	384	#endif
3863585b WD	385
3863585b WD	386	void eeprom_init (void)
3863585b WD	387	{
548738b4 HS	388
548738b4 HS	389	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	390	spi_init_f ();
	391	#endif
	392	#if defined(CONFIG_HARD_I2C) \|\| \
	393	defined(CONFIG_SOFT_I2C)
6d0f6bcf	394	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3863585b WD	395	#endif
3863585b WD	396	}
548738b4	397
3863585b WD	398	/*-----------------------------------------------------------------------
3863585b WD	399	*/
90253178	400
8bde7f77 WD	401	/***************************************************/
8bde7f77 WD	402
baa26db4	403	#if defined(CONFIG_CMD_EEPROM)
8bde7f77	404
6d0f6bcf	405	#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
0d498393 WD	406	U_BOOT_CMD(
0d498393 WD	407	eeprom, 6, 1, do_eeprom,
2fb2604d	408	"EEPROM sub-system",
8bde7f77 WD	409	"read devaddr addr off cnt\n"
8bde7f77 WD	410	"eeprom write devaddr addr off cnt\n"
a89c33db	411	" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
8bde7f77 WD	412	);
8bde7f77 WD	413	#else /* One EEPROM */
0d498393 WD	414	U_BOOT_CMD(
0d498393 WD	415	eeprom, 5, 1, do_eeprom,
2fb2604d	416	"EEPROM sub-system",
8bde7f77 WD	417	"read addr off cnt\n"
8bde7f77 WD	418	"eeprom write addr off cnt\n"
a89c33db	419	" - read/write `cnt' bytes at EEPROM offset `off'"
8bde7f77	420	);
6d0f6bcf	421	#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
8bde7f77	422
90253178	423	#endif