[J-u-boot.git] / drivers / net / designware.c

/*
 * (C) Copyright 2010
 * Vipin Kumar, ST Micoelectronics, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Designware ethernet IP driver for u-boot
 */

#include <common.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/compiler.h>
#include <linux/err.h>
#include <asm/io.h>
#include "designware.h"

#if !defined(CONFIG_PHYLIB)
# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
#endif

static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	struct eth_mac_regs *mac_p = bus->priv;
	ulong start;
	u16 miiaddr;
	int timeout = CONFIG_MDIO_TIMEOUT;

	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
		  ((reg << MIIREGSHIFT) & MII_REGMSK);

	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);

	start = get_timer(0);
	while (get_timer(start) < timeout) {
		if (!(readl(&mac_p->miiaddr) & MII_BUSY))
			return readl(&mac_p->miidata);
		udelay(10);
	};

	return -1;
}

static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val)
{
	struct eth_mac_regs *mac_p = bus->priv;
	ulong start;
	u16 miiaddr;
	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;

	writel(val, &mac_p->miidata);
	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
		  ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;

	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);

	start = get_timer(0);
	while (get_timer(start) < timeout) {
		if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
			ret = 0;
			break;
		}
		udelay(10);
	};

	return ret;
}

static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
{
	struct mii_dev *bus = mdio_alloc();

	if (!bus) {
		printf("Failed to allocate MDIO bus\n");
		return -1;
	}

	bus->read = dw_mdio_read;
	bus->write = dw_mdio_write;
	sprintf(bus->name, name);

	bus->priv = (void *)mac_regs_p;

	return mdio_register(bus);
}

static void tx_descs_init(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
	char *txbuffs = &priv->txbuffs[0];
	struct dmamacdescr *desc_p;
	u32 idx;

	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
		desc_p = &desc_table_p[idx];
		desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
		desc_p->dmamac_next = &desc_table_p[idx + 1];

#if defined(CONFIG_DW_ALTDESCRIPTOR)
		desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
				DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
				DESC_TXSTS_TXCHECKINSCTRL | \
				DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);

		desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
		desc_p->dmamac_cntl = 0;
		desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
#else
		desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
		desc_p->txrx_status = 0;
#endif
	}

	/* Correcting the last pointer of the chain */
	desc_p->dmamac_next = &desc_table_p[0];

	/* Flush all Tx buffer descriptors at once */
	flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
			   (unsigned int)priv->tx_mac_descrtable +
			   sizeof(priv->tx_mac_descrtable));

	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
	priv->tx_currdescnum = 0;
}

static void rx_descs_init(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
	char *rxbuffs = &priv->rxbuffs[0];
	struct dmamacdescr *desc_p;
	u32 idx;

	/* Before passing buffers to GMAC we need to make sure zeros
	 * written there right after "priv" structure allocation were
	 * flushed into RAM.
	 * Otherwise there's a chance to get some of them flushed in RAM when
	 * GMAC is already pushing data to RAM via DMA. This way incoming from
	 * GMAC data will be corrupted. */
	flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
			   RX_TOTAL_BUFSIZE);

	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
		desc_p = &desc_table_p[idx];
		desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
		desc_p->dmamac_next = &desc_table_p[idx + 1];

		desc_p->dmamac_cntl =
			(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
				      DESC_RXCTRL_RXCHAIN;

		desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
	}

	/* Correcting the last pointer of the chain */
	desc_p->dmamac_next = &desc_table_p[0];

	/* Flush all Rx buffer descriptors at once */
	flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
			   (unsigned int)priv->rx_mac_descrtable +
			   sizeof(priv->rx_mac_descrtable));

	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
	priv->rx_currdescnum = 0;
}

static int dw_write_hwaddr(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	u32 macid_lo, macid_hi;
	u8 *mac_id = &dev->enetaddr[0];

	macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
		   (mac_id[3] << 24);
	macid_hi = mac_id[4] + (mac_id[5] << 8);

	writel(macid_hi, &mac_p->macaddr0hi);
	writel(macid_lo, &mac_p->macaddr0lo);

	return 0;
}

static void dw_adjust_link(struct eth_mac_regs *mac_p,
			   struct phy_device *phydev)
{
	u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;

	if (!phydev->link) {
		printf("%s: No link.\n", phydev->dev->name);
		return;
	}

	if (phydev->speed != 1000)
		conf |= MII_PORTSELECT;

	if (phydev->speed == 100)
		conf |= FES_100;

	if (phydev->duplex)
		conf |= FULLDPLXMODE;

	writel(conf, &mac_p->conf);

	printf("Speed: %d, %s duplex%s\n", phydev->speed,
	       (phydev->duplex) ? "full" : "half",
	       (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}

static void dw_eth_halt(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;

	writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
	writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);

	phy_shutdown(priv->phydev);
}

static int dw_eth_init(struct eth_device *dev, bd_t *bis)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	unsigned int start;

	writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);

	start = get_timer(0);
	while (readl(&dma_p->busmode) & DMAMAC_SRST) {
		if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
			return -1;

		mdelay(100);
	};

	/* Soft reset above clears HW address registers.
	 * So we have to set it here once again */
	dw_write_hwaddr(dev);

	rx_descs_init(dev);
	tx_descs_init(dev);

	writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);

	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
	       &dma_p->opmode);

	writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);

	/* Start up the PHY */
	if (phy_startup(priv->phydev)) {
		printf("Could not initialize PHY %s\n",
		       priv->phydev->dev->name);
		return -1;
	}

	dw_adjust_link(mac_p, priv->phydev);

	if (!priv->phydev->link)
		return -1;

	writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);

	return 0;
}

static int dw_eth_send(struct eth_device *dev, void *packet, int length)
{
	struct dw_eth_dev *priv = dev->priv;
	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	u32 desc_num = priv->tx_currdescnum;
	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];

	/*
	 * Strictly we only need to invalidate the "txrx_status" field
	 * for the following check, but on some platforms we cannot
	 * invalidate only 4 bytes, so roundup to
	 * ARCH_DMA_MINALIGN. This is safe because the individual
	 * descriptors in the array are each aligned to
	 * ARCH_DMA_MINALIGN.
	 */
	invalidate_dcache_range(
		(unsigned long)desc_p,
		(unsigned long)desc_p +
		roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN));

	/* Check if the descriptor is owned by CPU */
	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
		printf("CPU not owner of tx frame\n");
		return -1;
	}

	memcpy((void *)desc_p->dmamac_addr, packet, length);

	/* Flush data to be sent */
	flush_dcache_range((unsigned long)desc_p->dmamac_addr,
			   (unsigned long)desc_p->dmamac_addr + length);

#if defined(CONFIG_DW_ALTDESCRIPTOR)
	desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
	desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
			       DESC_TXCTRL_SIZE1MASK;

	desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
	desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
	desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
			       DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
			       DESC_TXCTRL_TXFIRST;

	desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif

	/* Flush modified buffer descriptor */
	flush_dcache_range((unsigned long)desc_p,
			   (unsigned long)desc_p + sizeof(struct dmamacdescr));

	/* Test the wrap-around condition. */
	if (++desc_num >= CONFIG_TX_DESCR_NUM)
		desc_num = 0;

	priv->tx_currdescnum = desc_num;

	/* Start the transmission */
	writel(POLL_DATA, &dma_p->txpolldemand);

	return 0;
}

static int dw_eth_recv(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	u32 status, desc_num = priv->rx_currdescnum;
	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
	int length = 0;

	/* Invalidate entire buffer descriptor */
	invalidate_dcache_range((unsigned long)desc_p,
				(unsigned long)desc_p +
				sizeof(struct dmamacdescr));

	status = desc_p->txrx_status;

	/* Check  if the owner is the CPU */
	if (!(status & DESC_RXSTS_OWNBYDMA)) {

		length = (status & DESC_RXSTS_FRMLENMSK) >> \
			 DESC_RXSTS_FRMLENSHFT;

		/* Invalidate received data */
		invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
					(unsigned long)desc_p->dmamac_addr +
					roundup(length, ARCH_DMA_MINALIGN));

		NetReceive(desc_p->dmamac_addr, length);

		/*
		 * Make the current descriptor valid again and go to
		 * the next one
		 */
		desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;

		/* Flush only status field - others weren't changed */
		flush_dcache_range((unsigned long)&desc_p->txrx_status,
				   (unsigned long)&desc_p->txrx_status +
				   sizeof(desc_p->txrx_status));

		/* Test the wrap-around condition. */
		if (++desc_num >= CONFIG_RX_DESCR_NUM)
			desc_num = 0;
	}

	priv->rx_currdescnum = desc_num;

	return length;
}

static int dw_phy_init(struct eth_device *dev)
{
	struct dw_eth_dev *priv = dev->priv;
	struct phy_device *phydev;
	int mask = 0xffffffff;

#ifdef CONFIG_PHY_ADDR
	mask = 1 << CONFIG_PHY_ADDR;
#endif

	phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
	if (!phydev)
		return -1;

	phy_connect_dev(phydev, dev);

	phydev->supported &= PHY_GBIT_FEATURES;
	phydev->advertising = phydev->supported;

	priv->phydev = phydev;
	phy_config(phydev);

	return 1;
}

int designware_initialize(ulong base_addr, u32 interface)
{
	struct eth_device *dev;
	struct dw_eth_dev *priv;

	dev = (struct eth_device *) malloc(sizeof(struct eth_device));
	if (!dev)
		return -ENOMEM;

	/*
	 * Since the priv structure contains the descriptors which need a strict
	 * buswidth alignment, memalign is used to allocate memory
	 */
	priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
					      sizeof(struct dw_eth_dev));
	if (!priv) {
		free(dev);
		return -ENOMEM;
	}

	memset(dev, 0, sizeof(struct eth_device));
	memset(priv, 0, sizeof(struct dw_eth_dev));

	sprintf(dev->name, "dwmac.%lx", base_addr);
	dev->iobase = (int)base_addr;
	dev->priv = priv;

	priv->dev = dev;
	priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
	priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
			DW_DMA_BASE_OFFSET);

	dev->init = dw_eth_init;
	dev->send = dw_eth_send;
	dev->recv = dw_eth_recv;
	dev->halt = dw_eth_halt;
	dev->write_hwaddr = dw_write_hwaddr;

	eth_register(dev);

	priv->interface = interface;

	dw_mdio_init(dev->name, priv->mac_regs_p);
	priv->bus = miiphy_get_dev_by_name(dev->name);

	return dw_phy_init(dev);
}
Commit	Line	Data
5b1b1883 VK	1	/*
	2	* (C) Copyright 2010
	3	* Vipin Kumar, ST Micoelectronics, [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
5b1b1883 VK	6	*/
	7
	8	/*
	9	* Designware ethernet IP driver for u-boot
	10	*/
	11
	12	#include <common.h>
	13	#include <miiphy.h>
	14	#include <malloc.h>
ef76025a	15	#include <linux/compiler.h>
5b1b1883 VK	16	#include <linux/err.h>
	17	#include <asm/io.h>
	18	#include "designware.h"
	19
92a190aa AB	20	#if !defined(CONFIG_PHYLIB)
	21	# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
	22	#endif
	23
	24	static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
	25	{
	26	struct eth_mac_regs *mac_p = bus->priv;
	27	ulong start;
	28	u16 miiaddr;
	29	int timeout = CONFIG_MDIO_TIMEOUT;
	30
	31	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) \|
	32	((reg << MIIREGSHIFT) & MII_REGMSK);
	33
	34	writel(miiaddr \| MII_CLKRANGE_150_250M \| MII_BUSY, &mac_p->miiaddr);
	35
	36	start = get_timer(0);
	37	while (get_timer(start) < timeout) {
	38	if (!(readl(&mac_p->miiaddr) & MII_BUSY))
	39	return readl(&mac_p->miidata);
	40	udelay(10);
	41	};
	42
	43	return -1;
	44	}
	45
	46	static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
	47	u16 val)
	48	{
	49	struct eth_mac_regs *mac_p = bus->priv;
	50	ulong start;
	51	u16 miiaddr;
	52	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
	53
	54	writel(val, &mac_p->miidata);
	55	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) \|
	56	((reg << MIIREGSHIFT) & MII_REGMSK) \| MII_WRITE;
	57
	58	writel(miiaddr \| MII_CLKRANGE_150_250M \| MII_BUSY, &mac_p->miiaddr);
	59
	60	start = get_timer(0);
	61	while (get_timer(start) < timeout) {
	62	if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
	63	ret = 0;
	64	break;
	65	}
	66	udelay(10);
	67	};
	68
	69	return ret;
	70	}
	71
	72	static int dw_mdio_init(char name, struct eth_mac_regs mac_regs_p)
	73	{
	74	struct mii_dev *bus = mdio_alloc();
	75
	76	if (!bus) {
	77	printf("Failed to allocate MDIO bus\n");
	78	return -1;
	79	}
	80
	81	bus->read = dw_mdio_read;
	82	bus->write = dw_mdio_write;
	83	sprintf(bus->name, name);
84
85	bus->priv = (void *)mac_regs_p;
86
87	return mdio_register(bus);
88	}
13edd170	89
5b1b1883 VK	90	static void tx_descs_init(struct eth_device *dev)
	91	{
	92	struct dw_eth_dev *priv = dev->priv;
	93	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	94	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
	95	char *txbuffs = &priv->txbuffs[0];
	96	struct dmamacdescr *desc_p;
	97	u32 idx;
	98
	99	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
	100	desc_p = &desc_table_p[idx];
	101	desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
	102	desc_p->dmamac_next = &desc_table_p[idx + 1];
	103
	104	#if defined(CONFIG_DW_ALTDESCRIPTOR)
	105	desc_p->txrx_status &= ~(DESC_TXSTS_TXINT \| DESC_TXSTS_TXLAST \|
	106	DESC_TXSTS_TXFIRST \| DESC_TXSTS_TXCRCDIS \| \
	107	DESC_TXSTS_TXCHECKINSCTRL \| \
	108	DESC_TXSTS_TXRINGEND \| DESC_TXSTS_TXPADDIS);
	109
	110	desc_p->txrx_status \|= DESC_TXSTS_TXCHAIN;
	111	desc_p->dmamac_cntl = 0;
	112	desc_p->txrx_status &= ~(DESC_TXSTS_MSK \| DESC_TXSTS_OWNBYDMA);
	113	#else
	114	desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
	115	desc_p->txrx_status = 0;
	116	#endif
	117	}
	118
	119	/* Correcting the last pointer of the chain */
	120	desc_p->dmamac_next = &desc_table_p[0];
	121
50b0df81 AB	122	/* Flush all Tx buffer descriptors at once */
	123	flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
	124	(unsigned int)priv->tx_mac_descrtable +
	125	sizeof(priv->tx_mac_descrtable));
	126
5b1b1883	127	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
74cb708d	128	priv->tx_currdescnum = 0;
5b1b1883 VK	129	}
	130
	131	static void rx_descs_init(struct eth_device *dev)
	132	{
	133	struct dw_eth_dev *priv = dev->priv;
	134	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	135	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
	136	char *rxbuffs = &priv->rxbuffs[0];
	137	struct dmamacdescr *desc_p;
	138	u32 idx;
	139
50b0df81 AB	140	/* Before passing buffers to GMAC we need to make sure zeros
	141	* written there right after "priv" structure allocation were
	142	* flushed into RAM.
	143	* Otherwise there's a chance to get some of them flushed in RAM when
	144	* GMAC is already pushing data to RAM via DMA. This way incoming from
	145	* GMAC data will be corrupted. */
	146	flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
	147	RX_TOTAL_BUFSIZE);
	148
5b1b1883 VK	149	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
	150	desc_p = &desc_table_p[idx];
	151	desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
	152	desc_p->dmamac_next = &desc_table_p[idx + 1];
	153
	154	desc_p->dmamac_cntl =
	155	(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) \| \
	156	DESC_RXCTRL_RXCHAIN;
	157
	158	desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
	159	}
	160
	161	/* Correcting the last pointer of the chain */
	162	desc_p->dmamac_next = &desc_table_p[0];
	163
50b0df81 AB	164	/* Flush all Rx buffer descriptors at once */
	165	flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
	166	(unsigned int)priv->rx_mac_descrtable +
	167	sizeof(priv->rx_mac_descrtable));
	168
5b1b1883	169	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
74cb708d	170	priv->rx_currdescnum = 0;
5b1b1883 VK	171	}
5b1b1883 VK	172
92a190aa	173	static int dw_write_hwaddr(struct eth_device *dev)
5b1b1883	174	{
92a190aa AB	175	struct dw_eth_dev *priv = dev->priv;
	176	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	177	u32 macid_lo, macid_hi;
	178	u8 *mac_id = &dev->enetaddr[0];
	179
	180	macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
	181	(mac_id[3] << 24);
	182	macid_hi = mac_id[4] + (mac_id[5] << 8);
	183
	184	writel(macid_hi, &mac_p->macaddr0hi);
	185	writel(macid_lo, &mac_p->macaddr0lo);
	186
	187	return 0;
5b1b1883 VK	188	}
5b1b1883 VK	189
92a190aa AB	190	static void dw_adjust_link(struct eth_mac_regs *mac_p,
92a190aa AB	191	struct phy_device *phydev)
5b1b1883	192	{
92a190aa	193	u32 conf = readl(&mac_p->conf) \| FRAMEBURSTENABLE \| DISABLERXOWN;
5b1b1883	194
92a190aa AB	195	if (!phydev->link) {
	196	printf("%s: No link.\n", phydev->dev->name);
	197	return;
	198	}
5b1b1883	199
92a190aa AB	200	if (phydev->speed != 1000)
92a190aa AB	201	conf \|= MII_PORTSELECT;
7091915a	202
92a190aa AB	203	if (phydev->speed == 100)
92a190aa AB	204	conf \|= FES_100;
5b1b1883	205
92a190aa AB	206	if (phydev->duplex)
92a190aa AB	207	conf \|= FULLDPLXMODE;
cafabe19	208
92a190aa	209	writel(conf, &mac_p->conf);
5b1b1883	210
92a190aa AB	211	printf("Speed: %d, %s duplex%s\n", phydev->speed,
	212	(phydev->duplex) ? "full" : "half",
	213	(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
5b1b1883 VK	214	}
5b1b1883 VK	215
92a190aa	216	static void dw_eth_halt(struct eth_device *dev)
5b1b1883 VK	217	{
	218	struct dw_eth_dev *priv = dev->priv;
	219	struct eth_mac_regs *mac_p = priv->mac_regs_p;
92a190aa	220	struct eth_dma_regs *dma_p = priv->dma_regs_p;
5b1b1883	221
92a190aa AB	222	writel(readl(&mac_p->conf) & ~(RXENABLE \| TXENABLE), &mac_p->conf);
92a190aa AB	223	writel(readl(&dma_p->opmode) & ~(RXSTART \| TXSTART), &dma_p->opmode);
5b1b1883	224
92a190aa	225	phy_shutdown(priv->phydev);
5b1b1883 VK	226	}
	227
	228	static int dw_eth_init(struct eth_device dev, bd_t bis)
	229	{
	230	struct dw_eth_dev *priv = dev->priv;
	231	struct eth_mac_regs *mac_p = priv->mac_regs_p;
	232	struct eth_dma_regs *dma_p = priv->dma_regs_p;
92a190aa	233	unsigned int start;
5b1b1883	234
92a190aa	235	writel(readl(&dma_p->busmode) \| DMAMAC_SRST, &dma_p->busmode);
13edd170	236
92a190aa AB	237	start = get_timer(0);
	238	while (readl(&dma_p->busmode) & DMAMAC_SRST) {
	239	if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
	240	return -1;
ef76025a	241
92a190aa AB	242	mdelay(100);
92a190aa AB	243	};
5b1b1883	244
92a190aa AB	245	/* Soft reset above clears HW address registers.
92a190aa AB	246	* So we have to set it here once again */
c7f6dbe7 VK	247	dw_write_hwaddr(dev);
c7f6dbe7 VK	248
92a190aa AB	249	rx_descs_init(dev);
92a190aa AB	250	tx_descs_init(dev);
5b1b1883	251
92a190aa	252	writel(FIXEDBURST \| PRIORXTX_41 \| BURST_16, &dma_p->busmode);
5b1b1883	253
92a190aa AB	254	writel(readl(&dma_p->opmode) \| FLUSHTXFIFO \| STOREFORWARD,
92a190aa AB	255	&dma_p->opmode);
5b1b1883	256
92a190aa	257	writel(readl(&dma_p->opmode) \| RXSTART \| TXSTART, &dma_p->opmode);
9afc1af0	258
92a190aa AB	259	/* Start up the PHY */
	260	if (phy_startup(priv->phydev)) {
	261	printf("Could not initialize PHY %s\n",
	262	priv->phydev->dev->name);
	263	return -1;
9afc1af0 VK	264	}
9afc1af0 VK	265
92a190aa	266	dw_adjust_link(mac_p, priv->phydev);
5b1b1883	267
92a190aa AB	268	if (!priv->phydev->link)
92a190aa AB	269	return -1;
5b1b1883	270
aa51005c	271	writel(readl(&mac_p->conf) \| RXENABLE \| TXENABLE, &mac_p->conf);
5b1b1883 VK	272
	273	return 0;
	274	}
	275
10cbe3b6	276	static int dw_eth_send(struct eth_device dev, void packet, int length)
5b1b1883 VK	277	{
	278	struct dw_eth_dev *priv = dev->priv;
	279	struct eth_dma_regs *dma_p = priv->dma_regs_p;
	280	u32 desc_num = priv->tx_currdescnum;
	281	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
	282
964ea7c1 IC	283	/*
	284	* Strictly we only need to invalidate the "txrx_status" field
	285	* for the following check, but on some platforms we cannot
	286	* invalidate only 4 bytes, so roundup to
	287	* ARCH_DMA_MINALIGN. This is safe because the individual
	288	* descriptors in the array are each aligned to
	289	* ARCH_DMA_MINALIGN.
	290	*/
	291	invalidate_dcache_range(
	292	(unsigned long)desc_p,
	293	(unsigned long)desc_p +
	294	roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN));
50b0df81	295
5b1b1883 VK	296	/* Check if the descriptor is owned by CPU */
	297	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
	298	printf("CPU not owner of tx frame\n");
	299	return -1;
	300	}
	301
10cbe3b6	302	memcpy((void *)desc_p->dmamac_addr, packet, length);
5b1b1883	303
50b0df81 AB	304	/* Flush data to be sent */
	305	flush_dcache_range((unsigned long)desc_p->dmamac_addr,
	306	(unsigned long)desc_p->dmamac_addr + length);
	307
5b1b1883 VK	308	#if defined(CONFIG_DW_ALTDESCRIPTOR)
	309	desc_p->txrx_status \|= DESC_TXSTS_TXFIRST \| DESC_TXSTS_TXLAST;
	310	desc_p->dmamac_cntl \|= (length << DESC_TXCTRL_SIZE1SHFT) & \
	311	DESC_TXCTRL_SIZE1MASK;
	312
	313	desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
	314	desc_p->txrx_status \|= DESC_TXSTS_OWNBYDMA;
	315	#else
	316	desc_p->dmamac_cntl \|= ((length << DESC_TXCTRL_SIZE1SHFT) & \
	317	DESC_TXCTRL_SIZE1MASK) \| DESC_TXCTRL_TXLAST \| \
	318	DESC_TXCTRL_TXFIRST;
	319
	320	desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
	321	#endif
	322
50b0df81 AB	323	/* Flush modified buffer descriptor */
	324	flush_dcache_range((unsigned long)desc_p,
	325	(unsigned long)desc_p + sizeof(struct dmamacdescr));
	326
5b1b1883 VK	327	/* Test the wrap-around condition. */
	328	if (++desc_num >= CONFIG_TX_DESCR_NUM)
	329	desc_num = 0;
	330
	331	priv->tx_currdescnum = desc_num;
	332
	333	/* Start the transmission */
	334	writel(POLL_DATA, &dma_p->txpolldemand);
	335
	336	return 0;
	337	}
	338
	339	static int dw_eth_recv(struct eth_device *dev)
	340	{
	341	struct dw_eth_dev *priv = dev->priv;
50b0df81	342	u32 status, desc_num = priv->rx_currdescnum;
5b1b1883	343	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
5b1b1883 VK	344	int length = 0;
5b1b1883 VK	345
50b0df81 AB	346	/* Invalidate entire buffer descriptor */
	347	invalidate_dcache_range((unsigned long)desc_p,
	348	(unsigned long)desc_p +
	349	sizeof(struct dmamacdescr));
	350
	351	status = desc_p->txrx_status;
	352
5b1b1883 VK	353	/* Check if the owner is the CPU */
	354	if (!(status & DESC_RXSTS_OWNBYDMA)) {
	355
	356	length = (status & DESC_RXSTS_FRMLENMSK) >> \
	357	DESC_RXSTS_FRMLENSHFT;
	358
50b0df81 AB	359	/* Invalidate received data */
	360	invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
	361	(unsigned long)desc_p->dmamac_addr +
964ea7c1	362	roundup(length, ARCH_DMA_MINALIGN));
50b0df81	363
5b1b1883 VK	364	NetReceive(desc_p->dmamac_addr, length);
	365
	366	/*
	367	* Make the current descriptor valid again and go to
	368	* the next one
	369	*/
	370	desc_p->txrx_status \|= DESC_RXSTS_OWNBYDMA;
	371
50b0df81 AB	372	/* Flush only status field - others weren't changed */
	373	flush_dcache_range((unsigned long)&desc_p->txrx_status,
	374	(unsigned long)&desc_p->txrx_status +
	375	sizeof(desc_p->txrx_status));
	376
5b1b1883 VK	377	/* Test the wrap-around condition. */
	378	if (++desc_num >= CONFIG_RX_DESCR_NUM)
	379	desc_num = 0;
	380	}
	381
	382	priv->rx_currdescnum = desc_num;
	383
	384	return length;
	385	}
	386
92a190aa	387	static int dw_phy_init(struct eth_device *dev)
5b1b1883 VK	388	{
5b1b1883 VK	389	struct dw_eth_dev *priv = dev->priv;
92a190aa AB	390	struct phy_device *phydev;
92a190aa AB	391	int mask = 0xffffffff;
cafabe19	392
92a190aa AB	393	#ifdef CONFIG_PHY_ADDR
92a190aa AB	394	mask = 1 << CONFIG_PHY_ADDR;
5b1b1883 VK	395	#endif
5b1b1883 VK	396
92a190aa AB	397	phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
92a190aa AB	398	if (!phydev)
5b1b1883 VK	399	return -1;
5b1b1883 VK	400
15e82e53 IC	401	phy_connect_dev(phydev, dev);
15e82e53 IC	402
92a190aa AB	403	phydev->supported &= PHY_GBIT_FEATURES;
92a190aa AB	404	phydev->advertising = phydev->supported;
5b1b1883	405
92a190aa AB	406	priv->phydev = phydev;
92a190aa AB	407	phy_config(phydev);
ef76025a	408
92a190aa	409	return 1;
5b1b1883	410	}
5b1b1883	411
92a190aa	412	int designware_initialize(ulong base_addr, u32 interface)
5b1b1883 VK	413	{
	414	struct eth_device *dev;
	415	struct dw_eth_dev *priv;
	416
	417	dev = (struct eth_device *) malloc(sizeof(struct eth_device));
	418	if (!dev)
	419	return -ENOMEM;
	420
	421	/*
	422	* Since the priv structure contains the descriptors which need a strict
	423	* buswidth alignment, memalign is used to allocate memory
	424	*/
1c848a25 IC	425	priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
1c848a25 IC	426	sizeof(struct dw_eth_dev));
5b1b1883 VK	427	if (!priv) {
	428	free(dev);
	429	return -ENOMEM;
	430	}
	431
	432	memset(dev, 0, sizeof(struct eth_device));
	433	memset(priv, 0, sizeof(struct dw_eth_dev));
	434
92a190aa	435	sprintf(dev->name, "dwmac.%lx", base_addr);
5b1b1883 VK	436	dev->iobase = (int)base_addr;
	437	dev->priv = priv;
	438
5b1b1883 VK	439	priv->dev = dev;
	440	priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
	441	priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
	442	DW_DMA_BASE_OFFSET);
5b1b1883	443
5b1b1883 VK	444	dev->init = dw_eth_init;
	445	dev->send = dw_eth_send;
	446	dev->recv = dw_eth_recv;
	447	dev->halt = dw_eth_halt;
	448	dev->write_hwaddr = dw_write_hwaddr;
	449
	450	eth_register(dev);
	451
92a190aa AB	452	priv->interface = interface;
	453
	454	dw_mdio_init(dev->name, priv->mac_regs_p);
	455	priv->bus = miiphy_get_dev_by_name(dev->name);
	456
	457	return dw_phy_init(dev);
5b1b1883	458	}