projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8ed96046 WD |
1 | /* |
| 2 | ||
| 3 | Ported to U-Boot by Christian Pellegrin <[email protected]> | |
| 4 | ||
| 5 | Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and | |
| 6 | eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world | |
| 7 | are GPL, so this is, of course, GPL. | |
| 8 | ||
| 9 | */ | |
| 10 | ||
| 11 | /* Generic NS8390 register definitions. */ | |
| 12 | /* This file is part of Donald Becker's 8390 drivers, and is distributed | |
| 13 | under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. | |
| 14 | Some of these names and comments originated from the Crynwr | |
| 15 | packet drivers, which are distributed under the GPL. */ | |
| 16 | ||
| 17 | #ifndef _8390_h | |
| 18 | #define _8390_h | |
| 19 | ||
| 20 | /* Some generic ethernet register configurations. */ | |
| 21 | #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ | |
| 22 | #define E8390_RX_IRQ_MASK 0x5 | |
| 23 | #define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */ | |
| 24 | #define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */ | |
| 25 | #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */ | |
| 26 | #define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */ | |
| 27 | ||
| 28 | /* Register accessed at EN_CMD, the 8390 base addr. */ | |
| 29 | #define E8390_STOP 0x01 /* Stop and reset the chip */ | |
| 30 | #define E8390_START 0x02 /* Start the chip, clear reset */ | |
| 31 | #define E8390_TRANS 0x04 /* Transmit a frame */ | |
| 32 | #define E8390_RREAD 0x08 /* Remote read */ | |
| 33 | #define E8390_RWRITE 0x10 /* Remote write */ | |
| 34 | #define E8390_NODMA 0x20 /* Remote DMA */ | |
| 35 | #define E8390_PAGE0 0x00 /* Select page chip registers */ | |
| 36 | #define E8390_PAGE1 0x40 /* using the two high-order bits */ | |
| 37 | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ | |
| 38 | ||
| 39 | /* | |
| 40 | * Only generate indirect loads given a machine that needs them. | |
| 41 | * - removed AMIGA_PCMCIA from this list, handled as ISA io now | |
| 42 | */ | |
| 43 | ||
| 44 | #define n2k_inb(port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE))) | |
| 45 | #define n2k_outb(val,port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)) = val) | |
| 46 | ||
| 47 | #define EI_SHIFT(x) (x) | |
| 48 | ||
| 49 | #define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */ | |
| 50 | /* Page 0 register offsets. */ | |
| 51 | #define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */ | |
| 52 | #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */ | |
| 53 | #define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */ | |
| 54 | #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */ | |
| 55 | #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */ | |
| 56 | #define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */ | |
| 57 | #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */ | |
| 58 | #define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */ | |
| 59 | #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */ | |
| 60 | #define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */ | |
| 61 | #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */ | |
| 62 | #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ | |
| 63 | #define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */ | |
| 64 | #define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */ | |
| 65 | #define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */ | |
| 66 | #define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */ | |
| 67 | #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */ | |
| 68 | #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */ | |
| 69 | #define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */ | |
| 70 | #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */ | |
| 71 | #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */ | |
| 72 | #define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */ | |
| 73 | #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */ | |
| 74 | #define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */ | |
| 75 | #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */ | |
| 76 | #define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */ | |
| 77 | ||
| 78 | /* Bits in EN0_ISR - Interrupt status register */ | |
| 79 | #define ENISR_RX 0x01 /* Receiver, no error */ | |
| 80 | #define ENISR_TX 0x02 /* Transmitter, no error */ | |
| 81 | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ | |
| 82 | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ | |
| 83 | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ | |
| 84 | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ | |
| 85 | #define ENISR_RDC 0x40 /* remote dma complete */ | |
| 86 | #define ENISR_RESET 0x80 /* Reset completed */ | |
| 87 | #define ENISR_ALL 0x3f /* Interrupts we will enable */ | |
| 88 | ||
| 89 | /* Bits in EN0_DCFG - Data config register */ | |
| 90 | #define ENDCFG_WTS 0x01 /* word transfer mode selection */ | |
| 91 | #define ENDCFG_BOS 0x02 /* byte order selection */ | |
| 92 | #define ENDCFG_AUTO_INIT 0x10 /* Auto-init to remove packets from ring */ | |
| 93 | #define ENDCFG_FIFO 0x40 /* 8 bytes */ | |
| 94 | ||
| 8ed96046 WD |
95 | /* Page 1 register offsets. */ |
| 96 | #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */ | |
| 97 | #define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */ | |
| 98 | #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */ | |
| 99 | #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */ | |
| 100 | #define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */ | |
| 101 | ||
| 102 | /* Bits in received packet status byte and EN0_RSR*/ | |
| 103 | #define ENRSR_RXOK 0x01 /* Received a good packet */ | |
| 104 | #define ENRSR_CRC 0x02 /* CRC error */ | |
| 105 | #define ENRSR_FAE 0x04 /* frame alignment error */ | |
| 106 | #define ENRSR_FO 0x08 /* FIFO overrun */ | |
| 107 | #define ENRSR_MPA 0x10 /* missed pkt */ | |
| 108 | #define ENRSR_PHY 0x20 /* physical/multicast address */ | |
| 109 | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ | |
| 110 | #define ENRSR_DEF 0x80 /* deferring */ | |
| 111 | ||
| 112 | /* Transmitted packet status, EN0_TSR. */ | |
| 113 | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ | |
| 114 | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ | |
| 115 | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ | |
| 116 | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ | |
| 117 | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ | |
| 118 | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ | |
| 119 | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ | |
| 120 | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ | |
| 121 | ||
| 122 | #define NIC_RECEIVE_MONITOR_MODE 0x20 | |
| 123 | ||
| 124 | #endif /* _8390_h */ |