[J-u-boot.git] / arch / Kconfig.nxp

config NXP_ESBC
	bool "NXP ESBC (secure boot) functionality"
	help
	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
	  If unsure, do not change.

menu "Chain of trust / secure boot options"
	depends on !FIT_SIGNATURE && NXP_ESBC

config CHAIN_OF_TRUST
	select FSL_CAAM
	select ARCH_MISC_INIT
	select FSL_SEC_MON
	select SPL_BOARD_INIT if (ARM && SPL)
	select SPL_HASH if (ARM && SPL)
	select SHA_HW_ACCEL
	select SHA_PROG_HW_ACCEL
	select ENV_IS_NOWHERE
	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
	select CMD_EXT4 if ARM
	select CMD_EXT4_WRITE if ARM
	imply CMD_BLOB
	imply CMD_HASH if ARM
	def_bool y

config CMD_ESBC_VALIDATE
	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
	default y
	help
	  This option enables two commands used for secure booting:

	    esbc_validate - validate signature using RSA verification
	    esbc_halt - put the core in spin loop (Secure Boot Only)

config ESBC_HDR_LS
	bool

config ESBC_ADDR_64BIT
	def_bool y
	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
	help
	  For Layerscape based platforms, ESBC image Address in Header is 64bit.

config SYS_FSL_SFP_BE
	def_bool y
	depends on PPC || FSL_LSCH2 || ARCH_LS1021A

config SYS_FSL_SFP_LE
	def_bool y
	depends on !SYS_FSL_SFP_BE

choice
	prompt "SFP IP revision"
	default SYS_FSL_SFP_VER_3_0 if PPC
	default SYS_FSL_SFP_VER_3_4

config SYS_FSL_SFP_VER_3_0
	bool "SFP version 3.0"

config SYS_FSL_SFP_VER_3_2
	bool "SFP version 3.2"

config SYS_FSL_SFP_VER_3_4
	bool "SFP version 3.4"

endchoice

config SPL_UBOOT_KEY_HASH
	string "Non-SRK key hash for U-Boot public/private key pair"
	depends on SPL
	default ""
	help
	  Set the key hash for U-Boot here if public/private key pair used to
	  sign U-boot are different from the SRK hash put in the fuse.  Example
	  of a key hash is
	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
	  Otherwise leave this empty.

if PPC

config BOOTSCRIPT_COPY_RAM
	bool "Secure boot copies boot script to RAM"
	help
	  On systems that support chain of trust booting, a number of addresses
	  are required to set variables that are used in the copying and then
	  verification of different parts of the system.  If enabled, the subsequent
	  options are for what location to use in each step.

config BS_ADDR_DEVICE
	hex "Address in RAM for bs_device"
	depends on BOOTSCRIPT_COPY_RAM

config BS_SIZE
	hex "The size of bs_size which is the amount read from bs_device"
	depends on BOOTSCRIPT_COPY_RAM

config BS_ADDR_RAM
	hex "Address in RAM for bs_ram"
	depends on BOOTSCRIPT_COPY_RAM

config BS_HDR_ADDR_DEVICE
	hex "Address in RAM for bs_hdr_device"
	depends on BOOTSCRIPT_COPY_RAM

config BS_HDR_SIZE
	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
	depends on BOOTSCRIPT_COPY_RAM

config BS_HDR_ADDR_RAM
	hex "Address in RAM for bs_hdr_ram"
	depends on BOOTSCRIPT_COPY_RAM

config BOOTSCRIPT_HDR_ADDR
	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM

endif

config SYS_FSL_SRK_LE
	def_bool y
	depends on ARM

config KEY_REVOCATION
	def_bool y

endmenu

comment "Other functionality shared between NXP SoCs"

config DEEP_SLEEP
	bool "Enable SoC deep sleep feature"
	depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
	default y
	help
	  Indicates this SoC supports deep sleep feature. If deep sleep is
	  supported, core will start to execute uboot when wakes up.

config LAYERSCAPE_NS_ACCESS
	bool "Layerscape non-secure access support"
	depends on ARCH_LS1021A || FSL_LSCH2

config PCIE1
	bool "PCIe controller #1"
	depends on LAYERSCAPE_NS_ACCESS || PPC

config PCIE2
	bool "PCIe controller #2"
	depends on LAYERSCAPE_NS_ACCESS || PPC

config PCIE3
	bool "PCIe controller #3"
	depends on LAYERSCAPE_NS_ACCESS || PPC

config PCIE4
	bool "PCIe controller #4"
	depends on LAYERSCAPE_NS_ACCESS || PPC

config FSL_USE_PCA9547_MUX
	bool "Enable PCA9547 I2C Mux on Freescale boards"
	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
	help
	 This option enables the PCA9547 I2C mux on Freescale boards.

config VID
	bool "Enable Freescale VID"
	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
	help
	 This option enables setting core voltage based on individual
	 values saved in SoC fuses.

config SPL_VID
	bool "Enable Freescale VID in SPL"
	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
	help
	 This option enables setting core voltage based on individual
	 values saved in SoC fuses, in SPL.

if VID || SPL_VID

config VID_FLS_ENV
	string "Environment variable for overriding VDD"
	help
	  This option allows for specifying the environment variable
	  to check to override VDD information.

config VOL_MONITOR_INA220
	bool "Enable the INA220 voltage monitor read"
	help
	  This option enables INA220 voltage monitor read
	  functionality. It is used by the common VID driver.

config VOL_MONITOR_IR36021_READ
	bool "Enable the IR36021 voltage monitor read"
	help
	 This option enables IR36021 voltage monitor read
	 functionality. It is used by the common VID driver.

config VOL_MONITOR_IR36021_SET
	bool "Enable the IR36021 voltage monitor set"
	help
	 This option enables IR36021 voltage monitor set
	 functionality. It is used by the common VID driver.

config VOL_MONITOR_LTC3882_READ
	bool "Enable the LTC3882 voltage monitor read"
	help
	 This option enables LTC3882 voltage monitor read
	 functionality. It is used by the common VID driver.

config VOL_MONITOR_LTC3882_SET
	bool "Enable the LTC3882 voltage monitor set"
	help
	 This option enables LTC3882 voltage monitor set
	 functionality. It is used by the common VID driver.

config VOL_MONITOR_ISL68233_READ
	bool "Enable the ISL68233 voltage monitor read"
	help
	 This option enables ISL68233 voltage monitor read
	 functionality. It is used by the common VID driver.

config VOL_MONITOR_ISL68233_SET
	bool "Enable the ISL68233 voltage monitor set"
	help
	 This option enables ISL68233 voltage monitor set
	 functionality. It is used by the common VID driver.

endif

config SYS_FSL_NUM_CC_PLLS
	int "Number of clock control PLLs"
	depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
	default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
	default 6 if FSL_LSCH3 || MPC85xx

config SYS_FSL_ESDHC_BE
	bool

config SYS_FSL_IFC_BE
	bool

config FSL_QIXIS
	bool "Enable QIXIS support"
	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3

config QIXIS_I2C_ACCESS
	bool "Access to QIXIS is over i2c"
	depends on FSL_QIXIS
	default y

config HAS_FSL_DR_USB
	def_bool y
	depends on USB_EHCI_HCD && PPC
Commit	Line	Data
540b73a7 TR	1	config NXP_ESBC
	2	bool "NXP ESBC (secure boot) functionality"
	3	help
	4	Enable Freescale Secure Boot feature. Normally selected by defconfig.
	5	If unsure, do not change.
	6
	7	menu "Chain of trust / secure boot options"
5536c3c9	8	depends on !FIT_SIGNATURE && NXP_ESBC
540b73a7 TR	9
540b73a7 TR	10	config CHAIN_OF_TRUST
28522678	11	select FSL_CAAM
66e54716	12	select ARCH_MISC_INIT
c9f85187	13	select FSL_SEC_MON
0680f1b1	14	select SPL_BOARD_INIT if (ARM && SPL)
07212096	15	select SPL_HASH if (ARM && SPL)
089df18b TR	16	select SHA_HW_ACCEL
089df18b TR	17	select SHA_PROG_HW_ACCEL
2be29653	18	select ENV_IS_NOWHERE
f6c1f917	19	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
86c773fe SG	20	select CMD_EXT4 if ARM
86c773fe SG	21	select CMD_EXT4_WRITE if ARM
540b73a7 TR	22	imply CMD_BLOB
	23	imply CMD_HASH if ARM
	24	def_bool y
ea7971f7 SG	25
	26	config CMD_ESBC_VALIDATE
	27	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
93145335	28	default y
ea7971f7 SG	29	help
	30	This option enables two commands used for secure booting:
	31
	32	esbc_validate - validate signature using RSA verification
	33	esbc_halt - put the core in spin loop (Secure Boot Only)
6f2d0a50	34
2b2817b5 TR	35	config ESBC_HDR_LS
	36	bool
	37
	38	config ESBC_ADDR_64BIT
	39	def_bool y
	40	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
	41	help
	42	For Layerscape based platforms, ESBC image Address in Header is 64bit.
	43
601483ff TR	44	config SYS_FSL_SFP_BE
601483ff TR	45	def_bool y
540b73a7	46	depends on PPC \|\| FSL_LSCH2 \|\| ARCH_LS1021A
601483ff TR	47
	48	config SYS_FSL_SFP_LE
	49	def_bool y
540b73a7	50	depends on !SYS_FSL_SFP_BE
601483ff TR	51
	52	choice
	53	prompt "SFP IP revision"
601483ff TR	54	default SYS_FSL_SFP_VER_3_0 if PPC
	55	default SYS_FSL_SFP_VER_3_4
	56
	57	config SYS_FSL_SFP_VER_3_0
	58	bool "SFP version 3.0"
	59
	60	config SYS_FSL_SFP_VER_3_2
	61	bool "SFP version 3.2"
	62
	63	config SYS_FSL_SFP_VER_3_4
	64	bool "SFP version 3.4"
	65
	66	endchoice
	67
5aad0a14 TR	68	config SPL_UBOOT_KEY_HASH
	69	string "Non-SRK key hash for U-Boot public/private key pair"
	70	depends on SPL
	71	default ""
	72	help
	73	Set the key hash for U-Boot here if public/private key pair used to
	74	sign U-boot are different from the SRK hash put in the fuse. Example
	75	of a key hash is
	76	41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
	77	Otherwise leave this empty.
	78
f4cd75e9 TR	79	if PPC
	80
	81	config BOOTSCRIPT_COPY_RAM
	82	bool "Secure boot copies boot script to RAM"
	83	help
	84	On systems that support chain of trust booting, a number of addresses
	85	are required to set variables that are used in the copying and then
	86	verification of different parts of the system. If enabled, the subsequent
	87	options are for what location to use in each step.
	88
	89	config BS_ADDR_DEVICE
	90	hex "Address in RAM for bs_device"
	91	depends on BOOTSCRIPT_COPY_RAM
	92
	93	config BS_SIZE
	94	hex "The size of bs_size which is the amount read from bs_device"
	95	depends on BOOTSCRIPT_COPY_RAM
	96
	97	config BS_ADDR_RAM
	98	hex "Address in RAM for bs_ram"
	99	depends on BOOTSCRIPT_COPY_RAM
	100
	101	config BS_HDR_ADDR_DEVICE
	102	hex "Address in RAM for bs_hdr_device"
	103	depends on BOOTSCRIPT_COPY_RAM
	104
	105	config BS_HDR_SIZE
	106	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
	107	depends on BOOTSCRIPT_COPY_RAM
	108
	109	config BS_HDR_ADDR_RAM
	110	hex "Address in RAM for bs_hdr_ram"
	111	depends on BOOTSCRIPT_COPY_RAM
	112
	113	config BOOTSCRIPT_HDR_ADDR
	114	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
	115	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
	116
	117	endif
	118
601483ff TR	119	config SYS_FSL_SRK_LE
601483ff TR	120	def_bool y
540b73a7	121	depends on ARM
601483ff TR	122
	123	config KEY_REVOCATION
	124	def_bool y
540b73a7 TR	125
	126	endmenu
	127
	128	comment "Other functionality shared between NXP SoCs"
601483ff	129
28f9c312 TR	130	config DEEP_SLEEP
28f9c312 TR	131	bool "Enable SoC deep sleep feature"
93145335 TR	132	depends on ARCH_T1024 \|\| ARCH_T1040 \|\| ARCH_T1042 \|\| ARCH_LS1021A
93145335 TR	133	default y
28f9c312 TR	134	help
	135	Indicates this SoC supports deep sleep feature. If deep sleep is
	136	supported, core will start to execute uboot when wakes up.
	137
a552ffc9 TR	138	config LAYERSCAPE_NS_ACCESS
	139	bool "Layerscape non-secure access support"
	140	depends on ARCH_LS1021A \|\| FSL_LSCH2
	141
3dc2987f TR	142	config PCIE1
	143	bool "PCIe controller #1"
	144	depends on LAYERSCAPE_NS_ACCESS \|\| PPC
	145
	146	config PCIE2
	147	bool "PCIe controller #2"
	148	depends on LAYERSCAPE_NS_ACCESS \|\| PPC
	149
	150	config PCIE3
	151	bool "PCIe controller #3"
	152	depends on LAYERSCAPE_NS_ACCESS \|\| PPC
	153
	154	config PCIE4
	155	bool "PCIe controller #4"
	156	depends on LAYERSCAPE_NS_ACCESS \|\| PPC
	157
15347d2d SC	158	config FSL_USE_PCA9547_MUX
15347d2d SC	159	bool "Enable PCA9547 I2C Mux on Freescale boards"
93145335	160	depends on PPC \|\| ARCH_LS1021A \|\| FSL_LSCH2 \|\| FSL_LSCH3
15347d2d SC	161	help
	162	This option enables the PCA9547 I2C mux on Freescale boards.
	163
b5ee48c0	164	config VID
b5ee48c0	165	bool "Enable Freescale VID"
93145335	166	depends on (PPC \|\| ARCH_LS1021A \|\| FSL_LSCH2 \|\| FSL_LSCH3) && (I2C \|\| DM_I2C)
b5ee48c0 SC	167	help
	168	This option enables setting core voltage based on individual
	169	values saved in SoC fuses.
	170
d06e4b7e TR	171	config SPL_VID
d06e4b7e TR	172	bool "Enable Freescale VID in SPL"
93145335	173	depends on (PPC \|\| ARCH_LS1021A \|\| FSL_LSCH2 \|\| FSL_LSCH3) && (SPL_I2C \|\| DM_SPL_I2C)
d06e4b7e TR	174	help
	175	This option enables setting core voltage based on individual
	176	values saved in SoC fuses, in SPL.
	177
	178	if VID \|\| SPL_VID
	179
	180	config VID_FLS_ENV
	181	string "Environment variable for overriding VDD"
	182	help
	183	This option allows for specifying the environment variable
	184	to check to override VDD information.
	185
	186	config VOL_MONITOR_INA220
	187	bool "Enable the INA220 voltage monitor read"
	188	help
	189	This option enables INA220 voltage monitor read
	190	functionality. It is used by the common VID driver.
	191
	192	config VOL_MONITOR_IR36021_READ
	193	bool "Enable the IR36021 voltage monitor read"
	194	help
	195	This option enables IR36021 voltage monitor read
	196	functionality. It is used by the common VID driver.
	197
	198	config VOL_MONITOR_IR36021_SET
	199	bool "Enable the IR36021 voltage monitor set"
	200	help
	201	This option enables IR36021 voltage monitor set
	202	functionality. It is used by the common VID driver.
	203
6f2d0a50	204	config VOL_MONITOR_LTC3882_READ
6f2d0a50	205	bool "Enable the LTC3882 voltage monitor read"
6f2d0a50 RB	206	help
6f2d0a50 RB	207	This option enables LTC3882 voltage monitor read
b5ee48c0	208	functionality. It is used by the common VID driver.
6f2d0a50 RB	209
6f2d0a50 RB	210	config VOL_MONITOR_LTC3882_SET
6f2d0a50	211	bool "Enable the LTC3882 voltage monitor set"
6f2d0a50 RB	212	help
6f2d0a50 RB	213	This option enables LTC3882 voltage monitor set
b5ee48c0 SC	214	functionality. It is used by the common VID driver.
	215
	216	config VOL_MONITOR_ISL68233_READ
b5ee48c0 SC	217	bool "Enable the ISL68233 voltage monitor read"
	218	help
	219	This option enables ISL68233 voltage monitor read
	220	functionality. It is used by the common VID driver.
	221
	222	config VOL_MONITOR_ISL68233_SET
b5ee48c0 SC	223	bool "Enable the ISL68233 voltage monitor set"
	224	help
	225	This option enables ISL68233 voltage monitor set
	226	functionality. It is used by the common VID driver.
d06e4b7e TR	227
d06e4b7e TR	228	endif
d43cd486	229
1de46d91 TR	230	config SYS_FSL_NUM_CC_PLLS
	231	int "Number of clock control PLLs"
	232	depends on MPC85xx \|\| FSL_LSCH2 \|\| FSL_LSCH3 \|\| ARCH_LS1021A \|\| ARCH_LS1028A
	233	default 2 if ARCH_LS1021A \|\| ARCH_LS1028A \|\| FSL_LSCH2
	234	default 6 if FSL_LSCH3 \|\| MPC85xx
	235
923a8555 TR	236	config SYS_FSL_ESDHC_BE
	237	bool
	238
	239	config SYS_FSL_IFC_BE
	240	bool
	241
d43cd486 TR	242	config FSL_QIXIS
d43cd486 TR	243	bool "Enable QIXIS support"
93145335	244	depends on PPC \|\| ARCH_LS1021A \|\| FSL_LSCH2 \|\| FSL_LSCH3
d43cd486 TR	245
	246	config QIXIS_I2C_ACCESS
	247	bool "Access to QIXIS is over i2c"
	248	depends on FSL_QIXIS
	249	default y
5cc1d921 TR	250
	251	config HAS_FSL_DR_USB
	252	def_bool y
	253	depends on USB_EHCI_HCD && PPC