]>
Commit | Line | Data |
---|---|---|
d90a5a30 MY |
1 | # |
2 | # PINCTRL infrastructure and drivers | |
3 | # | |
4 | ||
5 | menu "Pin controllers" | |
6 | ||
7 | config PINCTRL | |
8 | bool "Support pin controllers" | |
9 | depends on DM | |
10 | help | |
11 | This enables the basic support for pinctrl framework. You may want | |
12 | to enable some more options depending on what you want to do. | |
13 | ||
14 | config PINCTRL_FULL | |
15 | bool "Support full pin controllers" | |
16 | depends on PINCTRL && OF_CONTROL | |
17 | default y | |
18 | help | |
19 | This provides Linux-compatible device tree interface for the pinctrl | |
20 | subsystem. This feature depends on device tree configuration because | |
21 | it parses a device tree to look for the pinctrl device which the | |
22 | peripheral device is associated with. | |
23 | ||
24 | If this option is disabled (it is the only possible choice for non-DT | |
25 | boards), the pinctrl core provides no systematic mechanism for | |
26 | identifying peripheral devices, applying needed pinctrl settings. | |
27 | It is totally up to the implementation of each low-level driver. | |
28 | You can save memory footprint in return for some limitations. | |
29 | ||
30 | config PINCTRL_GENERIC | |
31 | bool "Support generic pin controllers" | |
32 | depends on PINCTRL_FULL | |
33 | default y | |
34 | help | |
35 | Say Y here if you want to use the pinctrl subsystem through the | |
36 | generic DT interface. If enabled, some functions become available | |
37 | to parse common properties such as "pins", "groups", "functions" and | |
38 | some pin configuration parameters. It would be easier if you only | |
39 | need the generic DT interface for pin muxing and pin configuration. | |
40 | If you need to handle vendor-specific DT properties, you can disable | |
41 | this option and implement your own set_state callback in the pinctrl | |
42 | operations. | |
43 | ||
44 | config PINMUX | |
45 | bool "Support pin multiplexing controllers" | |
46 | depends on PINCTRL_GENERIC | |
47 | default y | |
48 | help | |
49 | This option enables pin multiplexing through the generic pinctrl | |
de2069c7 MB |
50 | framework. Most SoCs have their own multiplexing arrangement where |
51 | a single pin can be used for several functions. An SoC pinctrl driver | |
52 | allows the required function to be selected for each pin. | |
458a0700 | 53 | The driver is typically controlled by the device tree. |
d90a5a30 MY |
54 | |
55 | config PINCONF | |
56 | bool "Support pin configuration controllers" | |
57 | depends on PINCTRL_GENERIC | |
58 | help | |
59 | This option enables pin configuration through the generic pinctrl | |
60 | framework. | |
61 | ||
c20851b3 PD |
62 | config PINCONF_RECURSIVE |
63 | bool "Support recursive binding for pin configuration nodes" | |
64 | depends on PINCTRL_FULL | |
65 | default n if ARCH_STM32MP | |
66 | default y | |
67 | help | |
68 | In the Linux pinctrl binding, the pin configuration nodes need not be | |
69 | direct children of the pin controller device (may be grandchildren for | |
70 | example). It is define is each individual pin controller device. | |
71 | Say Y here if you want to keep this behavior with the pinconfig | |
423e324d | 72 | u-class: all sub are recursively bounded. |
c20851b3 PD |
73 | If the option is disabled, this behavior is deactivated and only |
74 | the direct children of pin controller will be assumed as pin | |
75 | configuration; you can save memory footprint when this feature is | |
76 | no needed. | |
77 | ||
d90a5a30 | 78 | config SPL_PINCTRL |
0fa0abec | 79 | bool "Support pin controllers in SPL" |
d90a5a30 MY |
80 | depends on SPL && SPL_DM |
81 | help | |
82 | This option is an SPL-variant of the PINCTRL option. | |
83 | See the help of PINCTRL for details. | |
84 | ||
8aeafb54 SG |
85 | config TPL_PINCTRL |
86 | bool "Support pin controllers in TPL" | |
87 | depends on TPL && TPL_DM | |
88 | help | |
89 | This option is an TPL variant of the PINCTRL option. | |
90 | See the help of PINCTRL for details. | |
91 | ||
d90a5a30 MY |
92 | config SPL_PINCTRL_FULL |
93 | bool "Support full pin controllers in SPL" | |
94 | depends on SPL_PINCTRL && SPL_OF_CONTROL | |
b9747696 | 95 | default n if TARGET_STM32F746_DISCO |
d90a5a30 MY |
96 | default y |
97 | help | |
98 | This option is an SPL-variant of the PINCTRL_FULL option. | |
99 | See the help of PINCTRL_FULL for details. | |
100 | ||
8aeafb54 SG |
101 | config TPL_PINCTRL_FULL |
102 | bool "Support full pin controllers in TPL" | |
103 | depends on TPL_PINCTRL && TPL_OF_CONTROL | |
104 | help | |
105 | This option is an TPL-variant of the PINCTRL_FULL option. | |
106 | See the help of PINCTRL_FULL for details. | |
107 | ||
d90a5a30 MY |
108 | config SPL_PINCTRL_GENERIC |
109 | bool "Support generic pin controllers in SPL" | |
110 | depends on SPL_PINCTRL_FULL | |
111 | default y | |
112 | help | |
113 | This option is an SPL-variant of the PINCTRL_GENERIC option. | |
114 | See the help of PINCTRL_GENERIC for details. | |
115 | ||
116 | config SPL_PINMUX | |
117 | bool "Support pin multiplexing controllers in SPL" | |
118 | depends on SPL_PINCTRL_GENERIC | |
119 | default y | |
120 | help | |
121 | This option is an SPL-variant of the PINMUX option. | |
122 | See the help of PINMUX for details. | |
458a0700 SG |
123 | The pinctrl subsystem can add a substantial overhead to the SPL |
124 | image since it typically requires quite a few tables either in the | |
125 | driver or in the device tree. If this is acceptable and you need | |
126 | to adjust pin multiplexing in SPL in order to boot into U-Boot, | |
127 | enable this option. You will need to enable device tree in SPL | |
128 | for this to work. | |
d90a5a30 MY |
129 | |
130 | config SPL_PINCONF | |
131 | bool "Support pin configuration controllers in SPL" | |
132 | depends on SPL_PINCTRL_GENERIC | |
133 | help | |
134 | This option is an SPL-variant of the PINCONF option. | |
135 | See the help of PINCONF for details. | |
136 | ||
c20851b3 PD |
137 | config SPL_PINCONF_RECURSIVE |
138 | bool "Support recursive binding for pin configuration nodes in SPL" | |
139 | depends on SPL_PINCTRL_FULL | |
140 | default n if ARCH_STM32MP | |
141 | default y | |
142 | help | |
143 | This option is an SPL-variant of the PINCONF_RECURSIVE option. | |
144 | See the help of PINCONF_RECURSIVE for details. | |
145 | ||
d90a5a30 MY |
146 | if PINCTRL || SPL_PINCTRL |
147 | ||
51c7f348 | 148 | config PINCTRL_AR933X |
a79d0643 WW |
149 | bool "QCA/Athores ar933x pin control driver" |
150 | depends on DM && SOC_AR933X | |
151 | help | |
152 | Support pin multiplexing control on QCA/Athores ar933x SoCs. | |
153 | The driver is controlled by a device tree node which contains | |
154 | both the GPIO definitions and pin control functions for each | |
155 | available multiplex function. | |
156 | ||
51c7f348 PT |
157 | config PINCTRL_AT91 |
158 | bool "AT91 pinctrl driver" | |
159 | depends on DM | |
160 | help | |
161 | This option is to enable the AT91 pinctrl driver for AT91 PIO | |
162 | controller. | |
163 | ||
164 | AT91 PIO controller is a combined gpio-controller, pin-mux and | |
165 | pin-config module. Each I/O pin may be dedicated as a general-purpose | |
166 | I/O or be assigned to a function of an embedded peripheral. Each I/O | |
167 | pin has a glitch filter providing rejection of glitches lower than | |
168 | one-half of peripheral clock cycle and a debouncing filter providing | |
169 | rejection of unwanted pulses from key or push button operations. You | |
170 | can also control the multi-driver capability, pull-up and pull-down | |
171 | feature on each I/O pin. | |
172 | ||
173 | config PINCTRL_AT91PIO4 | |
174 | bool "AT91 PIO4 pinctrl driver" | |
175 | depends on DM | |
176 | help | |
177 | This option is to enable the AT91 pinctrl driver for AT91 PIO4 | |
178 | controller which is available on SAMA5D2 SoC. | |
179 | ||
74749f1e SG |
180 | config PINCTRL_INTEL |
181 | bool "Standard Intel pin-control and pin-mux driver" | |
182 | help | |
183 | Recent Intel chips such as Apollo Lake (APL) use a common pin control | |
184 | and GPIO scheme. The settings for this come from an SoC-specific | |
185 | driver which must be separately enabled. The driver supports setting | |
186 | pins on start-up and changing the GPIO attributes. | |
187 | ||
51c7f348 PT |
188 | config PINCTRL_PIC32 |
189 | bool "Microchip PIC32 pin-control and pin-mux driver" | |
190 | depends on DM && MACH_PIC32 | |
191 | default y | |
192 | help | |
193 | Supports individual pin selection and configuration for each | |
194 | remappable peripheral available on Microchip PIC32 | |
195 | SoCs. This driver is controlled by a device tree node which | |
cb4d1bbe | 196 | contains both GPIO definition and pin control functions. |
51c7f348 PT |
197 | |
198 | config PINCTRL_QCA953X | |
c102453a WW |
199 | bool "QCA/Athores qca953x pin control driver" |
200 | depends on DM && SOC_QCA953X | |
201 | help | |
202 | Support pin multiplexing control on QCA/Athores qca953x SoCs. | |
c102453a | 203 | |
51c7f348 PT |
204 | The driver is controlled by a device tree node which contains both |
205 | the GPIO definitions and pin control functions for each available | |
206 | multiplex function. | |
207 | ||
5990b059 HS |
208 | config PINCTRL_QE |
209 | bool "QE based pinctrl driver, like on mpc83xx" | |
210 | depends on DM | |
211 | help | |
212 | This option is to enable the QE pinctrl driver for QE based io | |
213 | controller. | |
214 | ||
09aa7c46 AY |
215 | config PINCTRL_ROCKCHIP_RV1108 |
216 | bool "Rockchip rv1108 pin control driver" | |
217 | depends on DM | |
218 | help | |
219 | Support pin multiplexing control on Rockchip rv1108 SoC. | |
220 | ||
221 | The driver is controlled by a device tree node which contains | |
222 | both the GPIO definitions and pin control functions for each | |
223 | available multiplex function. | |
224 | ||
9c6a3c67 MY |
225 | config PINCTRL_SANDBOX |
226 | bool "Sandbox pinctrl driver" | |
227 | depends on SANDBOX | |
228 | help | |
51c7f348 | 229 | This enables pinctrl driver for sandbox. |
9c6a3c67 | 230 | |
51c7f348 PT |
231 | Currently, this driver actually does nothing but print debug |
232 | messages when pinctrl operations are invoked. | |
233 | ||
234 | config PINCTRL_SINGLE | |
235 | bool "Single register pin-control and pin-multiplex driver" | |
236 | depends on DM | |
5f266c60 | 237 | help |
51c7f348 PT |
238 | This enables pinctrl driver for systems using a single register for |
239 | pin configuration and multiplexing. TI's AM335X SoCs are examples of | |
240 | such systems. | |
241 | ||
242 | Depending on the platform make sure to also enable OF_TRANSLATE and | |
243 | eventually SPL_OF_TRANSLATE to get correct address translations. | |
5f266c60 | 244 | |
0c563102 PC |
245 | config PINCTRL_STI |
246 | bool "STMicroelectronics STi pin-control and pin-mux driver" | |
247 | depends on DM && ARCH_STI | |
248 | default y | |
249 | help | |
250 | Support pin multiplexing control on STMicrolectronics STi SoCs. | |
51c7f348 | 251 | |
0c563102 | 252 | The driver is controlled by a device tree node which contains both |
51c7f348 PT |
253 | the GPIO definitions and pin control functions for each available |
254 | multiplex function. | |
0c563102 | 255 | |
94d53084 VM |
256 | config PINCTRL_STM32 |
257 | bool "ST STM32 pin control driver" | |
258 | depends on DM | |
259 | help | |
51c7f348 | 260 | Supports pin multiplexing control on stm32 SoCs. |
94d53084 | 261 | |
51c7f348 PT |
262 | The driver is controlled by a device tree node which contains both |
263 | the GPIO definitions and pin control functions for each available | |
264 | multiplex function. | |
44d5c371 | 265 | |
8262435d PD |
266 | config PINCTRL_STMFX |
267 | bool "STMicroelectronics STMFX I2C GPIO expander pinctrl driver" | |
268 | depends on DM && PINCTRL_FULL | |
269 | help | |
270 | I2C driver for STMicroelectronics Multi-Function eXpander (STMFX) | |
271 | GPIO expander. | |
272 | Supports pin multiplexing control on stm32 SoCs. | |
273 | ||
274 | The driver is controlled by a device tree node which contains both | |
275 | the GPIO definitions and pin control functions for each available | |
276 | multiplex function. | |
277 | ||
278 | config SPL_PINCTRL_STMFX | |
279 | bool "STMicroelectronics STMFX I2C GPIO expander pinctrl driver in SPL" | |
280 | depends on SPL_PINCTRL_FULL | |
281 | help | |
282 | This option is an SPL-variant of the SPL_PINCTRL_STMFX option. | |
283 | See the help of PINCTRL_STMFX for details. | |
284 | ||
4f0e44e4 | 285 | config ASPEED_AST2500_PINCTRL |
171fd224 MS |
286 | bool "Aspeed AST2500 pin control driver" |
287 | depends on DM && PINCTRL_GENERIC && ASPEED_AST2500 | |
288 | default y | |
289 | help | |
290 | Support pin multiplexing control on Aspeed ast2500 SoC. The driver | |
291 | uses Generic Pinctrl framework and is compatible with the Linux | |
292 | driver, i.e. it uses the same device tree configuration. | |
4f0e44e4 | 293 | |
7224d5cc SA |
294 | config PINCTRL_K210 |
295 | bool "Kendryte K210 Fully-Programmable Input/Output Array driver" | |
296 | depends on DM && PINCTRL_GENERIC | |
297 | help | |
298 | Support pin multiplexing on the K210. The "FPIOA" can remap any | |
299 | supported function to any multifunctional IO pin. It can also perform | |
300 | basic GPIO functions, such as reading the current value of a pin. | |
d90a5a30 MY |
301 | endif |
302 | ||
efc46771 PT |
303 | source "drivers/pinctrl/broadcom/Kconfig" |
304 | source "drivers/pinctrl/exynos/Kconfig" | |
74749f1e | 305 | source "drivers/pinctrl/intel/Kconfig" |
01aa9d1d | 306 | source "drivers/pinctrl/mediatek/Kconfig" |
efc46771 PT |
307 | source "drivers/pinctrl/meson/Kconfig" |
308 | source "drivers/pinctrl/mscc/Kconfig" | |
3fad441c | 309 | source "drivers/pinctrl/mtmips/Kconfig" |
efc46771 | 310 | source "drivers/pinctrl/mvebu/Kconfig" |
8d393b2c | 311 | source "drivers/pinctrl/nexell/Kconfig" |
745df68d | 312 | source "drivers/pinctrl/nxp/Kconfig" |
910df4d0 | 313 | source "drivers/pinctrl/renesas/Kconfig" |
5a127325 | 314 | source "drivers/pinctrl/rockchip/Kconfig" |
5dc626f8 MY |
315 | source "drivers/pinctrl/uniphier/Kconfig" |
316 | ||
d90a5a30 | 317 | endmenu |