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Merge branch 'master' of git://git.denx.de/u-boot-at91
[J-u-boot.git] / cpu / mpc8xx / scc.c
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ed247f48
WD		 1/*
2 * File: scc.c
3 * Description:
53677ef1 4 * Basic ET HW initialization and packet RX/TX routines
ed247f48
WD		 5 *
6 * NOTE <<<IMPORTANT: PLEASE READ>>>:
7 * Do not cache Rx/Tx buffers!
8 */
9
10/*
11 * MPC823 <-> MC68160 Connections:
12 *
13 * Setup MPC823 to work with MC68160 Enhanced Ethernet
14 * Serial Tranceiver as follows:
15 *
16 * MPC823 Signal MC68160 Comments
17 * ------ ------ ------- --------
18 * PA-12 ETHTX --------> TX Eth. Port Transmit Data
19 * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
20 * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
21 * PA-13 ETHRX <-------- RX Eth. Port Receive Data
22 * PC-8 E_RENA <-------- RENA Eth. Receive Enable
23 * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
24 * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
25 *
26 * FADS Board Signal MC68160 Comments
27 * ----------------- ------- --------
28 * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
29 * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
30 * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
31 * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
32 *
33 */
34
35#include <common.h>
36#include <malloc.h>
37#include <commproc.h>
38#include <net.h>
39#include <command.h>
40
4431283c 41#if defined(CONFIG_CMD_NET) && defined(SCC_ENET)
ed247f48
WD		 42
43/* Ethernet Transmit and Receive Buffers */
44#define DBUF_LENGTH 1520
45
46#define TX_BUF_CNT 2
47
2729af9d 48#define TOUT_LOOP 10000 /* 10 ms to have a packet sent */
ed247f48
WD		 49
50static char txbuf[DBUF_LENGTH];
51
52static uint rxIdx; /* index of the current RX buffer */
53static uint txIdx; /* index of the current TX buffer */
54
55/*
56 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
57 * immr->udata_bd address on Dual-Port RAM
58 * Provide for Double Buffering
59 */
60
61typedef volatile struct CommonBufferDescriptor {
62 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
63 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
64} RTXBD;
65
66static RTXBD *rtx;
67
68static int scc_send(struct eth_device* dev, volatile void *packet, int length);
69static int scc_recv(struct eth_device* dev);
70static int scc_init (struct eth_device* dev, bd_t * bd);
71static void scc_halt(struct eth_device* dev);
72
73int scc_initialize(bd_t *bis)
74{
75 struct eth_device* dev;
76
77 dev = (struct eth_device*) malloc(sizeof *dev);
7f6c2cbc 78 memset(dev, 0, sizeof *dev);
ed247f48
WD		 79
80 sprintf(dev->name, "SCC ETHERNET");
81 dev->iobase = 0;
82 dev->priv = 0;
83 dev->init = scc_init;
84 dev->halt = scc_halt;
85 dev->send = scc_send;
86 dev->recv = scc_recv;
87
88 eth_register(dev);
89
90 return 1;
91}
92
93static int scc_send(struct eth_device* dev, volatile void *packet, int length)
94{
95 int i, j=0;
96#if 0
97 volatile char *in, *out;
98#endif
99
100 /* section 16.9.23.3
101 * Wait for ready
102 */
103#if 0
104 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
105 out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
106 in = packet;
107 for(i = 0; i < length; i++) {
108 *out++ = *in++;
109 }
110 rtx->txbd[txIdx].cbd_datlen = length;
111 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
112 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
113
114#ifdef ET_DEBUG
115 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
116#endif
117 i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
118
119 /* wrap around buffer index when necessary */
120 if (txIdx >= TX_BUF_CNT) txIdx = 0;
121#endif
122
123 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
124 udelay (1); /* will also trigger Wd if needed */
125 j++;
126 }
127 if (j>=TOUT_LOOP) printf("TX not ready\n");
128 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
129 rtx->txbd[txIdx].cbd_datlen = length;
130 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
131 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
132 udelay (1); /* will also trigger Wd if needed */
133 j++;
134 }
135 if (j>=TOUT_LOOP) printf("TX timeout\n");
136#ifdef ET_DEBUG
137 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
138#endif
139 i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
140 return i;
141}
142
3bbc899f 143static int scc_recv (struct eth_device *dev)
ed247f48
WD		 144{
145 int length;
146
3bbc899f
WD		 147 for (;;) {
148 /* section 16.9.23.2 */
149 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
150 length = -1;
151 break; /* nothing received - leave for() loop */
152 }
ed247f48 153
3bbc899f 154 length = rtx->rxbd[rxIdx].cbd_datlen;
ed247f48 155
3bbc899f 156 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
ed247f48 157#ifdef ET_DEBUG
3bbc899f 158 printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
ed247f48 159#endif
3bbc899f
WD		 160 } else {
161 /* Pass the packet up to the protocol layers. */
162 NetReceive (NetRxPackets[rxIdx], length - 4);
163 }
164
165
166 /* Give the buffer back to the SCC. */
167 rtx->rxbd[rxIdx].cbd_datlen = 0;
168
169 /* wrap around buffer index when necessary */
170 if ((rxIdx + 1) >= PKTBUFSRX) {
171 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
172 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
173 rxIdx = 0;
174 } else {
175 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
176 rxIdx++;
177 }
ed247f48 178 }
3bbc899f 179 return length;
ed247f48
WD		 180}
181
182/**************************************************************
183 *
184 * SCC Ethernet Initialization Routine
185 *
186 *************************************************************/
187
3bbc899f 188static int scc_init (struct eth_device *dev, bd_t * bis)
ed247f48
WD		 189{
190
3bbc899f
WD		 191 int i;
192 scc_enet_t *pram_ptr;
ed247f48 193
6d0f6bcf 194 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ed247f48 195
281e00a3
WD		 196#if defined(CONFIG_LWMON)
197 reset_phy();
198#endif
199
2535d602
WD		 200#ifdef CONFIG_FADS
201#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
3bbc899f
WD		 202 /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
203 *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
204 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
205 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
ed247f48 206#else
3bbc899f
WD		 207 *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
208 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
209 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
ed247f48
WD		 210#endif
211#endif
212
3bbc899f 213 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
ed247f48 214
3bbc899f
WD		 215 rxIdx = 0;
216 txIdx = 0;
ed247f48 217
5fdc215f 218 if (!rtx) {
6d0f6bcf 219#ifdef CONFIG_SYS_ALLOC_DPRAM
5fdc215f
WD		 220 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
221 dpram_alloc_align (sizeof (RTXBD), 8));
ed247f48 222#else
5fdc215f
WD		 223 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
224#endif
225 }
ed247f48
WD		 226
227#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
3bbc899f
WD		 228 /* Configure port A pins for Txd and Rxd.
229 */
230 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
231 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
232 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
ed247f48 233#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
3bbc899f
WD		 234 /* Configure port B pins for Txd and Rxd.
235 */
236 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
237 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
238 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
ed247f48
WD		 239#else
240#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
241#endif
242
243#if defined(PC_ENET_LBK)
3bbc899f
WD		 244 /* Configure port C pins to disable External Loopback
245 */
246 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
247 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
248 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
249 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
250#endif /* PC_ENET_LBK */
251
252 /* Configure port C pins to enable CLSN and RENA.
253 */
254 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
255 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
256 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
257
258 /* Configure port A for TCLK and RCLK.
259 */
260 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
261 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
262
263 /*
264 * Configure Serial Interface clock routing -- see section 16.7.5.3
265 * First, clear all SCC bits to zero, then set the ones we want.
266 */
267
268 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
269 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
270
271
272 /*
273 * Initialize SDCR -- see section 16.9.23.7
274 * SDMA configuration register
275 */
276 immr->im_siu_conf.sc_sdcr = 0x01;
277
278
279 /*
280 * Setup SCC Ethernet Parameter RAM
281 */
282
283 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
284 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
285
286 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
287
288 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
289 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
290
291 /*
292 * Setup Receiver Buffer Descriptors (13.14.24.18)
293 * Settings:
294 * Empty, Wrap
295 */
296
297 for (i = 0; i < PKTBUFSRX; i++) {
298 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
299 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
300 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
301 }
302
303 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
304
305 /*
306 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
307 * Settings:
308 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
309 */
310
311 for (i = 0; i < TX_BUF_CNT; i++) {
312 rtx->txbd[i].cbd_sc =
313 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
314 rtx->txbd[i].cbd_datlen = 0; /* Reset */
315 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
316 }
317
318 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
319
320 /*
321 * Enter Command: Initialize Rx Params for SCC
322 */
323
324 do { /* Spin until ready to issue command */
325 __asm__ ("eieio");
326 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
327 /* Issue command */
328 immr->im_cpm.cp_cpcr =
329 ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
330 do { /* Spin until command processed */
331 __asm__ ("eieio");
332 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
333
334 /*
335 * Ethernet Specific Parameter RAM
336 * see table 13-16, pg. 660,
337 * pg. 681 (example with suggested settings)
338 */
339
340 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
341 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
342 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
343 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
344 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
345 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
346
347 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
348 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
349 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
350
351 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
352 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
353
354 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
355 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
356 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
357 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
ed247f48
WD		 358
359#define ea eth_get_dev()->enetaddr
3bbc899f
WD		 360 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
361 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
362 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
ed247f48
WD		 363#undef ea
364
3bbc899f
WD		 365 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
366 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
367 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
368 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
369 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
370 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
371 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
372 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
373
374 /*
375 * Enter Command: Initialize Tx Params for SCC
376 */
377
378 do { /* Spin until ready to issue command */
379 __asm__ ("eieio");
380 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
381 /* Issue command */
382 immr->im_cpm.cp_cpcr =
383 ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
384 do { /* Spin until command processed */
385 __asm__ ("eieio");
386 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
387
388 /*
389 * Mask all Events in SCCM - we use polling mode
390 */
391 immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
392
393 /*
394 * Clear Events in SCCE -- Clear bits by writing 1's
395 */
396
397 immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
398
399
400 /*
401 * Initialize GSMR High 32-Bits
402 * Settings: Normal Mode
403 */
404
405 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
406
407 /*
408 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
409 * Settings:
410 * TCI = Invert
411 * TPL = 48 bits
412 * TPP = Repeating 10's
413 * MODE = Ethernet
414 */
415
416 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
417 SCC_GSMRL_TPL_48 |
418 SCC_GSMRL_TPP_10 |
419 SCC_GSMRL_MODE_ENET);
420
421 /*
422 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
423 */
424
425 immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
426
427 /*
428 * Initialize the PSMR
429 * Settings:
430 * CRC = 32-Bit CCITT
431 * NIB = Begin searching for SFD 22 bits after RENA
432 * FDE = Full Duplex Enable
433 * LPB = Loopback Enable (Needed when FDE is set)
434 * BRO = Reject broadcast packets
435 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
436 */
437 immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
438 SCC_PSMR_NIB22 |
ed247f48 439#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
3bbc899f 440 SCC_PSMR_FDE | SCC_PSMR_LPB |
ed247f48
WD		 441#endif
442#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
3bbc899f 443 SCC_PSMR_BRO |
ed247f48
WD		 444#endif
445#if defined(CONFIG_SCC_ENET_PROMISCOUS)
3bbc899f 446 SCC_PSMR_PRO |
ed247f48 447#endif
3bbc899f 448 0;
ed247f48 449
3bbc899f
WD		 450 /*
451 * Configure Ethernet TENA Signal
452 */
ed247f48
WD		 453
454#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
3bbc899f
WD		 455 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
456 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
ed247f48 457#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
3bbc899f
WD		 458 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
459 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
ed247f48
WD		 460#else
461#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
462#endif
463
464#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
3bbc899f
WD		 465 /*
466 * Port C is used to control the PHY,MC68160.
467 */
468 immr->im_ioport.iop_pcdir |=
469 (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
ed247f48 470
3bbc899f
WD		 471 immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
472 immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
473 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
474#endif /* MPC860ADS */
ed247f48
WD		 475
476#if defined(CONFIG_AMX860)
3bbc899f
WD		 477 /*
478 * Port B is used to control the PHY,MC68160.
479 */
480 immr->im_cpm.cp_pbdir |=
481 (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
ed247f48 482
3bbc899f
WD		 483 immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
484 immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
ed247f48 485
3bbc899f
WD		 486 immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
487 immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
488#endif /* AMX860 */
ed247f48
WD		 489
490#ifdef CONFIG_RPXCLASSIC
3bbc899f
WD		 491 *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
492 *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
ed247f48
WD		 493#endif
494
495#ifdef CONFIG_RPXLITE
3bbc899f 496 *((uchar *) BCSR0) |= BCSR0_ETHEN;
ed247f48
WD		 497#endif
498
3bbc899f
WD		 499#if defined(CONFIG_QS860T)
500 /*
501 * PB27=FDE-, set output low for full duplex
502 * PB26=Link Test Enable, normally high output
503 */
504 immr->im_cpm.cp_pbdir |= 0x00000030;
505 immr->im_cpm.cp_pbdat |= 0x00000020;
506 immr->im_cpm.cp_pbdat &= ~0x00000010;
507#endif /* QS860T */
508
ed247f48 509#ifdef CONFIG_MBX
3bbc899f 510 board_ether_init ();
ed247f48
WD		 511#endif
512
513#if defined(CONFIG_NETVIA)
993cad93 514#if defined(PA_ENET_PDN)
3bbc899f
WD		 515 immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
516 immr->im_ioport.iop_padir |= PA_ENET_PDN;
517 immr->im_ioport.iop_padat |= PA_ENET_PDN;
993cad93 518#elif defined(PB_ENET_PDN)
3bbc899f
WD		 519 immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
520 immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
521 immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
ed247f48 522#elif defined(PC_ENET_PDN)
3bbc899f
WD		 523 immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
524 immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
525 immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
993cad93 526#elif defined(PD_ENET_PDN)
3bbc899f
WD		 527 immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
528 immr->im_ioport.iop_pddir |= PD_ENET_PDN;
529 immr->im_ioport.iop_pddat |= PD_ENET_PDN;
ed247f48
WD		 530#endif
531#endif
532
3bbc899f
WD		 533 /*
534 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
535 */
ed247f48 536
3bbc899f
WD		 537 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
538 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
ed247f48 539
3bbc899f
WD		 540 /*
541 * Work around transmit problem with first eth packet
542 */
ed247f48 543#if defined (CONFIG_FADS)
3bbc899f 544 udelay (10000); /* wait 10 ms */
ed247f48 545#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
3bbc899f 546 udelay (100000); /* wait 100 ms */
ed247f48
WD		 547#endif
548
3bbc899f 549 return 1;
ed247f48
WD		 550}
551
552
3bbc899f 553static void scc_halt (struct eth_device *dev)
ed247f48 554{
6d0f6bcf 555 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
3bbc899f
WD		 556
557 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
558 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
281e00a3
WD		 559
560 immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
ed247f48
WD		 561}
562
563#if 0
3bbc899f 564void restart (void)
ed247f48 565{
6d0f6bcf 566 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
3bbc899f
WD		 567
568 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
569 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
ed247f48
WD		 570}
571#endif
068b60a0 572#endif
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