[J-u-boot.git] / drivers / net / dwc_eth_qos_rockchip.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright Contributors to the U-Boot project.
 *
 * rk_gmac_ops ported from linux drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
 *
 * Ported code is intentionally left as close as possible with linux counter
 * part in order to simplify future porting of fixes and support for other SoCs.
 */

#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <net.h>
#include <phy.h>
#include <regmap.h>
#include <reset.h>
#include <syscon.h>
#include <asm/gpio.h>
#include <linux/delay.h>

#include "dwc_eth_qos.h"

struct rk_gmac_ops {
	const char *compatible;
	int (*set_to_rgmii)(struct udevice *dev,
			    int tx_delay, int rx_delay);
	int (*set_to_rmii)(struct udevice *dev);
	int (*set_gmac_speed)(struct udevice *dev);
	void (*set_clock_selection)(struct udevice *dev, bool enable);
	u32 regs[3];
};

struct rockchip_platform_data {
	struct reset_ctl_bulk resets;
	const struct rk_gmac_ops *ops;
	int id;
	bool clock_input;
	struct regmap *grf;
	struct regmap *php_grf;
};

#define HIWORD_UPDATE(val, mask, shift) \
		((val) << (shift) | (mask) << ((shift) + 16))

#define GRF_BIT(nr)	(BIT(nr) | BIT((nr) + 16))
#define GRF_CLR_BIT(nr)	(BIT((nr) + 16))

#define RK3568_GRF_GMAC0_CON0		0x0380
#define RK3568_GRF_GMAC0_CON1		0x0384
#define RK3568_GRF_GMAC1_CON0		0x0388
#define RK3568_GRF_GMAC1_CON1		0x038c

/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
#define RK3568_GMAC_PHY_INTF_SEL_RGMII	\
		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
#define RK3568_GMAC_PHY_INTF_SEL_RMII	\
		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
#define RK3568_GMAC_FLOW_CTRL			GRF_BIT(3)
#define RK3568_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(3)
#define RK3568_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
#define RK3568_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(1)
#define RK3568_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
#define RK3568_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(0)

/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
#define RK3568_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
#define RK3568_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)

static int rk3568_set_to_rgmii(struct udevice *dev,
			       int tx_delay, int rx_delay)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	u32 con0, con1;

	con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
				 RK3568_GRF_GMAC0_CON0;
	con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
				 RK3568_GRF_GMAC0_CON1;

	regmap_write(data->grf, con0,
		     RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
		     RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));

	regmap_write(data->grf, con1,
		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
		     RK3568_GMAC_RXCLK_DLY_ENABLE |
		     RK3568_GMAC_TXCLK_DLY_ENABLE);

	return 0;
}

static int rk3568_set_to_rmii(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	u32 con1;

	con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
				 RK3568_GRF_GMAC0_CON1;
	regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);

	return 0;
}

static int rk3568_set_gmac_speed(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	ulong rate;
	int ret;

	switch (eqos->phy->speed) {
	case SPEED_10:
		rate = 2500000;
		break;
	case SPEED_100:
		rate = 25000000;
		break;
	case SPEED_1000:
		rate = 125000000;
		break;
	default:
		return -EINVAL;
	}

	ret = clk_set_rate(&eqos->clk_tx, rate);
	if (ret < 0)
		return ret;

	return 0;
}

/* sys_grf */
#define RK3588_GRF_GMAC_CON7			0x031c
#define RK3588_GRF_GMAC_CON8			0x0320
#define RK3588_GRF_GMAC_CON9			0x0324

#define RK3588_GMAC_RXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 3)
#define RK3588_GMAC_RXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 3)
#define RK3588_GMAC_TXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 2)
#define RK3588_GMAC_TXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 2)

#define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
#define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)

/* php_grf */
#define RK3588_GRF_GMAC_CON0			0x0008
#define RK3588_GRF_CLK_CON1			0x0070

#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)	\
	(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
#define RK3588_GMAC_PHY_INTF_SEL_RMII(id)	\
	(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))

#define RK3588_GMAC_CLK_RMII_MODE(id)		GRF_BIT(5 * (id))
#define RK3588_GMAC_CLK_RGMII_MODE(id)		GRF_CLR_BIT(5 * (id))

#define RK3588_GMAC_CLK_SELET_CRU(id)		GRF_BIT(5 * (id) + 4)
#define RK3588_GMAC_CLK_SELET_IO(id)		GRF_CLR_BIT(5 * (id) + 4)

#define RK3588_GMAC_CLK_RMII_DIV2(id)		GRF_BIT(5 * (id) + 2)
#define RK3588_GMAC_CLK_RMII_DIV20(id)		GRF_CLR_BIT(5 * (id) + 2)

#define RK3588_GMAC_CLK_RGMII_DIV1(id)		\
			(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
#define RK3588_GMAC_CLK_RGMII_DIV5(id)		\
			(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
#define RK3588_GMAC_CLK_RGMII_DIV50(id)		\
			(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))

#define RK3588_GMAC_CLK_RMII_GATE(id)		GRF_BIT(5 * (id) + 1)
#define RK3588_GMAC_CLK_RMII_NOGATE(id)		GRF_CLR_BIT(5 * (id) + 1)

static int rk3588_set_to_rgmii(struct udevice *dev,
			       int tx_delay, int rx_delay)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	u32 offset_con, id = data->id;

	offset_con = data->id == 1 ? RK3588_GRF_GMAC_CON9 :
				     RK3588_GRF_GMAC_CON8;

	regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
		     RK3588_GMAC_PHY_INTF_SEL_RGMII(id));

	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
		     RK3588_GMAC_CLK_RGMII_MODE(id));

	regmap_write(data->grf, RK3588_GRF_GMAC_CON7,
		     RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
		     RK3588_GMAC_TXCLK_DLY_ENABLE(id));

	regmap_write(data->grf, offset_con,
		     RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
		     RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));

	return 0;
}

static int rk3588_set_to_rmii(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
		     RK3588_GMAC_PHY_INTF_SEL_RMII(data->id));

	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
		     RK3588_GMAC_CLK_RMII_MODE(data->id));

	return 0;
}

static int rk3588_set_gmac_speed(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	u32 val = 0, id = data->id;

	switch (eqos->phy->speed) {
	case SPEED_10:
		if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
			val = RK3588_GMAC_CLK_RMII_DIV20(id);
		else
			val = RK3588_GMAC_CLK_RGMII_DIV50(id);
		break;
	case SPEED_100:
		if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
			val = RK3588_GMAC_CLK_RMII_DIV2(id);
		else
			val = RK3588_GMAC_CLK_RGMII_DIV5(id);
		break;
	case SPEED_1000:
		if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
			val = RK3588_GMAC_CLK_RGMII_DIV1(id);
		else
			return -EINVAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);

	return 0;
}

static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	u32 val = data->clock_input ? RK3588_GMAC_CLK_SELET_IO(data->id) :
				      RK3588_GMAC_CLK_SELET_CRU(data->id);

	val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :
			RK3588_GMAC_CLK_RMII_GATE(data->id);

	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
}

static const struct rk_gmac_ops rk_gmac_ops[] = {
	{
		.compatible = "rockchip,rk3568-gmac",
		.set_to_rgmii = rk3568_set_to_rgmii,
		.set_to_rmii = rk3568_set_to_rmii,
		.set_gmac_speed = rk3568_set_gmac_speed,
		.regs = {
			0xfe2a0000, /* gmac0 */
			0xfe010000, /* gmac1 */
			0x0, /* sentinel */
		},
	},
	{
		.compatible = "rockchip,rk3588-gmac",
		.set_to_rgmii = rk3588_set_to_rgmii,
		.set_to_rmii = rk3588_set_to_rmii,
		.set_gmac_speed = rk3588_set_gmac_speed,
		.set_clock_selection = rk3588_set_clock_selection,
		.regs = {
			0xfe1b0000, /* gmac0 */
			0xfe1c0000, /* gmac1 */
			0x0, /* sentinel */
		},
	},
	{ }
};

static const struct rk_gmac_ops *get_rk_gmac_ops(struct udevice *dev)
{
	const struct rk_gmac_ops *ops = rk_gmac_ops;

	while (ops->compatible) {
		if (device_is_compatible(dev, ops->compatible))
			return ops;
		ops++;
	}

	return NULL;
}

static int eqos_probe_resources_rk(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data;
	const char *clock_in_out;
	int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
	int ret;

	ret = eqos_get_base_addr_dt(dev);
	if (ret) {
		dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret);
		return ret;
	}

	data = calloc(1, sizeof(struct rockchip_platform_data));
	if (!data)
		return -ENOMEM;

	data->ops = get_rk_gmac_ops(dev);
	if (!data->ops) {
		ret = -EINVAL;
		goto err_free;
	}

	for (int i = 0; data->ops->regs[i]; i++) {
		if (data->ops->regs[i] == (u32)eqos->regs) {
			data->id = i;
			break;
		}
	}

	pdata->priv_pdata = data;
	pdata->phy_interface = eqos->config->interface(dev);
	pdata->max_speed = eqos->max_speed;

	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
		pr_err("Invalid PHY interface\n");
		ret = -EINVAL;
		goto err_free;
	}

	data->grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
	if (IS_ERR(data->grf)) {
		dev_err(dev, "Missing rockchip,grf property\n");
		ret = -EINVAL;
		goto err_free;
	}

	if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
		data->php_grf =
			syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
		if (IS_ERR(data->php_grf)) {
			dev_err(dev, "Missing rockchip,php-grf property\n");
			ret = -EINVAL;
			goto err_free;
		}
	}

	ret = reset_get_bulk(dev, &data->resets);
	if (ret < 0)
		goto err_free;

	reset_assert_bulk(&data->resets);

	ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
	if (ret) {
		dev_dbg(dev, "clk_get_by_name(stmmaceth) failed: %d", ret);
		goto err_release_resets;
	}

	if (device_is_compatible(dev, "rockchip,rk3568-gmac")) {
		ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
		if (ret) {
			dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
			goto err_release_resets;
		}
	}

	clock_in_out = dev_read_string(dev, "clock_in_out");
	if (clock_in_out && !strcmp(clock_in_out, "input"))
		data->clock_input = true;
	else
		data->clock_input = false;

	/* snps,reset props are deprecated, do bare minimum to support them */
	if (dev_read_bool(dev, "snps,reset-active-low"))
		reset_flags |= GPIOD_ACTIVE_LOW;

	dev_read_u32_array(dev, "snps,reset-delays-us", eqos->reset_delays, 3);

	gpio_request_by_name(dev, "snps,reset-gpio", 0,
			     &eqos->phy_reset_gpio, reset_flags);

	return 0;

err_release_resets:
	reset_release_bulk(&data->resets);
err_free:
	free(data);

	return ret;
}

static int eqos_remove_resources_rk(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
		dm_gpio_free(dev, &eqos->phy_reset_gpio);

	reset_release_bulk(&data->resets);
	free(data);

	return 0;
}

static int eqos_stop_resets_rk(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	return reset_assert_bulk(&data->resets);
}

static int eqos_start_resets_rk(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	return reset_deassert_bulk(&data->resets);
}

static int eqos_stop_clks_rk(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	if (data->ops->set_clock_selection)
		data->ops->set_clock_selection(dev, false);

	return 0;
}

static int eqos_start_clks_rk(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	int tx_delay, rx_delay, ret;

	if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
		udelay(eqos->reset_delays[1]);

		ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
		if (ret < 0)
			return ret;

		udelay(eqos->reset_delays[2]);
	}

	if (data->ops->set_clock_selection)
		data->ops->set_clock_selection(dev, true);

	tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
	rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);

	switch (pdata->phy_interface) {
	case PHY_INTERFACE_MODE_RGMII:
		return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
	case PHY_INTERFACE_MODE_RGMII_ID:
		return data->ops->set_to_rgmii(dev, 0, 0);
	case PHY_INTERFACE_MODE_RGMII_RXID:
		return data->ops->set_to_rgmii(dev, tx_delay, 0);
	case PHY_INTERFACE_MODE_RGMII_TXID:
		return data->ops->set_to_rgmii(dev, 0, rx_delay);
	case PHY_INTERFACE_MODE_RMII:
		return data->ops->set_to_rmii(dev);
	}

	return -EINVAL;
}

static int eqos_set_tx_clk_speed_rk(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	return data->ops->set_gmac_speed(dev);
}

static ulong eqos_get_tick_clk_rate_rk(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);

	return clk_get_rate(&eqos->clk_master_bus);
}

static struct eqos_ops eqos_rockchip_ops = {
	.eqos_inval_desc = eqos_inval_desc_generic,
	.eqos_flush_desc = eqos_flush_desc_generic,
	.eqos_inval_buffer = eqos_inval_buffer_generic,
	.eqos_flush_buffer = eqos_flush_buffer_generic,
	.eqos_probe_resources = eqos_probe_resources_rk,
	.eqos_remove_resources = eqos_remove_resources_rk,
	.eqos_stop_resets = eqos_stop_resets_rk,
	.eqos_start_resets = eqos_start_resets_rk,
	.eqos_stop_clks = eqos_stop_clks_rk,
	.eqos_start_clks = eqos_start_clks_rk,
	.eqos_calibrate_pads = eqos_null_ops,
	.eqos_disable_calibration = eqos_null_ops,
	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_rk,
	.eqos_get_enetaddr = eqos_null_ops,
	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_rk,
};

struct eqos_config eqos_rockchip_config = {
	.reg_access_always_ok = false,
	.mdio_wait = 10,
	.swr_wait = 50,
	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
	.axi_bus_width = EQOS_AXI_WIDTH_64,
	.interface = dev_read_phy_mode,
	.ops = &eqos_rockchip_ops,
};
Commit	Line	Data
8e76ff61 JK	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* Copyright Contributors to the U-Boot project.
	4	*
	5	* rk_gmac_ops ported from linux drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
	6	*
	7	* Ported code is intentionally left as close as possible with linux counter
	8	* part in order to simplify future porting of fixes and support for other SoCs.
	9	*/
	10
8e76ff61 JK	11	#include <clk.h>
	12	#include <dm.h>
	13	#include <dm/device_compat.h>
	14	#include <net.h>
	15	#include <phy.h>
	16	#include <regmap.h>
	17	#include <reset.h>
	18	#include <syscon.h>
	19	#include <asm/gpio.h>
	20	#include <linux/delay.h>
	21
	22	#include "dwc_eth_qos.h"
	23
	24	struct rk_gmac_ops {
	25	const char *compatible;
	26	int (set_to_rgmii)(struct udevice dev,
	27	int tx_delay, int rx_delay);
	28	int (set_to_rmii)(struct udevice dev);
	29	int (set_gmac_speed)(struct udevice dev);
01b8ed47	30	void (set_clock_selection)(struct udevice dev, bool enable);
8e76ff61 JK	31	u32 regs[3];
	32	};
	33
	34	struct rockchip_platform_data {
	35	struct reset_ctl_bulk resets;
	36	const struct rk_gmac_ops *ops;
	37	int id;
01b8ed47	38	bool clock_input;
8e76ff61	39	struct regmap *grf;
01b8ed47	40	struct regmap *php_grf;
8e76ff61 JK	41	};
	42
	43	#define HIWORD_UPDATE(val, mask, shift) \
	44	((val) << (shift) \| (mask) << ((shift) + 16))
	45
	46	#define GRF_BIT(nr) (BIT(nr) \| BIT((nr) + 16))
	47	#define GRF_CLR_BIT(nr) (BIT((nr) + 16))
	48
	49	#define RK3568_GRF_GMAC0_CON0 0x0380
	50	#define RK3568_GRF_GMAC0_CON1 0x0384
	51	#define RK3568_GRF_GMAC1_CON0 0x0388
	52	#define RK3568_GRF_GMAC1_CON1 0x038c
	53
	54	/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
	55	#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
	56	(GRF_BIT(4) \| GRF_CLR_BIT(5) \| GRF_CLR_BIT(6))
	57	#define RK3568_GMAC_PHY_INTF_SEL_RMII \
	58	(GRF_CLR_BIT(4) \| GRF_CLR_BIT(5) \| GRF_BIT(6))
	59	#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
	60	#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
	61	#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
	62	#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
	63	#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
	64	#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
	65
	66	/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
	67	#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
	68	#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
	69
	70	static int rk3568_set_to_rgmii(struct udevice *dev,
	71	int tx_delay, int rx_delay)
	72	{
	73	struct eth_pdata *pdata = dev_get_plat(dev);
	74	struct rockchip_platform_data *data = pdata->priv_pdata;
	75	u32 con0, con1;
	76
	77	con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
	78	RK3568_GRF_GMAC0_CON0;
	79	con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
	80	RK3568_GRF_GMAC0_CON1;
	81
	82	regmap_write(data->grf, con0,
	83	RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) \|
	84	RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
	85
	86	regmap_write(data->grf, con1,
	87	RK3568_GMAC_PHY_INTF_SEL_RGMII \|
	88	RK3568_GMAC_RXCLK_DLY_ENABLE \|
	89	RK3568_GMAC_TXCLK_DLY_ENABLE);
	90
	91	return 0;
	92	}
	93
	94	static int rk3568_set_to_rmii(struct udevice *dev)
	95	{
	96	struct eth_pdata *pdata = dev_get_plat(dev);
	97	struct rockchip_platform_data *data = pdata->priv_pdata;
	98	u32 con1;
	99
	100	con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
	101	RK3568_GRF_GMAC0_CON1;
	102	regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
	103
	104	return 0;
105	}
106
107	static int rk3568_set_gmac_speed(struct udevice *dev)
108	{
109	struct eqos_priv *eqos = dev_get_priv(dev);
110	ulong rate;
111	int ret;
112
113	switch (eqos->phy->speed) {
114	case SPEED_10:
115	rate = 2500000;
116	break;
117	case SPEED_100:
118	rate = 25000000;
119	break;
120	case SPEED_1000:
121	rate = 125000000;
122	break;
123	default:
124	return -EINVAL;
125	}
126
127	ret = clk_set_rate(&eqos->clk_tx, rate);
128	if (ret < 0)
129	return ret;
130
131	return 0;
132	}
133
01b8ed47 JK	134	/* sys_grf */
	135	#define RK3588_GRF_GMAC_CON7 0x031c
	136	#define RK3588_GRF_GMAC_CON8 0x0320
	137	#define RK3588_GRF_GMAC_CON9 0x0324
	138
	139	#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
	140	#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
	141	#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
	142	#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
	143
	144	#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
	145	#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
	146
	147	/* php_grf */
	148	#define RK3588_GRF_GMAC_CON0 0x0008
	149	#define RK3588_GRF_CLK_CON1 0x0070
	150
	151	#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
	152	(GRF_BIT(3 + (id) * 6) \| GRF_CLR_BIT(4 + (id) * 6) \| GRF_CLR_BIT(5 + (id) * 6))
	153	#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
	154	(GRF_CLR_BIT(3 + (id) * 6) \| GRF_CLR_BIT(4 + (id) * 6) \| GRF_BIT(5 + (id) * 6))
	155
	156	#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
	157	#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
	158
	159	#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4)
	160	#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)
	161
	162	#define RK3588_GMAC_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
	163	#define RK3588_GMAC_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
	164
	165	#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
	166	(GRF_CLR_BIT(5 * (id) + 2) \| GRF_CLR_BIT(5 * (id) + 3))
	167	#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
	168	(GRF_BIT(5 * (id) + 2) \| GRF_BIT(5 * (id) + 3))
	169	#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
	170	(GRF_CLR_BIT(5 * (id) + 2) \| GRF_BIT(5 * (id) + 3))
	171
	172	#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
	173	#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
	174
	175	static int rk3588_set_to_rgmii(struct udevice *dev,
	176	int tx_delay, int rx_delay)
	177	{
	178	struct eth_pdata *pdata = dev_get_plat(dev);
	179	struct rockchip_platform_data *data = pdata->priv_pdata;
	180	u32 offset_con, id = data->id;
	181
	182	offset_con = data->id == 1 ? RK3588_GRF_GMAC_CON9 :
	183	RK3588_GRF_GMAC_CON8;
	184
	185	regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
	186	RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
	187
	188	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
	189	RK3588_GMAC_CLK_RGMII_MODE(id));
	190
	191	regmap_write(data->grf, RK3588_GRF_GMAC_CON7,
	192	RK3588_GMAC_RXCLK_DLY_ENABLE(id) \|
	193	RK3588_GMAC_TXCLK_DLY_ENABLE(id));
	194
	195	regmap_write(data->grf, offset_con,
	196	RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) \|
	197	RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
198
199	return 0;
200	}
201
202	static int rk3588_set_to_rmii(struct udevice *dev)
203	{
204	struct eth_pdata *pdata = dev_get_plat(dev);
205	struct rockchip_platform_data *data = pdata->priv_pdata;
206
207	regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
208	RK3588_GMAC_PHY_INTF_SEL_RMII(data->id));
209
210	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
211	RK3588_GMAC_CLK_RMII_MODE(data->id));
212
213	return 0;
214	}
215
216	static int rk3588_set_gmac_speed(struct udevice *dev)
217	{
218	struct eqos_priv *eqos = dev_get_priv(dev);
219	struct eth_pdata *pdata = dev_get_plat(dev);
220	struct rockchip_platform_data *data = pdata->priv_pdata;
221	u32 val = 0, id = data->id;
222
223	switch (eqos->phy->speed) {
224	case SPEED_10:
225	if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
226	val = RK3588_GMAC_CLK_RMII_DIV20(id);
227	else
228	val = RK3588_GMAC_CLK_RGMII_DIV50(id);
229	break;
230	case SPEED_100:
231	if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
232	val = RK3588_GMAC_CLK_RMII_DIV2(id);
233	else
234	val = RK3588_GMAC_CLK_RGMII_DIV5(id);
235	break;
236	case SPEED_1000:
237	if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
238	val = RK3588_GMAC_CLK_RGMII_DIV1(id);
239	else
240	return -EINVAL;
241	break;
242	default:
243	return -EINVAL;
244	}
245
246	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
247
248	return 0;
249	}
250
251	static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
252	{
253	struct eth_pdata *pdata = dev_get_plat(dev);
254	struct rockchip_platform_data *data = pdata->priv_pdata;
255
256	u32 val = data->clock_input ? RK3588_GMAC_CLK_SELET_IO(data->id) :
257	RK3588_GMAC_CLK_SELET_CRU(data->id);
258
259	val \|= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :
260	RK3588_GMAC_CLK_RMII_GATE(data->id);
261
262	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
263	}
264
8e76ff61 JK	265	static const struct rk_gmac_ops rk_gmac_ops[] = {
	266	{
	267	.compatible = "rockchip,rk3568-gmac",
	268	.set_to_rgmii = rk3568_set_to_rgmii,
	269	.set_to_rmii = rk3568_set_to_rmii,
	270	.set_gmac_speed = rk3568_set_gmac_speed,
	271	.regs = {
	272	0xfe2a0000, /* gmac0 */
	273	0xfe010000, /* gmac1 */
	274	0x0, /* sentinel */
	275	},
	276	},
01b8ed47 JK	277	{
	278	.compatible = "rockchip,rk3588-gmac",
	279	.set_to_rgmii = rk3588_set_to_rgmii,
	280	.set_to_rmii = rk3588_set_to_rmii,
	281	.set_gmac_speed = rk3588_set_gmac_speed,
	282	.set_clock_selection = rk3588_set_clock_selection,
	283	.regs = {
	284	0xfe1b0000, /* gmac0 */
	285	0xfe1c0000, /* gmac1 */
	286	0x0, /* sentinel */
	287	},
	288	},
8e76ff61 JK	289	{ }
	290	};
	291
	292	static const struct rk_gmac_ops get_rk_gmac_ops(struct udevice dev)
	293	{
	294	const struct rk_gmac_ops *ops = rk_gmac_ops;
	295
	296	while (ops->compatible) {
	297	if (device_is_compatible(dev, ops->compatible))
	298	return ops;
	299	ops++;
	300	}
	301
	302	return NULL;
	303	}
	304
	305	static int eqos_probe_resources_rk(struct udevice *dev)
	306	{
	307	struct eqos_priv *eqos = dev_get_priv(dev);
	308	struct eth_pdata *pdata = dev_get_plat(dev);
	309	struct rockchip_platform_data *data;
01b8ed47	310	const char *clock_in_out;
8e76ff61 JK	311	int reset_flags = GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE;
	312	int ret;
	313
beabef65 PO	314	ret = eqos_get_base_addr_dt(dev);
	315	if (ret) {
	316	dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret);
	317	return ret;
	318	}
	319
8e76ff61 JK	320	data = calloc(1, sizeof(struct rockchip_platform_data));
	321	if (!data)
	322	return -ENOMEM;
	323
	324	data->ops = get_rk_gmac_ops(dev);
	325	if (!data->ops) {
	326	ret = -EINVAL;
	327	goto err_free;
	328	}
	329
	330	for (int i = 0; data->ops->regs[i]; i++) {
	331	if (data->ops->regs[i] == (u32)eqos->regs) {
	332	data->id = i;
	333	break;
	334	}
	335	}
	336
	337	pdata->priv_pdata = data;
	338	pdata->phy_interface = eqos->config->interface(dev);
	339	pdata->max_speed = eqos->max_speed;
	340
	341	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
	342	pr_err("Invalid PHY interface\n");
	343	ret = -EINVAL;
	344	goto err_free;
	345	}
	346
	347	data->grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
	348	if (IS_ERR(data->grf)) {
	349	dev_err(dev, "Missing rockchip,grf property\n");
	350	ret = -EINVAL;
	351	goto err_free;
	352	}
	353
01b8ed47 JK	354	if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
	355	data->php_grf =
	356	syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
	357	if (IS_ERR(data->php_grf)) {
	358	dev_err(dev, "Missing rockchip,php-grf property\n");
	359	ret = -EINVAL;
	360	goto err_free;
	361	}
	362	}
	363
8e76ff61 JK	364	ret = reset_get_bulk(dev, &data->resets);
	365	if (ret < 0)
	366	goto err_free;
	367
	368	reset_assert_bulk(&data->resets);
	369
	370	ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
	371	if (ret) {
	372	dev_dbg(dev, "clk_get_by_name(stmmaceth) failed: %d", ret);
	373	goto err_release_resets;
	374	}
	375
01b8ed47 JK	376	if (device_is_compatible(dev, "rockchip,rk3568-gmac")) {
	377	ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
	378	if (ret) {
	379	dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
c9309f40	380	goto err_release_resets;
01b8ed47	381	}
8e76ff61 JK	382	}
8e76ff61 JK	383
01b8ed47 JK	384	clock_in_out = dev_read_string(dev, "clock_in_out");
	385	if (clock_in_out && !strcmp(clock_in_out, "input"))
	386	data->clock_input = true;
	387	else
	388	data->clock_input = false;
	389
8e76ff61 JK	390	/* snps,reset props are deprecated, do bare minimum to support them */
	391	if (dev_read_bool(dev, "snps,reset-active-low"))
	392	reset_flags \|= GPIOD_ACTIVE_LOW;
	393
	394	dev_read_u32_array(dev, "snps,reset-delays-us", eqos->reset_delays, 3);
	395
	396	gpio_request_by_name(dev, "snps,reset-gpio", 0,
	397	&eqos->phy_reset_gpio, reset_flags);
	398
	399	return 0;
	400
8e76ff61 JK	401	err_release_resets:
	402	reset_release_bulk(&data->resets);
	403	err_free:
	404	free(data);
	405
	406	return ret;
	407	}
	408
	409	static int eqos_remove_resources_rk(struct udevice *dev)
	410	{
	411	struct eqos_priv *eqos = dev_get_priv(dev);
	412	struct eth_pdata *pdata = dev_get_plat(dev);
	413	struct rockchip_platform_data *data = pdata->priv_pdata;
	414
	415	if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
	416	dm_gpio_free(dev, &eqos->phy_reset_gpio);
	417
8e76ff61 JK	418	reset_release_bulk(&data->resets);
	419	free(data);
	420
	421	return 0;
	422	}
	423
	424	static int eqos_stop_resets_rk(struct udevice *dev)
	425	{
	426	struct eth_pdata *pdata = dev_get_plat(dev);
	427	struct rockchip_platform_data *data = pdata->priv_pdata;
	428
	429	return reset_assert_bulk(&data->resets);
	430	}
	431
	432	static int eqos_start_resets_rk(struct udevice *dev)
	433	{
	434	struct eth_pdata *pdata = dev_get_plat(dev);
	435	struct rockchip_platform_data *data = pdata->priv_pdata;
	436
	437	return reset_deassert_bulk(&data->resets);
	438	}
	439
	440	static int eqos_stop_clks_rk(struct udevice *dev)
	441	{
01b8ed47 JK	442	struct eth_pdata *pdata = dev_get_plat(dev);
	443	struct rockchip_platform_data *data = pdata->priv_pdata;
	444
	445	if (data->ops->set_clock_selection)
	446	data->ops->set_clock_selection(dev, false);
	447
8e76ff61 JK	448	return 0;
	449	}
	450
	451	static int eqos_start_clks_rk(struct udevice *dev)
	452	{
	453	struct eqos_priv *eqos = dev_get_priv(dev);
	454	struct eth_pdata *pdata = dev_get_plat(dev);
	455	struct rockchip_platform_data *data = pdata->priv_pdata;
	456	int tx_delay, rx_delay, ret;
	457
	458	if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
	459	udelay(eqos->reset_delays[1]);
	460
	461	ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
	462	if (ret < 0)
	463	return ret;
	464
	465	udelay(eqos->reset_delays[2]);
	466	}
	467
01b8ed47 JK	468	if (data->ops->set_clock_selection)
	469	data->ops->set_clock_selection(dev, true);
	470
8e76ff61 JK	471	tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
	472	rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);
	473
	474	switch (pdata->phy_interface) {
	475	case PHY_INTERFACE_MODE_RGMII:
	476	return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
	477	case PHY_INTERFACE_MODE_RGMII_ID:
	478	return data->ops->set_to_rgmii(dev, 0, 0);
	479	case PHY_INTERFACE_MODE_RGMII_RXID:
	480	return data->ops->set_to_rgmii(dev, tx_delay, 0);
	481	case PHY_INTERFACE_MODE_RGMII_TXID:
	482	return data->ops->set_to_rgmii(dev, 0, rx_delay);
	483	case PHY_INTERFACE_MODE_RMII:
	484	return data->ops->set_to_rmii(dev);
	485	}
	486
	487	return -EINVAL;
	488	}
	489
	490	static int eqos_set_tx_clk_speed_rk(struct udevice *dev)
	491	{
	492	struct eth_pdata *pdata = dev_get_plat(dev);
	493	struct rockchip_platform_data *data = pdata->priv_pdata;
	494
	495	return data->ops->set_gmac_speed(dev);
	496	}
	497
	498	static ulong eqos_get_tick_clk_rate_rk(struct udevice *dev)
	499	{
	500	struct eqos_priv *eqos = dev_get_priv(dev);
	501
	502	return clk_get_rate(&eqos->clk_master_bus);
	503	}
	504
	505	static struct eqos_ops eqos_rockchip_ops = {
	506	.eqos_inval_desc = eqos_inval_desc_generic,
	507	.eqos_flush_desc = eqos_flush_desc_generic,
	508	.eqos_inval_buffer = eqos_inval_buffer_generic,
	509	.eqos_flush_buffer = eqos_flush_buffer_generic,
	510	.eqos_probe_resources = eqos_probe_resources_rk,
	511	.eqos_remove_resources = eqos_remove_resources_rk,
	512	.eqos_stop_resets = eqos_stop_resets_rk,
	513	.eqos_start_resets = eqos_start_resets_rk,
	514	.eqos_stop_clks = eqos_stop_clks_rk,
	515	.eqos_start_clks = eqos_start_clks_rk,
	516	.eqos_calibrate_pads = eqos_null_ops,
	517	.eqos_disable_calibration = eqos_null_ops,
	518	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_rk,
	519	.eqos_get_enetaddr = eqos_null_ops,
	520	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_rk,
	521	};
	522
	523	struct eqos_config eqos_rockchip_config = {
	524	.reg_access_always_ok = false,
	525	.mdio_wait = 10,
	526	.swr_wait = 50,
	527	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
	528	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
	529	.axi_bus_width = EQOS_AXI_WIDTH_64,
	530	.interface = dev_read_phy_mode,
	531	.ops = &eqos_rockchip_ops,
	532	};