projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6ded73aa MS |
1 | menu "FPGA support" |
| 2 | ||
| 6b245014 SDPP |
3 | config FPGA |
| 4 | bool | |
| 5 | ||
| 98d62e61 PB |
6 | config FPGA_ALTERA |
| 7 | bool "Enable Altera FPGA drivers" | |
| 8 | select FPGA | |
| 9 | help | |
| 10 | Say Y here to enable the Altera FPGA driver | |
| 11 | ||
| 12 | This provides basic infrastructure to support Altera FPGA devices. | |
| 13 | Enable Altera FPGA specific functions which includes bitstream | |
| 14 | (in BIT format), fpga and device validation. | |
| 15 | ||
| fa23ba1a TFC |
16 | config FPGA_SOCFPGA |
| 17 | bool "Enable Gen5 and Arria10 common FPGA drivers" | |
| 18 | select FPGA_ALTERA | |
| 19 | help | |
| 20 | Say Y here to enable the Gen5 and Arria10 common FPGA driver | |
| 21 | ||
| 22 | This provides common functionality for Gen5 and Arria10 devices. | |
| 23 | ||
| 6e52cb25 TR |
24 | config FPGA_STRATIX_V |
| 25 | bool "Enable Stratix V FPGA drivers" | |
| 26 | depends on FPGA_ALTERA | |
| 27 | help | |
| 28 | Say Y here to enable the Altera Stratix V FPGA specific driver. | |
| 29 | ||
| 98d62e61 PB |
30 | config FPGA_CYCLON2 |
| 31 | bool "Enable Altera FPGA driver for Cyclone II" | |
| 32 | depends on FPGA_ALTERA | |
| 33 | help | |
| 34 | Say Y here to enable the Altera Cyclone II FPGA specific driver | |
| 35 | ||
| 36 | This provides common functionality for Altera Cyclone II devices. | |
| 37 | Enable FPGA driver for loading bitstream in BIT and BIN format | |
| 38 | on Altera Cyclone II device. | |
| 39 | ||
| d2170168 CHA |
40 | config FPGA_INTEL_SDM_MAILBOX |
| 41 | bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" | |
| 9a5bbdfd | 42 | depends on TARGET_SOCFPGA_SOC64 |
| c41e660b ACH |
43 | select FPGA_ALTERA |
| 44 | help | |
| d2170168 | 45 | Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver |
| c41e660b | 46 | |
| d2170168 CHA |
47 | This provides common functionality for Intel FPGA devices. |
| 48 | Enable FPGA driver for writing full bitstream into Intel FPGA | |
| 49 | devices through SDM (Secure Device Manager) Mailbox. | |
| c41e660b | 50 | |
| 6b245014 SDPP |
51 | config FPGA_XILINX |
| 52 | bool "Enable Xilinx FPGA drivers" | |
| 53 | select FPGA | |
| 54 | help | |
| 55 | Enable Xilinx FPGA specific functions which includes bitstream | |
| 56 | (in BIT format), fpga and device validation. | |
| 57 | ||
| 58 | config FPGA_ZYNQMPPL | |
| 59 | bool "Enable Xilinx FPGA driver for ZynqMP" | |
| 60 | depends on FPGA_XILINX | |
| 61 | help | |
| 62 | Enable FPGA driver for loading bitstream in BIT and BIN format | |
| 63 | on Xilinx Zynq UltraScale+ (ZynqMP) device. | |
| 64 | ||
| 26e054c9 SDPP |
65 | config FPGA_VERSALPL |
| 66 | bool "Enable Xilinx FPGA driver for Versal" | |
| 67 | depends on FPGA_XILINX | |
| 68 | help | |
| 69 | Enable FPGA driver for loading bitstream in PDI format on Xilinx | |
| 70 | Versal device. PDI is a new programmable device image format for | |
| 71 | Versal. The bitstream will only be generated as PDI for Versal | |
| 72 | platform. | |
| 73 | ||
| f4158346 | 74 | config FPGA_SPARTAN3 |
| a225f810 | 75 | bool "Enable Spartan3 FPGA driver" |
| 25d63a36 | 76 | depends on FPGA_XILINX |
| a225f810 MS |
77 | help |
| 78 | Enable Spartan3 FPGA driver for loading in BIT format. | |
| f4158346 | 79 | |
| 25d63a36 RH |
80 | config FPGA_VIRTEX2 |
| 81 | bool "Enable Xilinx Virtex-II and later FPGA driver" | |
| 82 | depends on FPGA_XILINX | |
| 83 | help | |
| 84 | Enable Virtex-II FPGA driver for loading in BIT format. This driver | |
| 85 | also supports many newer Xilinx FPGA families. | |
| 86 | ||
| 3990c9d6 | 87 | config FPGA_ZYNQPL |
| a225f810 MS |
88 | bool "Enable Xilinx FPGA for Zynq" |
| 89 | depends on ARCH_ZYNQ | |
| 90 | help | |
| 91 | Enable FPGA driver for loading bitstream in BIT and BIN format | |
| 92 | on Xilinx Zynq devices. | |
| 3990c9d6 | 93 | |
| e8ffc1df AD |
94 | config SYS_FPGA_CHECK_CTRLC |
| 95 | bool "Allow Control-C to interrupt FPGA configuration" | |
| 96 | depends on FPGA | |
| 97 | help | |
| 98 | User can interrupt FPGA configuration by pressing CTRL+C. | |
| 99 | ||
| 8c09cb6f AD |
100 | config SYS_FPGA_PROG_FEEDBACK |
| 101 | bool "Progress output during FPGA configuration" | |
| 102 | depends on FPGA | |
| 103 | default y if FPGA_VIRTEX2 | |
| 104 | help | |
| 105 | Enable printing of hash marks during FPGA configuration. | |
| 106 | ||
| fb2b8856 OS |
107 | config FPGA_LOAD_SECURE |
| 108 | bool "Enable loading secure bitstreams" | |
| 109 | depends on FPGA | |
| 110 | help | |
| 111 | Enables the fpga loads() functions that are used to load secure | |
| 112 | (authenticated or encrypted or both) bitstreams on to FPGA. | |
| 113 | ||
| 114 | config SPL_FPGA_LOAD_SECURE | |
| 115 | bool "Enable loading secure bitstreams for SPL" | |
| 116 | depends on SPL_FPGA | |
| 117 | help | |
| 118 | Enables the fpga loads() functions that are used to load secure | |
| 119 | (authenticated or encrypted or both) bitstreams on to FPGA. | |
| 120 | ||
| 1323d08b AD |
121 | config DM_FPGA |
| 122 | bool "Enable Driver Model for FPGA drivers" | |
| 123 | depends on DM | |
| 124 | select FPGA | |
| 125 | help | |
| 126 | Enable driver model for Field-Programmable Gate Array (FPGA) devices. | |
| 127 | The devices cover a wide range of applications and are configured at | |
| 128 | runtime by loading a bitstream into the FPGA device. | |
| 129 | Loading a bitstream from any kind of storage is the main task of the | |
| 130 | FPGA drivers. | |
| 131 | For now this uclass has no methods yet. | |
| 132 | ||
| 133 | config SANDBOX_FPGA | |
| 134 | bool "Enable sandbox FPGA driver" | |
| 135 | depends on SANDBOX && DM_FPGA | |
| 136 | help | |
| 137 | This is a driver model based FPGA driver for sandbox. | |
| 138 | Currently it is a stub only, as there are no usable uclass methods yet. | |
| 139 | ||
| 6ded73aa | 140 | endmenu |