[J-u-boot.git] / drivers / video / tegra.c

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fdtdec.h>
#include <lcd.h>

#include <asm/system.h>
#include <asm/gpio.h>

#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/pwm.h>
#include <asm/arch/display.h>
#include <asm/arch-tegra/timer.h>

DECLARE_GLOBAL_DATA_PTR;

/* These are the stages we go throuh in enabling the LCD */
enum stage_t {
	STAGE_START,
	STAGE_PANEL_VDD,
	STAGE_LVDS,
	STAGE_BACKLIGHT_VDD,
	STAGE_PWM,
	STAGE_BACKLIGHT_EN,
	STAGE_DONE,
};

static enum stage_t stage;	/* Current stage we are at */
static unsigned long timer_next; /* Time we can move onto next stage */

/* Our LCD config, set up in handle_stage() */
static struct fdt_panel_config config;
struct fdt_disp_config *disp_config;	/* Display controller config */

enum {
	/* Maximum LCD size we support */
	LCD_MAX_WIDTH		= 1366,
	LCD_MAX_HEIGHT		= 768,
	LCD_MAX_LOG2_BPP	= 4,		/* 2^4 = 16 bpp */
};

vidinfo_t panel_info = {
	/* Insert a value here so that we don't end up in the BSS */
	.vl_col = -1,
};

#if !CONFIG_IS_ENABLED(OF_CONTROL)
#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support"
#endif

static void update_panel_size(struct fdt_disp_config *config)
{
	panel_info.vl_col = config->width;
	panel_info.vl_row = config->height;
	panel_info.vl_bpix = config->log2_bpp;
}

/*
 *  Main init function called by lcd driver.
 *  Inits and then prints test pattern if required.
 */

void lcd_ctrl_init(void *lcdbase)
{
	int type = DCACHE_OFF;
	int size;

	assert(disp_config);

	/* Make sure that we can acommodate the selected LCD */
	assert(disp_config->width <= LCD_MAX_WIDTH);
	assert(disp_config->height <= LCD_MAX_HEIGHT);
	assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP);
	if (disp_config->width <= LCD_MAX_WIDTH
			&& disp_config->height <= LCD_MAX_HEIGHT
			&& disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
		update_panel_size(disp_config);
	size = lcd_get_size(&lcd_line_length);

	/* Set up the LCD caching as requested */
	if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
		type = DCACHE_WRITETHROUGH;
	else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK)
		type = DCACHE_WRITEBACK;
	mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type);

	/* Enable flushing after LCD writes if requested */
	lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);

	debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer);
}

ulong calc_fbsize(void)
{
	return (panel_info.vl_col * panel_info.vl_row *
		NBITS(panel_info.vl_bpix)) / 8;
}

void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
{
}

void tegra_lcd_early_init(const void *blob)
{
	/*
	 * Go with the maximum size for now. We will fix this up after
	 * relocation. These values are only used for memory alocation.
	 */
	panel_info.vl_col = LCD_MAX_WIDTH;
	panel_info.vl_row = LCD_MAX_HEIGHT;
	panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
}

/**
 * Decode the panel information from the fdt.
 *
 * @param blob		fdt blob
 * @param config	structure to store fdt config into
 * @return 0 if ok, -ve on error
 */
static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config)
{
	int display_node;

	disp_config = tegra_display_get_config();
	if (!disp_config) {
		debug("%s: Display controller is not configured\n", __func__);
		return -1;
	}
	display_node = disp_config->panel_node;
	if (display_node < 0) {
		debug("%s: No panel configuration available\n", __func__);
		return -1;
	}

	config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm");
	if (config->pwm_channel < 0) {
		debug("%s: Unable to request PWM channel\n", __func__);
		return -1;
	}

	config->cache_type = fdtdec_get_int(blob, display_node,
					    "nvidia,cache-type",
					    FDT_LCD_CACHE_WRITE_BACK_FLUSH);

	/* These GPIOs are all optional */
	gpio_request_by_name_nodev(blob, display_node,
				   "nvidia,backlight-enable-gpios", 0,
				   &config->backlight_en, GPIOD_IS_OUT);
	gpio_request_by_name_nodev(blob, display_node,
				   "nvidia,lvds-shutdown-gpios", 0,
				   &config->lvds_shutdown, GPIOD_IS_OUT);
	gpio_request_by_name_nodev(blob, display_node,
				   "nvidia,backlight-vdd-gpios", 0,
				   &config->backlight_vdd, GPIOD_IS_OUT);
	gpio_request_by_name_nodev(blob, display_node,
				   "nvidia,panel-vdd-gpios", 0,
				   &config->panel_vdd, GPIOD_IS_OUT);

	return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings",
			config->panel_timings, FDT_LCD_TIMINGS);
}

/**
 * Handle the next stage of device init
 */
static int handle_stage(const void *blob)
{
	debug("%s: stage %d\n", __func__, stage);

	/* do the things for this stage */
	switch (stage) {
	case STAGE_START:
		/* Initialize the Tegra display controller */
		if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) {
			printf("%s: Failed to probe display driver\n",
			__func__);
			return -1;
		}

		/* get panel details */
		if (fdt_decode_lcd(blob, &config)) {
			printf("No valid LCD information in device tree\n");
			return -1;
		}

		/*
		 * It is possible that the FDT has requested that the LCD be
		 * disabled. We currently don't support this. It would require
		 * changes to U-Boot LCD subsystem to have LCD support
		 * compiled in but not used. An easier option might be to
		 * still have a frame buffer, but leave the backlight off and
		 * remove all mention of lcd in the stdout environment
		 * variable.
		 */

		funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
		break;
	case STAGE_PANEL_VDD:
		if (dm_gpio_is_valid(&config.panel_vdd))
			dm_gpio_set_value(&config.panel_vdd, 1);
		break;
	case STAGE_LVDS:
		if (dm_gpio_is_valid(&config.lvds_shutdown))
			dm_gpio_set_value(&config.lvds_shutdown, 1);
		break;
	case STAGE_BACKLIGHT_VDD:
		if (dm_gpio_is_valid(&config.backlight_vdd))
			dm_gpio_set_value(&config.backlight_vdd, 1);
		break;
	case STAGE_PWM:
		/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
		pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
		pinmux_tristate_disable(PMUX_PINGRP_GPU);

		pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
		break;
	case STAGE_BACKLIGHT_EN:
		if (dm_gpio_is_valid(&config.backlight_en))
			dm_gpio_set_value(&config.backlight_en, 1);
		break;
	case STAGE_DONE:
		break;
	}

	/* set up timer for next stage */
	timer_next = timer_get_us();
	if (stage < FDT_LCD_TIMINGS)
		timer_next += config.panel_timings[stage] * 1000;

	/* move to next stage */
	stage++;
	return 0;
}

int tegra_lcd_check_next_stage(const void *blob, int wait)
{
	if (stage == STAGE_DONE)
		return 0;

	do {
		/* wait if we need to */
		debug("%s: stage %d\n", __func__, stage);
		if (stage != STAGE_START) {
			int delay = timer_next - timer_get_us();

			if (delay > 0) {
				if (wait)
					udelay(delay);
				else
					return 0;
			}
		}

		if (handle_stage(blob))
			return -1;
	} while (wait && stage != STAGE_DONE);
	if (stage == STAGE_DONE)
		debug("%s: LCD init complete\n", __func__);

	return 0;
}

void lcd_enable(void)
{
	/*
	 * Backlight and power init will be done separately in
	 * tegra_lcd_check_next_stage(), which should be called in
	 * board_late_init().
	 *
	 * U-Boot code supports only colour depth, selected at compile time.
	 * The device tree setting should match this. Otherwise the display
	 * will not look right, and U-Boot may crash.
	 */
	if (disp_config->log2_bpp != LCD_BPP) {
		printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)"
			" must match setting of LCD_BPP (%d)\n", __func__,
		       disp_config->log2_bpp, disp_config->bpp, LCD_BPP);
	}
}
Commit	Line	Data
0be8f203 SG	1	/*
0be8f203 SG	2	* Copyright (c) 2011 The Chromium OS Authors.
1a459660	3	* SPDX-License-Identifier: GPL-2.0+
0be8f203 SG	4	*/
	5
	6	#include <common.h>
	7	#include <fdtdec.h>
	8	#include <lcd.h>
	9
	10	#include <asm/system.h>
	11	#include <asm/gpio.h>
	12
	13	#include <asm/arch/clock.h>
	14	#include <asm/arch/funcmux.h>
	15	#include <asm/arch/pinmux.h>
	16	#include <asm/arch/pwm.h>
	17	#include <asm/arch/display.h>
	18	#include <asm/arch-tegra/timer.h>
	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	/* These are the stages we go throuh in enabling the LCD */
	23	enum stage_t {
	24	STAGE_START,
	25	STAGE_PANEL_VDD,
	26	STAGE_LVDS,
	27	STAGE_BACKLIGHT_VDD,
	28	STAGE_PWM,
	29	STAGE_BACKLIGHT_EN,
	30	STAGE_DONE,
	31	};
	32
	33	static enum stage_t stage; /* Current stage we are at */
	34	static unsigned long timer_next; /* Time we can move onto next stage */
	35
	36	/* Our LCD config, set up in handle_stage() */
	37	static struct fdt_panel_config config;
	38	struct fdt_disp_config disp_config; / Display controller config */
	39
	40	enum {
	41	/* Maximum LCD size we support */
	42	LCD_MAX_WIDTH = 1366,
	43	LCD_MAX_HEIGHT = 768,
	44	LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
	45	};
	46
0be8f203 SG	47	vidinfo_t panel_info = {
	48	/* Insert a value here so that we don't end up in the BSS */
	49	.vl_col = -1,
	50	};
	51
0f925822	52	#if !CONFIG_IS_ENABLED(OF_CONTROL)
0be8f203 SG	53	#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support"
	54	#endif
	55
0be8f203 SG	56	static void update_panel_size(struct fdt_disp_config *config)
	57	{
	58	panel_info.vl_col = config->width;
	59	panel_info.vl_row = config->height;
	60	panel_info.vl_bpix = config->log2_bpp;
	61	}
	62
	63	/*
	64	* Main init function called by lcd driver.
	65	* Inits and then prints test pattern if required.
	66	*/
	67
	68	void lcd_ctrl_init(void *lcdbase)
	69	{
44706a87	70	int type = DCACHE_OFF;
0c558754	71	int size;
0be8f203 SG	72
	73	assert(disp_config);
	74
0be8f203 SG	75	/* Make sure that we can acommodate the selected LCD */
	76	assert(disp_config->width <= LCD_MAX_WIDTH);
	77	assert(disp_config->height <= LCD_MAX_HEIGHT);
	78	assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP);
	79	if (disp_config->width <= LCD_MAX_WIDTH
	80	&& disp_config->height <= LCD_MAX_HEIGHT
	81	&& disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
	82	update_panel_size(disp_config);
0c558754	83	size = lcd_get_size(&lcd_line_length);
0be8f203	84
44706a87 SG	85	/* Set up the LCD caching as requested */
	86	if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
	87	type = DCACHE_WRITETHROUGH;
	88	else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK)
	89	type = DCACHE_WRITEBACK;
	90	mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type);
	91
	92	/* Enable flushing after LCD writes if requested */
	93	lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
	94
fdb9f349	95	debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer);
0be8f203 SG	96	}
	97
	98	ulong calc_fbsize(void)
	99	{
	100	return (panel_info.vl_col * panel_info.vl_row *
	101	NBITS(panel_info.vl_bpix)) / 8;
	102	}
	103
	104	void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
	105	{
	106	}
	107
	108	void tegra_lcd_early_init(const void *blob)
	109	{
	110	/*
	111	* Go with the maximum size for now. We will fix this up after
	112	* relocation. These values are only used for memory alocation.
	113	*/
	114	panel_info.vl_col = LCD_MAX_WIDTH;
	115	panel_info.vl_row = LCD_MAX_HEIGHT;
	116	panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
	117	}
	118
	119	/**
	120	* Decode the panel information from the fdt.
	121	*
	122	* @param blob fdt blob
	123	* @param config structure to store fdt config into
	124	* @return 0 if ok, -ve on error
	125	*/
	126	static int fdt_decode_lcd(const void blob, struct fdt_panel_config config)
	127	{
	128	int display_node;
	129
	130	disp_config = tegra_display_get_config();
	131	if (!disp_config) {
	132	debug("%s: Display controller is not configured\n", __func__);
	133	return -1;
	134	}
	135	display_node = disp_config->panel_node;
	136	if (display_node < 0) {
	137	debug("%s: No panel configuration available\n", __func__);
	138	return -1;
	139	}
	140
	141	config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm");
	142	if (config->pwm_channel < 0) {
	143	debug("%s: Unable to request PWM channel\n", __func__);
	144	return -1;
	145	}
	146
	147	config->cache_type = fdtdec_get_int(blob, display_node,
	148	"nvidia,cache-type",
	149	FDT_LCD_CACHE_WRITE_BACK_FLUSH);
	150
	151	/* These GPIOs are all optional */
04072cba SG	152	gpio_request_by_name_nodev(blob, display_node,
	153	"nvidia,backlight-enable-gpios", 0,
	154	&config->backlight_en, GPIOD_IS_OUT);
	155	gpio_request_by_name_nodev(blob, display_node,
	156	"nvidia,lvds-shutdown-gpios", 0,
	157	&config->lvds_shutdown, GPIOD_IS_OUT);
	158	gpio_request_by_name_nodev(blob, display_node,
	159	"nvidia,backlight-vdd-gpios", 0,
	160	&config->backlight_vdd, GPIOD_IS_OUT);
	161	gpio_request_by_name_nodev(blob, display_node,
	162	"nvidia,panel-vdd-gpios", 0,
	163	&config->panel_vdd, GPIOD_IS_OUT);
0be8f203 SG	164
	165	return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings",
	166	config->panel_timings, FDT_LCD_TIMINGS);
	167	}
	168
	169	/**
	170	* Handle the next stage of device init
	171	*/
	172	static int handle_stage(const void *blob)
	173	{
	174	debug("%s: stage %d\n", __func__, stage);
	175
	176	/* do the things for this stage */
	177	switch (stage) {
	178	case STAGE_START:
	179	/* Initialize the Tegra display controller */
	180	if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) {
	181	printf("%s: Failed to probe display driver\n",
	182	__func__);
	183	return -1;
	184	}
	185
	186	/* get panel details */
	187	if (fdt_decode_lcd(blob, &config)) {
	188	printf("No valid LCD information in device tree\n");
	189	return -1;
	190	}
	191
	192	/*
	193	* It is possible that the FDT has requested that the LCD be
	194	* disabled. We currently don't support this. It would require
	195	* changes to U-Boot LCD subsystem to have LCD support
	196	* compiled in but not used. An easier option might be to
	197	* still have a frame buffer, but leave the backlight off and
	198	* remove all mention of lcd in the stdout environment
	199	* variable.
	200	*/
	201
	202	funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
0be8f203 SG	203	break;
0be8f203 SG	204	case STAGE_PANEL_VDD:
04072cba SG	205	if (dm_gpio_is_valid(&config.panel_vdd))
04072cba SG	206	dm_gpio_set_value(&config.panel_vdd, 1);
0be8f203 SG	207	break;
0be8f203 SG	208	case STAGE_LVDS:
04072cba SG	209	if (dm_gpio_is_valid(&config.lvds_shutdown))
04072cba SG	210	dm_gpio_set_value(&config.lvds_shutdown, 1);
0be8f203 SG	211	break;
0be8f203 SG	212	case STAGE_BACKLIGHT_VDD:
04072cba SG	213	if (dm_gpio_is_valid(&config.backlight_vdd))
04072cba SG	214	dm_gpio_set_value(&config.backlight_vdd, 1);
0be8f203 SG	215	break;
	216	case STAGE_PWM:
	217	/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
70ad375e SW	218	pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
70ad375e SW	219	pinmux_tristate_disable(PMUX_PINGRP_GPU);
0be8f203 SG	220
	221	pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
	222	break;
	223	case STAGE_BACKLIGHT_EN:
04072cba SG	224	if (dm_gpio_is_valid(&config.backlight_en))
04072cba SG	225	dm_gpio_set_value(&config.backlight_en, 1);
0be8f203 SG	226	break;
	227	case STAGE_DONE:
	228	break;
	229	}
	230
	231	/* set up timer for next stage */
	232	timer_next = timer_get_us();
	233	if (stage < FDT_LCD_TIMINGS)
	234	timer_next += config.panel_timings[stage] * 1000;
	235
	236	/* move to next stage */
	237	stage++;
	238	return 0;
	239	}
	240
	241	int tegra_lcd_check_next_stage(const void *blob, int wait)
	242	{
	243	if (stage == STAGE_DONE)
	244	return 0;
	245
	246	do {
	247	/* wait if we need to */
	248	debug("%s: stage %d\n", __func__, stage);
	249	if (stage != STAGE_START) {
	250	int delay = timer_next - timer_get_us();
	251
	252	if (delay > 0) {
	253	if (wait)
	254	udelay(delay);
	255	else
	256	return 0;
	257	}
	258	}
	259
	260	if (handle_stage(blob))
	261	return -1;
	262	} while (wait && stage != STAGE_DONE);
	263	if (stage == STAGE_DONE)
	264	debug("%s: LCD init complete\n", __func__);
	265
	266	return 0;
	267	}
	268
	269	void lcd_enable(void)
	270	{
	271	/*
	272	* Backlight and power init will be done separately in
	273	* tegra_lcd_check_next_stage(), which should be called in
	274	* board_late_init().
	275	*
	276	* U-Boot code supports only colour depth, selected at compile time.
	277	* The device tree setting should match this. Otherwise the display
	278	* will not look right, and U-Boot may crash.
	279	*/
	280	if (disp_config->log2_bpp != LCD_BPP) {
	281	printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)"
	282	" must match setting of LCD_BPP (%d)\n", __func__,
	283	disp_config->log2_bpp, disp_config->bpp, LCD_BPP);
	284	}
	285	}