[J-u-boot.git] / drivers / video / mxsfb.c

/*
 * Freescale i.MX23/i.MX28 LCDIF driver
 *
 * Copyright (C) 2011-2013 Marek Vasut <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <malloc.h>
#include <video_fb.h>

#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/errno.h>
#include <asm/io.h>

#include <asm/imx-common/dma.h>

#include "videomodes.h"

#define	PS2KHZ(ps)	(1000000000UL / (ps))

static GraphicDevice panel;
struct mxs_dma_desc desc;

/**
 * mxsfb_system_setup() - Fine-tune LCDIF configuration
 *
 * This function is used to adjust the LCDIF configuration. This is usually
 * needed when driving the controller in System-Mode to operate an 8080 or
 * 6800 connected SmartLCD.
 */
__weak void mxsfb_system_setup(void)
{
}

/*
 * DENX M28EVK:
 * setenv videomode
 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
 *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
 *
 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
 * setenv videomode
 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
 * 	 le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
 */

static void mxs_lcd_init(GraphicDevice *panel,
			struct ctfb_res_modes *mode, int bpp)
{
	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
	uint32_t word_len = 0, bus_width = 0;
	uint8_t valid_data = 0;

	/* Kick in the LCDIF clock */
	mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));

	/* Restart the LCDIF block */
	mxs_reset_block(&regs->hw_lcdif_ctrl_reg);

	switch (bpp) {
	case 24:
		word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
		valid_data = 0x7;
		break;
	case 18:
		word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
		valid_data = 0x7;
		break;
	case 16:
		word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
		valid_data = 0xf;
		break;
	case 8:
		word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
		valid_data = 0xf;
		break;
	}

	writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
		LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
		&regs->hw_lcdif_ctrl);

	writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
		&regs->hw_lcdif_ctrl1);

	mxsfb_system_setup();

	writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
		&regs->hw_lcdif_transfer_count);

	writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
		LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
		LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
		mode->vsync_len, &regs->hw_lcdif_vdctrl0);
	writel(mode->upper_margin + mode->lower_margin +
		mode->vsync_len + mode->yres,
		&regs->hw_lcdif_vdctrl1);
	writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
		(mode->left_margin + mode->right_margin +
		mode->hsync_len + mode->xres),
		&regs->hw_lcdif_vdctrl2);
	writel(((mode->left_margin + mode->hsync_len) <<
		LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
		(mode->upper_margin + mode->vsync_len),
		&regs->hw_lcdif_vdctrl3);
	writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
		&regs->hw_lcdif_vdctrl4);

	writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
	writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);

	/* Flush FIFO first */
	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);

#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
	/* Sync signals ON */
	setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
#endif

	/* FIFO cleared */
	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);

	/* RUN! */
	writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
}

void lcdif_power_down(void)
{
	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
	int timeout = 1000000;

	writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
	writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
	writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
	while (--timeout) {
		if (readl(&regs->hw_lcdif_ctrl1_reg) &
		    LCDIF_CTRL1_VSYNC_EDGE_IRQ)
			break;
		udelay(1);
	}
	mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
}

void *video_hw_init(void)
{
	int bpp = -1;
	char *penv;
	void *fb;
	struct ctfb_res_modes mode;

	puts("Video: ");

	/* Suck display configuration from "videomode" variable */
	penv = getenv("videomode");
	if (!penv) {
		puts("MXSFB: 'videomode' variable not set!\n");
		return NULL;
	}

	bpp = video_get_params(&mode, penv);

	/* fill in Graphic device struct */
	sprintf(panel.modeIdent, "%dx%dx%d",
			mode.xres, mode.yres, bpp);

	panel.winSizeX = mode.xres;
	panel.winSizeY = mode.yres;
	panel.plnSizeX = mode.xres;
	panel.plnSizeY = mode.yres;

	switch (bpp) {
	case 24:
	case 18:
		panel.gdfBytesPP = 4;
		panel.gdfIndex = GDF_32BIT_X888RGB;
		break;
	case 16:
		panel.gdfBytesPP = 2;
		panel.gdfIndex = GDF_16BIT_565RGB;
		break;
	case 8:
		panel.gdfBytesPP = 1;
		panel.gdfIndex = GDF__8BIT_INDEX;
		break;
	default:
		printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
		return NULL;
	}

	panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;

	/* Allocate framebuffer */
	fb = memalign(ARCH_DMA_MINALIGN,
		      roundup(panel.memSize, ARCH_DMA_MINALIGN));
	if (!fb) {
		printf("MXSFB: Error allocating framebuffer!\n");
		return NULL;
	}

	/* Wipe framebuffer */
	memset(fb, 0, panel.memSize);

	panel.frameAdrs = (u32)fb;

	printf("%s\n", panel.modeIdent);

	/* Start framebuffer */
	mxs_lcd_init(&panel, &mode, bpp);

#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
	/*
	 * If the LCD runs in system mode, the LCD refresh has to be triggered
	 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
	 * having to set this bit manually after every single change in the
	 * framebuffer memory, we set up specially crafted circular DMA, which
	 * sets the RUN bit, then waits until it gets cleared and repeats this
	 * infinitelly. This way, we get smooth continuous updates of the LCD.
	 */
	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;

	memset(&desc, 0, sizeof(struct mxs_dma_desc));
	desc.address = (dma_addr_t)&desc;
	desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
			MXS_DMA_DESC_WAIT4END |
			(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
	desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
	desc.cmd.next = (uint32_t)&desc.cmd;

	/* Execute the DMA chain. */
	mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
#endif

	return (void *)&panel;
}
Commit	Line	Data
fb8ddc24 MV	1	/*
	2	* Freescale i.MX23/i.MX28 LCDIF driver
	3	*
	4	* Copyright (C) 2011-2013 Marek Vasut <[email protected]>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
fb8ddc24 MV	7	*/
	8	#include <common.h>
	9	#include <malloc.h>
	10	#include <video_fb.h>
	11
	12	#include <asm/arch/imx-regs.h>
	13	#include <asm/arch/clock.h>
	14	#include <asm/arch/sys_proto.h>
	15	#include <asm/errno.h>
	16	#include <asm/io.h>
	17
84f957f8 MV	18	#include <asm/imx-common/dma.h>
84f957f8 MV	19
fb8ddc24 MV	20	#include "videomodes.h"
	21
	22	#define PS2KHZ(ps) (1000000000UL / (ps))
	23
	24	static GraphicDevice panel;
84f957f8	25	struct mxs_dma_desc desc;
fb8ddc24	26
9de4b729 MV	27	/**
	28	* mxsfb_system_setup() - Fine-tune LCDIF configuration
	29	*
	30	* This function is used to adjust the LCDIF configuration. This is usually
	31	* needed when driving the controller in System-Mode to operate an 8080 or
	32	* 6800 connected SmartLCD.
	33	*/
	34	__weak void mxsfb_system_setup(void)
	35	{
	36	}
	37
fb8ddc24 MV	38	/*
	39	* DENX M28EVK:
	40	* setenv videomode
	41	* video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
	42	* le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
11f98d1f FE	43	*
	44	* Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
	45	* setenv videomode
	46	* video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
	47	* le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
fb8ddc24 MV	48	*/
	49
	50	static void mxs_lcd_init(GraphicDevice *panel,
	51	struct ctfb_res_modes *mode, int bpp)
	52	{
	53	struct mxs_lcdif_regs regs = (struct mxs_lcdif_regs )MXS_LCDIF_BASE;
	54	uint32_t word_len = 0, bus_width = 0;
	55	uint8_t valid_data = 0;
	56
	57	/* Kick in the LCDIF clock */
95ae7000	58	mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
fb8ddc24 MV	59
	60	/* Restart the LCDIF block */
	61	mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
	62
	63	switch (bpp) {
	64	case 24:
	65	word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
	66	bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
	67	valid_data = 0x7;
	68	break;
	69	case 18:
	70	word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
	71	bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
	72	valid_data = 0x7;
	73	break;
	74	case 16:
	75	word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
	76	bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
	77	valid_data = 0xf;
	78	break;
	79	case 8:
	80	word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
	81	bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
	82	valid_data = 0xf;
	83	break;
	84	}
	85
	86	writel(bus_width \| word_len \| LCDIF_CTRL_DOTCLK_MODE \|
	87	LCDIF_CTRL_BYPASS_COUNT \| LCDIF_CTRL_LCDIF_MASTER,
	88	&regs->hw_lcdif_ctrl);
	89
	90	writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
	91	&regs->hw_lcdif_ctrl1);
9de4b729 MV	92
	93	mxsfb_system_setup();
	94
fb8ddc24 MV	95	writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) \| mode->xres,
	96	&regs->hw_lcdif_transfer_count);
	97
	98	writel(LCDIF_VDCTRL0_ENABLE_PRESENT \| LCDIF_VDCTRL0_ENABLE_POL \|
	99	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT \|
	100	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT \|
	101	mode->vsync_len, &regs->hw_lcdif_vdctrl0);
	102	writel(mode->upper_margin + mode->lower_margin +
	103	mode->vsync_len + mode->yres,
	104	&regs->hw_lcdif_vdctrl1);
	105	writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) \|
	106	(mode->left_margin + mode->right_margin +
	107	mode->hsync_len + mode->xres),
	108	&regs->hw_lcdif_vdctrl2);
	109	writel(((mode->left_margin + mode->hsync_len) <<
	110	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) \|
	111	(mode->upper_margin + mode->vsync_len),
	112	&regs->hw_lcdif_vdctrl3);
	113	writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) \| mode->xres,
	114	&regs->hw_lcdif_vdctrl4);
	115
	116	writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
	117	writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
	118
	119	/* Flush FIFO first */
	120	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
	121
9de4b729	122	#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
fb8ddc24 MV	123	/* Sync signals ON */
fb8ddc24 MV	124	setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
9de4b729	125	#endif
fb8ddc24 MV	126
	127	/* FIFO cleared */
	128	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
	129
	130	/* RUN! */
	131	writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
	132	}
	133
a3c252d6 PF	134	void lcdif_power_down(void)
	135	{
	136	struct mxs_lcdif_regs regs = (struct mxs_lcdif_regs )MXS_LCDIF_BASE;
	137	int timeout = 1000000;
	138
	139	writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
	140	writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
	141	writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
	142	while (--timeout) {
	143	if (readl(&regs->hw_lcdif_ctrl1_reg) &
	144	LCDIF_CTRL1_VSYNC_EDGE_IRQ)
	145	break;
	146	udelay(1);
	147	}
	148	mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
	149	}
	150
fb8ddc24 MV	151	void *video_hw_init(void)
	152	{
	153	int bpp = -1;
	154	char *penv;
	155	void *fb;
	156	struct ctfb_res_modes mode;
	157
	158	puts("Video: ");
	159
	160	/* Suck display configuration from "videomode" variable */
	161	penv = getenv("videomode");
	162	if (!penv) {
620ca1c1	163	puts("MXSFB: 'videomode' variable not set!\n");
fb8ddc24 MV	164	return NULL;
	165	}
	166
	167	bpp = video_get_params(&mode, penv);
	168
	169	/* fill in Graphic device struct */
	170	sprintf(panel.modeIdent, "%dx%dx%d",
	171	mode.xres, mode.yres, bpp);
	172
	173	panel.winSizeX = mode.xres;
	174	panel.winSizeY = mode.yres;
	175	panel.plnSizeX = mode.xres;
	176	panel.plnSizeY = mode.yres;
	177
	178	switch (bpp) {
	179	case 24:
	180	case 18:
	181	panel.gdfBytesPP = 4;
	182	panel.gdfIndex = GDF_32BIT_X888RGB;
	183	break;
	184	case 16:
	185	panel.gdfBytesPP = 2;
	186	panel.gdfIndex = GDF_16BIT_565RGB;
	187	break;
	188	case 8:
	189	panel.gdfBytesPP = 1;
	190	panel.gdfIndex = GDF__8BIT_INDEX;
	191	break;
	192	default:
	193	printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
	194	return NULL;
	195	}
	196
	197	panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
	198
	199	/* Allocate framebuffer */
e57baf5d MV	200	fb = memalign(ARCH_DMA_MINALIGN,
e57baf5d MV	201	roundup(panel.memSize, ARCH_DMA_MINALIGN));
fb8ddc24 MV	202	if (!fb) {
	203	printf("MXSFB: Error allocating framebuffer!\n");
	204	return NULL;
	205	}
	206
	207	/* Wipe framebuffer */
	208	memset(fb, 0, panel.memSize);
	209
	210	panel.frameAdrs = (u32)fb;
	211
	212	printf("%s\n", panel.modeIdent);
	213
	214	/* Start framebuffer */
	215	mxs_lcd_init(&panel, &mode, bpp);
	216
84f957f8 MV	217	#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
	218	/*
	219	* If the LCD runs in system mode, the LCD refresh has to be triggered
	220	* manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
	221	* having to set this bit manually after every single change in the
	222	* framebuffer memory, we set up specially crafted circular DMA, which
	223	* sets the RUN bit, then waits until it gets cleared and repeats this
	224	* infinitelly. This way, we get smooth continuous updates of the LCD.
	225	*/
	226	struct mxs_lcdif_regs regs = (struct mxs_lcdif_regs )MXS_LCDIF_BASE;
	227
	228	memset(&desc, 0, sizeof(struct mxs_dma_desc));
	229	desc.address = (dma_addr_t)&desc;
	230	desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER \| MXS_DMA_DESC_CHAIN \|
	231	MXS_DMA_DESC_WAIT4END \|
	232	(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
	233	desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) \| LCDIF_CTRL_RUN;
	234	desc.cmd.next = (uint32_t)&desc.cmd;
	235
	236	/* Execute the DMA chain. */
	237	mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
	238	#endif
	239
fb8ddc24 MV	240	return (void *)&panel;
fb8ddc24 MV	241	}