[J-u-boot.git] / drivers / video / mpc8xx_lcd.c

/*
 * (C) Copyright 2001-2002
 * Wolfgang Denk, DENX Software Engineering -- [email protected]
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************/
/* ** HEADER FILES							*/
/************************************************************************/

/* #define DEBUG */

#include <config.h>
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <stdarg.h>
#include <lcdvideo.h>
#include <linux/types.h>
#include <stdio_dev.h>
#if defined(CONFIG_POST)
#include <post.h>
#endif
#include <lcd.h>

#ifdef CONFIG_LCD

/************************************************************************/
/* ** CONFIG STUFF -- should be moved to board config file		*/
/************************************************************************/
#ifndef CONFIG_LCD_INFO
#define CONFIG_LCD_INFO		/* Display Logo, (C) and system info	*/
#endif

/*----------------------------------------------------------------------*/
#ifdef CONFIG_KYOCERA_KCS057QV1AJ
/*
 *  Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
 */
#define LCD_BPP	LCD_COLOR4

vidinfo_t panel_info = {
    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
    LCD_BPP, 1, 0, 1, 0,  5, 0, 0, 0
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
/*----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SP19X001_Z1A
/*
 *  Hitachi SP19X001-. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
    LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_HITACHI_SP19X001_Z1A */
/*----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/
#ifdef CONFIG_NEC_NL6448AC33
/*
 *  NEC NL6448AC33-18. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 144, 2, 0, 33
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448AC33 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_NEC_NL6448BC20
/*
 *  NEC NL6448BC20-08.  6.5", 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 144, 2, 0, 33
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448BC20 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_NEC_NL6448BC33_54
/*
 *  NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 144, 2, 0, 33
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448BC33_54 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_SHARP_LQ104V7DS01
/*
 *  SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
    3, 0, 0, 1, 1, 25, 1, 0, 33
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ104V7DS01 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_SHARP_16x9
/*
 * Sharp 320x240. Active, color, single scan.  It isn't 16x9, and I am
 * not sure what it is.......
 */
vidinfo_t panel_info = {
    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 15, 4, 0, 3
};
#endif /* CONFIG_SHARP_16x9 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_SHARP_LQ057Q3DC02
/*
 * Sharp LQ057Q3DC02 display. Active, color, single scan.
 */
#undef LCD_DF
#define LCD_DF 12

vidinfo_t panel_info = {
    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 15, 4, 0, 3
		/* wbl, vpw, lcdac, wbf */
};
#define CONFIG_LCD_INFO_BELOW_LOGO
#endif /* CONFIG_SHARP_LQ057Q3DC02 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_SHARP_LQ64D341
/*
 * Sharp LQ64D341 display, 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 128, 16, 0, 32
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ64D341 */

#ifdef CONFIG_SHARP_LQ065T9DR51U
/*
 * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
 */
vidinfo_t panel_info = {
    400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 248, 4, 0, 35
		/* wbl, vpw, lcdac, wbf */
};
#define CONFIG_LCD_INFO_BELOW_LOGO
#endif /* CONFIG_SHARP_LQ065T9DR51U */

#ifdef CONFIG_SHARP_LQ084V1DG21
/*
 * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
    3, 0, 0, 1, 1, 160, 3, 0, 48
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ084V1DG21 */

/*----------------------------------------------------------------------*/

#ifdef CONFIG_HLD1045
/*
 * HLD1045 display, 640x480. Active, color, single scan.
 */
vidinfo_t panel_info = {
    640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 160, 3, 0, 48
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_HLD1045 */
/*----------------------------------------------------------------------*/

#ifdef CONFIG_PRIMEVIEW_V16C6448AC
/*
 * Prime View V16C6448AC
 */
vidinfo_t panel_info = {
    640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
    3, 0, 0, 1, 1, 144, 2, 0, 35
		/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_PRIMEVIEW_V16C6448AC */

/*----------------------------------------------------------------------*/

#ifdef CONFIG_OPTREX_BW
/*
 * Optrex   CBL50840-2 NF-FW 99 22 M5
 * or
 * Hitachi  LMG6912RPFC-00T
 * or
 * Hitachi  SP14Q002
 *
 * 320x240. Black & white.
 */
#define OPTREX_BPP	0	/* 0 - monochrome,     1 bpp */
				/* 1 -  4 grey levels, 2 bpp */
				/* 2 - 16 grey levels, 4 bpp */
vidinfo_t panel_info = {
    320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
    OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
};
#endif /* CONFIG_OPTREX_BW */

/************************************************************************/
/* ----------------- chipset specific functions ----------------------- */
/************************************************************************/

/*
 * Calculate fb size for VIDEOLFB_ATAG.
 */
ulong calc_fbsize (void)
{
	ulong size;
	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;

	size = line_length * panel_info.vl_row;

	return size;
}

void lcd_ctrl_init (void *lcdbase)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile lcd823_t *lcdp = &immr->im_lcd;

	uint lccrtmp;
	uint lchcr_hpc_tmp;

	/* Initialize the LCD control register according to the LCD
	 * parameters defined.  We do everything here but enable
	 * the controller.
	 */

	lccrtmp  = LCDBIT (LCCR_BNUM_BIT,
		   (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));

	lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp)	|
		   LCDBIT (LCCR_OEP_BIT,  panel_info.vl_oep)	|
		   LCDBIT (LCCR_HSP_BIT,  panel_info.vl_hsp)	|
		   LCDBIT (LCCR_VSP_BIT,  panel_info.vl_vsp)	|
		   LCDBIT (LCCR_DP_BIT,   panel_info.vl_dp)	|
		   LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix)	|
		   LCDBIT (LCCR_LBW_BIT,  panel_info.vl_lbw)	|
		   LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt)	|
		   LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor)	|
		   LCDBIT (LCCR_TFT_BIT,  panel_info.vl_tft);

#if 0
	lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
	lccrtmp |= LCCR_EIEN;
#endif

	lcdp->lcd_lccr = lccrtmp;
	lcdp->lcd_lcsr = 0xFF;		/* Clear pending interrupts */

	/* Initialize LCD controller bus priorities.
	 */
	immr->im_siu_conf.sc_sdcr &= ~0x0f;	/* RAID = LAID = 0 */

	/* set SHFT/CLOCK division factor 4
	 * This needs to be set based upon display type and processor
	 * speed.  The TFT displays run about 20 to 30 MHz.
	 * I was running 64 MHz processor speed.
	 * The value for this divider must be chosen so the result is
	 * an integer of the processor speed (i.e., divide by 3 with
	 * 64 MHz would be bad).
	 */
	immr->im_clkrst.car_sccr &= ~0x1F;
	immr->im_clkrst.car_sccr |= LCD_DF;	/* was 8 */

	/* Enable LCD on port D.
	 */
	immr->im_ioport.iop_pdpar |= 0x1FFF;
	immr->im_ioport.iop_pddir |= 0x1FFF;

	/* Enable LCD_A/B/C on port B.
	 */
	immr->im_cpm.cp_pbpar |= 0x00005001;
	immr->im_cpm.cp_pbdir |= 0x00005001;

	/* Load the physical address of the linear frame buffer
	 * into the LCD controller.
	 * BIG NOTE:  This has to be modified to load A and B depending
	 * upon the split mode of the LCD.
	 */
	lcdp->lcd_lcfaa = (ulong)lcdbase;
	lcdp->lcd_lcfba = (ulong)lcdbase;

	/* MORE HACKS...This must be updated according to 823 manual
	 * for different panels.
	 * Udi Finkelstein - done - see below:
	 * Note: You better not try unsupported combinations such as
	 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
	 */
	lchcr_hpc_tmp =
		(panel_info.vl_col *
		 (panel_info.vl_tft ? 8 :
			(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
			 /* use << to mult by: single scan = 1, dual scan = 2 */
			  panel_info.vl_splt) *
			 (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */

	lcdp->lcd_lchcr = LCHCR_BO |
			  LCDBIT (LCHCR_AT_BIT, 4) |
			  LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
			  panel_info.vl_wbl;

	lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
			  LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
			  LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
			  panel_info.vl_wbf;

}

/*----------------------------------------------------------------------*/

#if LCD_BPP == LCD_COLOR8
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cp = &(immr->im_cpm);
	unsigned short colreg, *cmap_ptr;

	cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];

	colreg = ((red   & 0x0F) << 8) |
		 ((green & 0x0F) << 4) |
		  (blue  & 0x0F) ;

	*cmap_ptr = colreg;

	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
		regno, &(cp->lcd_cmap[regno * 2]),
		red, green, blue,
		cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
}
#endif	/* LCD_COLOR8 */

/*----------------------------------------------------------------------*/

ushort *configuration_get_cmap(void)
{
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	cpm8xx_t *cp = &(immr->im_cpm);
	return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
}

#if defined(CONFIG_MPC823)
void fb_put_byte(uchar **fb, uchar **from)
{
	*(*fb)++ = (255 - *(*from)++);
}
#endif

#ifdef CONFIG_LCD_LOGO
#include <bmp_logo.h>
void lcd_logo_set_cmap(void)
{
	int i;
	ushort *cmap;
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	cpm8xx_t *cp = &(immr->im_cpm);
	cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET * sizeof(ushort)]);

	for (i = 0; i < BMP_LOGO_COLORS; ++i)
		*cmap++ = bmp_logo_palette[i];
}
#endif

void lcd_enable (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile lcd823_t *lcdp = &immr->im_lcd;

	/* Enable the LCD panel */
	immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25));		/* LAM = 1 */
	lcdp->lcd_lccr |= LCCR_PON;
}

/************************************************************************/

#endif /* CONFIG_LCD */
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* (C) Copyright 2001-2002
	3	* Wolfgang Denk, DENX Software Engineering -- [email protected]
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
5b1d7137 WD	6	*/
	7
	8	/************************************************************************/
	9	/* ** HEADER FILES */
	10	/************************************************************************/
	11
8564acf9 WD	12	/* #define DEBUG */
8564acf9 WD	13
5b1d7137 WD	14	#include <config.h>
5b1d7137 WD	15	#include <common.h>
c3f4d17e	16	#include <command.h>
7aa78614	17	#include <watchdog.h>
5b1d7137 WD	18	#include <stdarg.h>
	19	#include <lcdvideo.h>
	20	#include <linux/types.h>
52cb4d4f	21	#include <stdio_dev.h>
4532cb69 WD	22	#if defined(CONFIG_POST)
	23	#include <post.h>
	24	#endif
682011ff	25	#include <lcd.h>
5b1d7137 WD	26
	27	#ifdef CONFIG_LCD
	28
	29	/************************************************************************/
	30	/* ** CONFIG STUFF -- should be moved to board config file */
	31	/************************************************************************/
88804d19 WD	32	#ifndef CONFIG_LCD_INFO
	33	#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
	34	#endif
608c9146	35
5b1d7137 WD	36	/----------------------------------------------------------------------/
	37	#ifdef CONFIG_KYOCERA_KCS057QV1AJ
	38	/*
	39	* Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
	40	*/
	41	#define LCD_BPP LCD_COLOR4
	42
8655b6f8	43	vidinfo_t panel_info = {
6d0f6bcf	44	640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
5b1d7137 WD	45	LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
	46	/* wbl, vpw, lcdac, wbf */
	47	};
	48	#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
	49	/----------------------------------------------------------------------/
	50
682011ff WD	51	/----------------------------------------------------------------------/
	52	#ifdef CONFIG_HITACHI_SP19X001_Z1A
	53	/*
	54	* Hitachi SP19X001-. Active, color, single scan.
	55	*/
8655b6f8	56	vidinfo_t panel_info = {
6d0f6bcf	57	640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
682011ff WD	58	LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
	59	/* wbl, vpw, lcdac, wbf */
	60	};
	61	#endif /* CONFIG_HITACHI_SP19X001_Z1A */
	62	/----------------------------------------------------------------------/
	63
5b1d7137	64	/----------------------------------------------------------------------/
fd3103bb	65	#ifdef CONFIG_NEC_NL6448AC33
5b1d7137	66	/*
fd3103bb	67	* NEC NL6448AC33-18. Active, color, single scan.
5b1d7137	68	*/
8655b6f8	69	vidinfo_t panel_info = {
6d0f6bcf	70	640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	71	3, 0, 0, 1, 1, 144, 2, 0, 33
	72	/* wbl, vpw, lcdac, wbf */
	73	};
fd3103bb	74	#endif /* CONFIG_NEC_NL6448AC33 */
5b1d7137 WD	75	/----------------------------------------------------------------------/
5b1d7137 WD	76
fd3103bb	77	#ifdef CONFIG_NEC_NL6448BC20
5b1d7137	78	/*
fd3103bb	79	* NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
5b1d7137	80	*/
8655b6f8	81	vidinfo_t panel_info = {
6d0f6bcf	82	640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	83	3, 0, 0, 1, 1, 144, 2, 0, 33
	84	/* wbl, vpw, lcdac, wbf */
	85	};
fd3103bb WD	86	#endif /* CONFIG_NEC_NL6448BC20 */
	87	/----------------------------------------------------------------------/
	88
	89	#ifdef CONFIG_NEC_NL6448BC33_54
	90	/*
	91	* NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
	92	*/
8655b6f8	93	vidinfo_t panel_info = {
6d0f6bcf	94	640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
fd3103bb WD	95	3, 0, 0, 1, 1, 144, 2, 0, 33
	96	/* wbl, vpw, lcdac, wbf */
	97	};
	98	#endif /* CONFIG_NEC_NL6448BC33_54 */
5b1d7137 WD	99	/----------------------------------------------------------------------/
	100
	101	#ifdef CONFIG_SHARP_LQ104V7DS01
	102	/*
	103	* SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
	104	*/
8655b6f8	105	vidinfo_t panel_info = {
6d0f6bcf	106	640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
5b1d7137 WD	107	3, 0, 0, 1, 1, 25, 1, 0, 33
	108	/* wbl, vpw, lcdac, wbf */
	109	};
	110	#endif /* CONFIG_SHARP_LQ104V7DS01 */
	111	/----------------------------------------------------------------------/
	112
	113	#ifdef CONFIG_SHARP_16x9
	114	/*
	115	* Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
	116	* not sure what it is.......
	117	*/
8655b6f8	118	vidinfo_t panel_info = {
6d0f6bcf	119	320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
5b1d7137 WD	120	3, 0, 0, 1, 1, 15, 4, 0, 3
	121	};
	122	#endif /* CONFIG_SHARP_16x9 */
	123	/----------------------------------------------------------------------/
	124
	125	#ifdef CONFIG_SHARP_LQ057Q3DC02
	126	/*
	127	* Sharp LQ057Q3DC02 display. Active, color, single scan.
	128	*/
8655b6f8	129	#undef LCD_DF
4a6fd34b WD	130	#define LCD_DF 12
4a6fd34b WD	131
8655b6f8	132	vidinfo_t panel_info = {
6d0f6bcf	133	320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	134	3, 0, 0, 1, 1, 15, 4, 0, 3
	135	/* wbl, vpw, lcdac, wbf */
	136	};
88804d19	137	#define CONFIG_LCD_INFO_BELOW_LOGO
5b1d7137 WD	138	#endif /* CONFIG_SHARP_LQ057Q3DC02 */
	139	/----------------------------------------------------------------------/
	140
	141	#ifdef CONFIG_SHARP_LQ64D341
	142	/*
	143	* Sharp LQ64D341 display, 640x480. Active, color, single scan.
	144	*/
8655b6f8	145	vidinfo_t panel_info = {
6d0f6bcf	146	640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	147	3, 0, 0, 1, 1, 128, 16, 0, 32
	148	/* wbl, vpw, lcdac, wbf */
	149	};
	150	#endif /* CONFIG_SHARP_LQ64D341 */
608c9146	151
29127b6a	152	#ifdef CONFIG_SHARP_LQ065T9DR51U
	153	/*
	154	* Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
	155	*/
8655b6f8	156	vidinfo_t panel_info = {
6d0f6bcf	157	400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
29127b6a	158	3, 0, 0, 1, 1, 248, 4, 0, 35
	159	/* wbl, vpw, lcdac, wbf */
	160	};
88804d19	161	#define CONFIG_LCD_INFO_BELOW_LOGO
29127b6a	162	#endif /* CONFIG_SHARP_LQ065T9DR51U */
29127b6a	163
608c9146 WD	164	#ifdef CONFIG_SHARP_LQ084V1DG21
	165	/*
	166	* Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
	167	*/
8655b6f8	168	vidinfo_t panel_info = {
6d0f6bcf	169	640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
608c9146 WD	170	3, 0, 0, 1, 1, 160, 3, 0, 48
	171	/* wbl, vpw, lcdac, wbf */
	172	};
	173	#endif /* CONFIG_SHARP_LQ084V1DG21 */
	174
5b1d7137 WD	175	/----------------------------------------------------------------------/
	176
	177	#ifdef CONFIG_HLD1045
	178	/*
	179	* HLD1045 display, 640x480. Active, color, single scan.
	180	*/
8655b6f8	181	vidinfo_t panel_info = {
6d0f6bcf	182	640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	183	3, 0, 0, 1, 1, 160, 3, 0, 48
	184	/* wbl, vpw, lcdac, wbf */
	185	};
	186	#endif /* CONFIG_HLD1045 */
	187	/----------------------------------------------------------------------/
	188
	189	#ifdef CONFIG_PRIMEVIEW_V16C6448AC
	190	/*
	191	* Prime View V16C6448AC
	192	*/
8655b6f8	193	vidinfo_t panel_info = {
6d0f6bcf	194	640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
5b1d7137 WD	195	3, 0, 0, 1, 1, 144, 2, 0, 35
	196	/* wbl, vpw, lcdac, wbf */
	197	};
	198	#endif /* CONFIG_PRIMEVIEW_V16C6448AC */
	199
	200	/----------------------------------------------------------------------/
	201
	202	#ifdef CONFIG_OPTREX_BW
	203	/*
	204	* Optrex CBL50840-2 NF-FW 99 22 M5
	205	* or
	206	* Hitachi LMG6912RPFC-00T
	207	* or
	208	* Hitachi SP14Q002
	209	*
	210	* 320x240. Black & white.
	211	*/
	212	#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
	213	/* 1 - 4 grey levels, 2 bpp */
	214	/* 2 - 16 grey levels, 4 bpp */
8655b6f8	215	vidinfo_t panel_info = {
6d0f6bcf	216	320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
5b1d7137 WD	217	OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
	218	};
	219	#endif /* CONFIG_OPTREX_BW */
	220
5b1d7137	221	/************************************************************************/
8655b6f8	222	/* ----------------- chipset specific functions ----------------------- */
5b1d7137 WD	223	/************************************************************************/
	224
	225	/*
8655b6f8	226	* Calculate fb size for VIDEOLFB_ATAG.
5b1d7137	227	*/
8655b6f8	228	ulong calc_fbsize (void)
5b1d7137 WD	229	{
	230	ulong size;
	231	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
	232
5b1d7137 WD	233	size = line_length * panel_info.vl_row;
5b1d7137 WD	234
8655b6f8	235	return size;
5b1d7137 WD	236	}
5b1d7137 WD	237
8655b6f8	238	void lcd_ctrl_init (void *lcdbase)
5b1d7137	239	{
6d0f6bcf	240	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
5b1d7137 WD	241	volatile lcd823_t *lcdp = &immr->im_lcd;
	242
	243	uint lccrtmp;
682011ff	244	uint lchcr_hpc_tmp;
5b1d7137 WD	245
	246	/* Initialize the LCD control register according to the LCD
	247	* parameters defined. We do everything here but enable
	248	* the controller.
	249	*/
	250
	251	lccrtmp = LCDBIT (LCCR_BNUM_BIT,
	252	(((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
	253
	254	lccrtmp \|= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) \|
	255	LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) \|
	256	LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) \|
	257	LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) \|
	258	LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) \|
	259	LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) \|
	260	LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) \|
	261	LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) \|
	262	LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) \|
	263	LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft);
	264
	265	#if 0
	266	lccrtmp \|= ((SIU_LEVEL5 / 2) << 12);
	267	lccrtmp \|= LCCR_EIEN;
	268	#endif
	269
	270	lcdp->lcd_lccr = lccrtmp;
	271	lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */
	272
	273	/* Initialize LCD controller bus priorities.
	274	*/
	275	immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
	276
	277	/* set SHFT/CLOCK division factor 4
	278	* This needs to be set based upon display type and processor
	279	* speed. The TFT displays run about 20 to 30 MHz.
	280	* I was running 64 MHz processor speed.
	281	* The value for this divider must be chosen so the result is
	282	* an integer of the processor speed (i.e., divide by 3 with
	283	* 64 MHz would be bad).
	284	*/
	285	immr->im_clkrst.car_sccr &= ~0x1F;
	286	immr->im_clkrst.car_sccr \|= LCD_DF; /* was 8 */
	287
5b1d7137 WD	288	/* Enable LCD on port D.
	289	*/
	290	immr->im_ioport.iop_pdpar \|= 0x1FFF;
	291	immr->im_ioport.iop_pddir \|= 0x1FFF;
	292
	293	/* Enable LCD_A/B/C on port B.
	294	*/
	295	immr->im_cpm.cp_pbpar \|= 0x00005001;
	296	immr->im_cpm.cp_pbdir \|= 0x00005001;
5b1d7137 WD	297
	298	/* Load the physical address of the linear frame buffer
	299	* into the LCD controller.
	300	* BIG NOTE: This has to be modified to load A and B depending
	301	* upon the split mode of the LCD.
	302	*/
00a0ca59 JH	303	lcdp->lcd_lcfaa = (ulong)lcdbase;
00a0ca59 JH	304	lcdp->lcd_lcfba = (ulong)lcdbase;
5b1d7137 WD	305
	306	/* MORE HACKS...This must be updated according to 823 manual
	307	* for different panels.
682011ff WD	308	* Udi Finkelstein - done - see below:
	309	* Note: You better not try unsupported combinations such as
	310	* 4-bit wide passive dual scan LCD at 4/8 Bit color.
5b1d7137	311	*/
682011ff	312	lchcr_hpc_tmp =
8bde7f77	313	(panel_info.vl_col *
682011ff WD	314	(panel_info.vl_tft ? 8 :
	315	(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
	316	/* use << to mult by: single scan = 1, dual scan = 2 */
	317	panel_info.vl_splt) *
	318	(panel_info.vl_bpix \| 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
	319
5b1d7137 WD	320	lcdp->lcd_lchcr = LCHCR_BO \|
5b1d7137 WD	321	LCDBIT (LCHCR_AT_BIT, 4) \|
682011ff	322	LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) \|
5b1d7137	323	panel_info.vl_wbl;
5b1d7137 WD	324
	325	lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) \|
	326	LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) \|
	327	LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) \|
	328	panel_info.vl_wbf;
	329
	330	}
	331
	332	/----------------------------------------------------------------------/
	333
5b1d7137	334	#if LCD_BPP == LCD_COLOR8
8655b6f8	335	void
5b1d7137 WD	336	lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
5b1d7137 WD	337	{
6d0f6bcf	338	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
5b1d7137 WD	339	volatile cpm8xx_t *cp = &(immr->im_cpm);
	340	unsigned short colreg, *cmap_ptr;
	341
	342	cmap_ptr = (unsigned short )&cp->lcd_cmap[regno 2];
	343
	344	colreg = ((red & 0x0F) << 8) \|
	345	((green & 0x0F) << 4) \|
	346	(blue & 0x0F) ;
dc6b5b3a	347
5b1d7137 WD	348	*cmap_ptr = colreg;
	349
	350	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
	351	regno, &(cp->lcd_cmap[regno * 2]),
	352	red, green, blue,
8bde7f77	353	cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
5b1d7137 WD	354	}
	355	#endif /* LCD_COLOR8 */
	356
	357	/----------------------------------------------------------------------/
	358
38b55087 NK	359	ushort *configuration_get_cmap(void)
	360	{
	361	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	362	cpm8xx_t *cp = &(immr->im_cpm);
	363	return (ushort )&(cp->lcd_cmap[255 sizeof(ushort)]);
	364	}
	365
27fad01b NK	366	#if defined(CONFIG_MPC823)
	367	void fb_put_byte(uchar fb, uchar from)
	368	{
	369	(fb)++ = (255 - (from)++);
	370	}
	371	#endif
	372
0ee261f6 NK	373	#ifdef CONFIG_LCD_LOGO
	374	#include <bmp_logo.h>
	375	void lcd_logo_set_cmap(void)
	376	{
	377	int i;
	378	ushort *cmap;
	379	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	380	cpm8xx_t *cp = &(immr->im_cpm);
	381	cmap = (ushort )&(cp->lcd_cmap[BMP_LOGO_OFFSET sizeof(ushort)]);
	382
	383	for (i = 0; i < BMP_LOGO_COLORS; ++i)
	384	*cmap++ = bmp_logo_palette[i];
	385	}
	386	#endif
	387
8655b6f8	388	void lcd_enable (void)
5b1d7137	389	{
6d0f6bcf	390	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
5b1d7137 WD	391	volatile lcd823_t *lcdp = &immr->im_lcd;
	392
	393	/* Enable the LCD panel */
	394	immr->im_siu_conf.sc_sdcr \|= (1 << (31 - 25)); /* LAM = 1 */
	395	lcdp->lcd_lccr \|= LCCR_PON;
5b1d7137 WD	396	}
5b1d7137 WD	397
5b1d7137 WD	398	/************************************************************************/
	399
	400	#endif /* CONFIG_LCD */