[J-u-boot.git] / arch / x86 / cpu / irq.c

/*
 * Copyright (C) 2015, Bin Meng <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/pirq_routing.h>

DECLARE_GLOBAL_DATA_PTR;

static struct irq_router irq_router;
static struct irq_routing_table *pirq_routing_table;

bool pirq_check_irq_routed(int link, u8 irq)
{
	u8 pirq;
	int base = irq_router.link_base;

	if (irq_router.config == PIRQ_VIA_PCI)
		pirq = x86_pci_read_config8(irq_router.bdf,
					    LINK_N2V(link, base));
	else
		pirq = readb(irq_router.ibase + LINK_N2V(link, base));

	pirq &= 0xf;

	/* IRQ# 0/1/2/8/13 are reserved */
	if (pirq < 3 || pirq == 8 || pirq == 13)
		return false;

	return pirq == irq ? true : false;
}

int pirq_translate_link(int link)
{
	return LINK_V2N(link, irq_router.link_base);
}

void pirq_assign_irq(int link, u8 irq)
{
	int base = irq_router.link_base;

	/* IRQ# 0/1/2/8/13 are reserved */
	if (irq < 3 || irq == 8 || irq == 13)
		return;

	if (irq_router.config == PIRQ_VIA_PCI)
		x86_pci_write_config8(irq_router.bdf,
				      LINK_N2V(link, base), irq);
	else
		writeb(irq, irq_router.ibase + LINK_N2V(link, base));
}

static struct irq_info *check_dup_entry(struct irq_info *slot_base,
					int entry_num, int bus, int device)
{
	struct irq_info *slot = slot_base;
	int i;

	for (i = 0; i < entry_num; i++) {
		if (slot->bus == bus && slot->devfn == (device << 3))
			break;
		slot++;
	}

	return (i == entry_num) ? NULL : slot;
}

static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
				 int pin, int pirq)
{
	slot->bus = bus;
	slot->devfn = (device << 3) | 0;
	slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
	slot->irq[pin - 1].bitmap = irq_router.irq_mask;
}

__weak void cpu_irq_init(void)
{
	return;
}

static int create_pirq_routing_table(void)
{
	const void *blob = gd->fdt_blob;
	struct fdt_pci_addr addr;
	int node;
	int len, count;
	const u32 *cell;
	struct irq_routing_table *rt;
	struct irq_info *slot, *slot_base;
	int irq_entries = 0;
	int parent;
	int i;
	int ret;

	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER);
	if (node < 0) {
		debug("%s: Cannot find irq router node\n", __func__);
		return -EINVAL;
	}

	/* TODO([email protected]): Drop this when PIRQ is a driver */
	parent = fdt_parent_offset(blob, node);
	if (parent < 0)
		return -EINVAL;
	ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
				  "reg", &addr);
	if (ret)
		return ret;

	/* extract the bdf from fdt_pci_addr */
	irq_router.bdf = addr.phys_hi & 0xffff00;

	ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
	if (!ret) {
		irq_router.config = PIRQ_VIA_PCI;
	} else {
		ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
		if (!ret)
			irq_router.config = PIRQ_VIA_IBASE;
		else
			return -EINVAL;
	}

	ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
	if (ret == -1)
		return ret;
	irq_router.link_base = ret;

	irq_router.irq_mask = fdtdec_get_int(blob, node,
					     "intel,pirq-mask", PIRQ_BITMAP);

	if (irq_router.config == PIRQ_VIA_IBASE) {
		int ibase_off;

		ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
		if (!ibase_off)
			return -EINVAL;

		/*
		 * Here we assume that the IBASE register has already been
		 * properly configured by U-Boot before.
		 *
		 * By 'valid' we mean:
		 *   1) a valid memory space carved within system memory space
		 *      assigned to IBASE register block.
		 *   2) memory range decoding is enabled.
		 * Hence we don't do any santify test here.
		 */
		irq_router.ibase = x86_pci_read_config32(irq_router.bdf,
							 ibase_off);
		irq_router.ibase &= ~0xf;
	}

	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
	if (!cell || len % sizeof(struct pirq_routing))
		return -EINVAL;
	count = len / sizeof(struct pirq_routing);

	rt = calloc(1, sizeof(struct irq_routing_table));
	if (!rt)
		return -ENOMEM;

	/* Populate the PIRQ table fields */
	rt->signature = PIRQ_SIGNATURE;
	rt->version = PIRQ_VERSION;
	rt->rtr_bus = PCI_BUS(irq_router.bdf);
	rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) |
			PCI_FUNC(irq_router.bdf);
	rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
	rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;

	slot_base = rt->slots;

	/* Now fill in the irq_info entries in the PIRQ table */
	for (i = 0; i < count;
	     i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
		struct pirq_routing pr;

		pr.bdf = fdt_addr_to_cpu(cell[0]);
		pr.pin = fdt_addr_to_cpu(cell[1]);
		pr.pirq = fdt_addr_to_cpu(cell[2]);

		debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
		      i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
		      PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
		      'A' + pr.pirq);

		slot = check_dup_entry(slot_base, irq_entries,
				       PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
		if (slot) {
			debug("found entry for bus %d device %d, ",
			      PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));

			if (slot->irq[pr.pin - 1].link) {
				debug("skipping\n");

				/*
				 * Sanity test on the routed PIRQ pin
				 *
				 * If they don't match, show a warning to tell
				 * there might be something wrong with the PIRQ
				 * routing information in the device tree.
				 */
				if (slot->irq[pr.pin - 1].link !=
					LINK_N2V(pr.pirq, irq_router.link_base))
					debug("WARNING: Inconsistent PIRQ routing information\n");
				continue;
			}
		} else {
			slot = slot_base + irq_entries++;
		}
		debug("writing INT%c\n", 'A' + pr.pin - 1);
		fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin,
			      pr.pirq);
	}

	rt->size = irq_entries * sizeof(struct irq_info) + 32;

	pirq_routing_table = rt;

	return 0;
}

int irq_router_probe(struct udevice *dev)
{
	int ret;

	cpu_irq_init();

	ret = create_pirq_routing_table();
	if (ret) {
		debug("Failed to create pirq routing table\n");
		return ret;
	}
	/* Route PIRQ */
	pirq_route_irqs(pirq_routing_table->slots,
			get_irq_slot_count(pirq_routing_table));

	return 0;
}

u32 write_pirq_routing_table(u32 addr)
{
	if (!pirq_routing_table)
		return addr;

	return copy_pirq_routing_table(addr, pirq_routing_table);
}

static const struct udevice_id irq_router_ids[] = {
	{ .compatible = "intel,irq-router" },
	{ }
};

U_BOOT_DRIVER(irq_router_drv) = {
	.name		= "intel_irq",
	.id		= UCLASS_IRQ,
	.of_match	= irq_router_ids,
	.probe		= irq_router_probe,
};

UCLASS_DRIVER(irq) = {
	.id		= UCLASS_IRQ,
	.name		= "irq",
};
Commit	Line	Data
9c7dea60 BM	1	/*
	2	* Copyright (C) 2015, Bin Meng <[email protected]>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
e76187a3	8	#include <dm.h>
9c7dea60 BM	9	#include <errno.h>
	10	#include <fdtdec.h>
	11	#include <malloc.h>
	12	#include <asm/io.h>
	13	#include <asm/irq.h>
	14	#include <asm/pci.h>
	15	#include <asm/pirq_routing.h>
	16
	17	DECLARE_GLOBAL_DATA_PTR;
	18
	19	static struct irq_router irq_router;
	20	static struct irq_routing_table *pirq_routing_table;
	21
	22	bool pirq_check_irq_routed(int link, u8 irq)
	23	{
	24	u8 pirq;
	25	int base = irq_router.link_base;
	26
	27	if (irq_router.config == PIRQ_VIA_PCI)
	28	pirq = x86_pci_read_config8(irq_router.bdf,
	29	LINK_N2V(link, base));
	30	else
	31	pirq = readb(irq_router.ibase + LINK_N2V(link, base));
	32
	33	pirq &= 0xf;
	34
	35	/* IRQ# 0/1/2/8/13 are reserved */
	36	if (pirq < 3 \|\| pirq == 8 \|\| pirq == 13)
	37	return false;
	38
	39	return pirq == irq ? true : false;
	40	}
	41
	42	int pirq_translate_link(int link)
	43	{
	44	return LINK_V2N(link, irq_router.link_base);
	45	}
	46
	47	void pirq_assign_irq(int link, u8 irq)
	48	{
	49	int base = irq_router.link_base;
	50
	51	/* IRQ# 0/1/2/8/13 are reserved */
	52	if (irq < 3 \|\| irq == 8 \|\| irq == 13)
	53	return;
	54
	55	if (irq_router.config == PIRQ_VIA_PCI)
	56	x86_pci_write_config8(irq_router.bdf,
	57	LINK_N2V(link, base), irq);
	58	else
	59	writeb(irq, irq_router.ibase + LINK_N2V(link, base));
	60	}
	61
df81749d BM	62	static struct irq_info check_dup_entry(struct irq_info slot_base,
df81749d BM	63	int entry_num, int bus, int device)
9c7dea60	64	{
df81749d BM	65	struct irq_info *slot = slot_base;
	66	int i;
	67
	68	for (i = 0; i < entry_num; i++) {
	69	if (slot->bus == bus && slot->devfn == (device << 3))
	70	break;
	71	slot++;
	72	}
9c7dea60	73
df81749d BM	74	return (i == entry_num) ? NULL : slot;
	75	}
	76
	77	static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
	78	int pin, int pirq)
	79	{
9c7dea60	80	slot->bus = bus;
8c38e4d0	81	slot->devfn = (device << 3) \| 0;
9c7dea60 BM	82	slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
9c7dea60 BM	83	slot->irq[pin - 1].bitmap = irq_router.irq_mask;
9c7dea60 BM	84	}
	85
	86	__weak void cpu_irq_init(void)
	87	{
	88	return;
	89	}
	90
	91	static int create_pirq_routing_table(void)
	92	{
	93	const void *blob = gd->fdt_blob;
	94	struct fdt_pci_addr addr;
	95	int node;
	96	int len, count;
	97	const u32 *cell;
	98	struct irq_routing_table *rt;
df81749d	99	struct irq_info slot, slot_base;
9c7dea60	100	int irq_entries = 0;
f2b85ab5	101	int parent;
9c7dea60 BM	102	int i;
	103	int ret;
	104
	105	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER);
	106	if (node < 0) {
	107	debug("%s: Cannot find irq router node\n", __func__);
	108	return -EINVAL;
	109	}
	110
f2b85ab5 SG	111	/* TODO([email protected]): Drop this when PIRQ is a driver */
	112	parent = fdt_parent_offset(blob, node);
	113	if (parent < 0)
	114	return -EINVAL;
	115	ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
9c7dea60 BM	116	"reg", &addr);
	117	if (ret)
	118	return ret;
	119
	120	/* extract the bdf from fdt_pci_addr */
	121	irq_router.bdf = addr.phys_hi & 0xffff00;
	122
	123	ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
	124	if (!ret) {
	125	irq_router.config = PIRQ_VIA_PCI;
	126	} else {
	127	ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
	128	if (!ret)
	129	irq_router.config = PIRQ_VIA_IBASE;
	130	else
	131	return -EINVAL;
	132	}
	133
9e3ff9c2 SG	134	ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
9e3ff9c2 SG	135	if (ret == -1)
9c7dea60	136	return ret;
9e3ff9c2	137	irq_router.link_base = ret;
9c7dea60 BM	138
	139	irq_router.irq_mask = fdtdec_get_int(blob, node,
	140	"intel,pirq-mask", PIRQ_BITMAP);
	141
	142	if (irq_router.config == PIRQ_VIA_IBASE) {
	143	int ibase_off;
	144
	145	ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
	146	if (!ibase_off)
	147	return -EINVAL;
	148
	149	/*
	150	* Here we assume that the IBASE register has already been
	151	* properly configured by U-Boot before.
	152	*
	153	* By 'valid' we mean:
	154	* 1) a valid memory space carved within system memory space
	155	* assigned to IBASE register block.
	156	* 2) memory range decoding is enabled.
	157	* Hence we don't do any santify test here.
	158	*/
	159	irq_router.ibase = x86_pci_read_config32(irq_router.bdf,
	160	ibase_off);
	161	irq_router.ibase &= ~0xf;
	162	}
	163
	164	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
9e3ff9c2	165	if (!cell \|\| len % sizeof(struct pirq_routing))
9c7dea60	166	return -EINVAL;
9e3ff9c2	167	count = len / sizeof(struct pirq_routing);
9c7dea60	168
9e3ff9c2	169	rt = calloc(1, sizeof(struct irq_routing_table));
9c7dea60 BM	170	if (!rt)
9c7dea60 BM	171	return -ENOMEM;
9c7dea60 BM	172
	173	/* Populate the PIRQ table fields */
	174	rt->signature = PIRQ_SIGNATURE;
	175	rt->version = PIRQ_VERSION;
9c235436	176	rt->rtr_bus = PCI_BUS(irq_router.bdf);
9c7dea60 BM	177	rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) \|
	178	PCI_FUNC(irq_router.bdf);
	179	rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
	180	rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
	181
df81749d	182	slot_base = rt->slots;
9c7dea60 BM	183
9c7dea60 BM	184	/* Now fill in the irq_info entries in the PIRQ table */
9e3ff9c2 SG	185	for (i = 0; i < count;
9e3ff9c2 SG	186	i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
9c7dea60 BM	187	struct pirq_routing pr;
	188
	189	pr.bdf = fdt_addr_to_cpu(cell[0]);
	190	pr.pin = fdt_addr_to_cpu(cell[1]);
	191	pr.pirq = fdt_addr_to_cpu(cell[2]);
	192
	193	debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
	194	i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
	195	PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
	196	'A' + pr.pirq);
df81749d BM	197
	198	slot = check_dup_entry(slot_base, irq_entries,
	199	PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
	200	if (slot) {
	201	debug("found entry for bus %d device %d, ",
	202	PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
	203
	204	if (slot->irq[pr.pin - 1].link) {
	205	debug("skipping\n");
	206
	207	/*
	208	* Sanity test on the routed PIRQ pin
	209	*
	210	* If they don't match, show a warning to tell
	211	* there might be something wrong with the PIRQ
	212	* routing information in the device tree.
	213	*/
	214	if (slot->irq[pr.pin - 1].link !=
	215	LINK_N2V(pr.pirq, irq_router.link_base))
	216	debug("WARNING: Inconsistent PIRQ routing information\n");
df81749d BM	217	continue;
df81749d BM	218	}
9e3ff9c2 SG	219	} else {
9e3ff9c2 SG	220	slot = slot_base + irq_entries++;
df81749d	221	}
9e3ff9c2 SG	222	debug("writing INT%c\n", 'A' + pr.pin - 1);
	223	fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin,
	224	pr.pirq);
9c7dea60 BM	225	}
	226
	227	rt->size = irq_entries * sizeof(struct irq_info) + 32;
	228
	229	pirq_routing_table = rt;
	230
	231	return 0;
	232	}
	233
e76187a3	234	int irq_router_probe(struct udevice *dev)
9c7dea60	235	{
7e4be120 SG	236	int ret;
7e4be120 SG	237
9c7dea60 BM	238	cpu_irq_init();
9c7dea60 BM	239
7e4be120 SG	240	ret = create_pirq_routing_table();
7e4be120 SG	241	if (ret) {
9c7dea60	242	debug("Failed to create pirq routing table\n");
7e4be120	243	return ret;
9c7dea60	244	}
7e4be120 SG	245	/* Route PIRQ */
	246	pirq_route_irqs(pirq_routing_table->slots,
	247	get_irq_slot_count(pirq_routing_table));
	248
	249	return 0;
9c7dea60 BM	250	}
	251
	252	u32 write_pirq_routing_table(u32 addr)
	253	{
67b24970 BM	254	if (!pirq_routing_table)
	255	return addr;
	256
9c7dea60 BM	257	return copy_pirq_routing_table(addr, pirq_routing_table);
9c7dea60 BM	258	}
e76187a3 SG	259
	260	static const struct udevice_id irq_router_ids[] = {
	261	{ .compatible = "intel,irq-router" },
	262	{ }
	263	};
	264
	265	U_BOOT_DRIVER(irq_router_drv) = {
	266	.name = "intel_irq",
	267	.id = UCLASS_IRQ,
	268	.of_match = irq_router_ids,
	269	.probe = irq_router_probe,
	270	};
	271
	272	UCLASS_DRIVER(irq) = {
	273	.id = UCLASS_IRQ,
	274	.name = "irq",
	275	};