[J-u-boot.git] / board / esd / plu405 / plu405.c

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>


#if 0
#define FPGA_DEBUG
#endif

extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);

/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


/*
 * include common auto-update code (for esd boards)
 */
#include "../common/auto_update.h"

au_image_t au_image[] = {
	{"plu405/preinst.img", 0, -1, AU_SCRIPT},
	{"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
	{"plu405/pImage_$(bd_type)", 0x00000000, 0x00100000, AU_NAND},
	{"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
	{"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
	{"plu405/postinst.img", 0, 0, AU_SCRIPT},
};

int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));


/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);


int board_early_init_f (void)
{
	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
	mtebc (epcr, 0xa8400000); /* ebc always driven */

	return 0;
}


int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}


int misc_init_r (void)
{
	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;

	dst = malloc(CFG_FPGA_MAX_SIZE);
	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf ("GUNZIP ERROR - must RESET board to recover\n");
		do_reset (NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=20; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc ('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc ('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */

	/*
	 * Reset external DUARTs
	 */
	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
	udelay(10); /* wait 10us */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
	udelay(1000); /* wait 1ms */

	/*
	 * Set NAND-FLASH GPIO signals to default
	 */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;

	return (0);
}


/*
 * Check Board Identity:
 */
int checkboard (void)
{
	unsigned char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming PLU405");
	} else {
		puts(str);
	}

	putc ('\n');

	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();

	return 0;
}


long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}


int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}


#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
	volatile unsigned short *fpga_mode =
		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);

	/*
	 * Assert or deassert CompactFlash Reset Pin
	 */
	if (on) {		/* assert RESET */
		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
	} else {		/* release RESET */
		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
	}
}
#endif /* CONFIG_IDE_RESET */


#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

void nand_init(void)
{
	nand_probe(CFG_NAND_BASE);
	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
		print_size(nand_dev_desc[0].totlen, "\n");
	}
}
#endif


#ifdef CONFIG_AUTO_UPDATE_SHOW
void board_auto_update_show(int au_active)
{
	if (au_active) {
		printf("\n Dies ist die board-funktion: Updating!!!\n");
	} else {
		printf("\n Dies ist die board-funktion: Updating done!!!\n");
	}
}
#endif
Commit	Line	Data
b318262a SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, [email protected]
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
	27	#include <malloc.h>
	28
b318262a SR	29
	30	#if 0
	31	#define FPGA_DEBUG
	32	#endif
	33
	34	extern int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[]);
12537cc5	35	extern void lxt971_no_sleep(void);
b318262a SR	36
	37	/* fpga configuration data - gzip compressed and generated by bin2c */
	38	const unsigned char fpgadata[] =
	39	{
	40	#include "fpgadata.c"
	41	};
	42
	43	/*
	44	* include common fpga code (for esd boards)
	45	*/
	46	#include "../common/fpga.c"
	47
	48
12537cc5 SR	49	/*
	50	* include common auto-update code (for esd boards)
	51	*/
	52	#include "../common/auto_update.h"
	53
	54	au_image_t au_image[] = {
	55	{"plu405/preinst.img", 0, -1, AU_SCRIPT},
	56	{"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
	57	{"plu405/pImage_$(bd_type)", 0x00000000, 0x00100000, AU_NAND},
	58	{"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
	59	{"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
	60	{"plu405/postinst.img", 0, 0, AU_SCRIPT},
	61	};
	62
	63	int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
	64
	65
b318262a	66	/* Prototypes */
eedcd078	67	int gunzip(void , int, unsigned char , unsigned long *);
b318262a SR	68
b318262a SR	69
c837dcb1	70	int board_early_init_f (void)
b318262a SR	71	{
	72	/*
	73	* IRQ 0-15 405GP internally generated; active high; level sensitive
	74	* IRQ 16 405GP internally generated; active low; level sensitive
	75	* IRQ 17-24 RESERVED
	76	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	77	* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	78	* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	79	* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	80	* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	81	* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	82	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	83	*/
	84	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	85	mtdcr(uicer, 0x00000000); /* disable all ints */
	86	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
	87	mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
	88	mtdcr(uictr, 0x10000000); /* set int trigger levels */
	89	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	90	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	91
	92	/*
	93	* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	94	*/
	95	mtebc (epcr, 0xa8400000); /* ebc always driven */
	96
	97	return 0;
	98	}
	99
	100
b318262a SR	101	int misc_init_f (void)
	102	{
	103	return 0; /* dummy implementation */
	104	}
	105
	106
	107	int misc_init_r (void)
	108	{
	109	volatile unsigned char duart0_mcr = (unsigned char )((ulong)DUART0_BA + 4);
	110	volatile unsigned char duart1_mcr = (unsigned char )((ulong)DUART1_BA + 4);
	111	unsigned char *dst;
	112	ulong len = sizeof(fpgadata);
	113	int status;
	114	int index;
	115	int i;
	116
b318262a	117	dst = malloc(CFG_FPGA_MAX_SIZE);
eedcd078	118	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
b318262a SR	119	printf ("GUNZIP ERROR - must RESET board to recover\n");
	120	do_reset (NULL, 0, 0, NULL);
	121	}
	122
	123	status = fpga_boot(dst, len);
	124	if (status != 0) {
	125	printf("\nFPGA: Booting failed ");
	126	switch (status) {
	127	case ERROR_FPGA_PRG_INIT_LOW:
	128	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	129	break;
	130	case ERROR_FPGA_PRG_INIT_HIGH:
	131	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	132	break;
	133	case ERROR_FPGA_PRG_DONE:
	134	printf("(Timeout: DONE not high after programming FPGA)\n ");
	135	break;
	136	}
	137
	138	/* display infos on fpgaimage */
	139	index = 15;
	140	for (i=0; i<4; i++) {
	141	len = dst[index];
	142	printf("FPGA: %s\n", &(dst[index+1]));
	143	index += len+3;
	144	}
	145	putc ('\n');
	146	/* delayed reboot */
	147	for (i=20; i>0; i--) {
	148	printf("Rebooting in %2d seconds \r",i);
	149	for (index=0;index<1000;index++)
	150	udelay(1000);
	151	}
	152	putc ('\n');
	153	do_reset(NULL, 0, 0, NULL);
	154	}
	155
	156	puts("FPGA: ");
	157
	158	/* display infos on fpgaimage */
	159	index = 15;
	160	for (i=0; i<4; i++) {
	161	len = dst[index];
	162	printf("%s ", &(dst[index+1]));
	163	index += len+3;
	164	}
	165	putc ('\n');
	166
	167	free(dst);
	168
	169	/*
	170	* Reset FPGA via FPGA_DATA pin
	171	*/
	172	SET_FPGA(FPGA_PRG \| FPGA_CLK);
	173	udelay(1000); /* wait 1ms */
	174	SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
	175	udelay(1000); /* wait 1ms */
	176
	177	/*
	178	* Reset external DUARTs
	179	*/
	180	out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_DUART_RST); /* set reset to high */
	181	udelay(10); /* wait 10us */
	182	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
183	udelay(1000); /* wait 1ms */
184
185	/*
186	* Set NAND-FLASH GPIO signals to default
187	*/
188	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE \| CFG_NAND_ALE));
189	out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_NAND_CE);
190
191	/*
192	* Enable interrupts in exar duart mcr[3]
193	*/
194	*duart0_mcr = 0x08;
195	*duart1_mcr = 0x08;
b318262a SR	196
	197	return (0);
	198	}
	199
	200
	201	/*
	202	* Check Board Identity:
	203	*/
b318262a SR	204	int checkboard (void)
	205	{
	206	unsigned char str[64];
	207	int i = getenv_r ("serial#", str, sizeof(str));
	208
	209	puts ("Board: ");
	210
	211	if (i == -1) {
	212	puts ("### No HW ID - assuming PLU405");
	213	} else {
	214	puts(str);
	215	}
	216
	217	putc ('\n');
	218
12537cc5 SR	219	/*
	220	* Disable sleep mode in LXT971
	221	*/
	222	lxt971_no_sleep();
	223
b318262a SR	224	return 0;
	225	}
	226
b318262a SR	227
	228	long int initdram (int board_type)
	229	{
	230	unsigned long val;
	231
	232	mtdcr(memcfga, mem_mb0cf);
	233	val = mfdcr(memcfgd);
	234
	235	#if 0
	236	printf("\nmb0cf=%x\n", val); /* test-only */
	237	printf("strap=%x\n", mfdcr(strap)); /* test-only */
	238	#endif
	239
	240	return (410241024 << ((val & 0x000e0000) >> 17));
	241	}
	242
b318262a SR	243
	244	int testdram (void)
	245	{
	246	/* TODO: XXX XXX XXX */
	247	printf ("test: 16 MB - ok\n");
	248
	249	return (0);
	250	}
	251
b318262a SR	252
	253	#ifdef CONFIG_IDE_RESET
	254	void ide_set_reset(int on)
	255	{
	256	volatile unsigned short *fpga_mode =
	257	(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
	258
	259	/*
	260	* Assert or deassert CompactFlash Reset Pin
	261	*/
	262	if (on) { /* assert RESET */
	263	*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
	264	} else { /* release RESET */
	265	*fpga_mode \|= CFG_FPGA_CTRL_CF_RESET;
	266	}
	267	}
	268	#endif /* CONFIG_IDE_RESET */
	269
	270
	271	#if (CONFIG_COMMANDS & CFG_CMD_NAND)
	272	#include <linux/mtd/nand.h>
	273	extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
	274
	275	void nand_init(void)
	276	{
	277	nand_probe(CFG_NAND_BASE);
	278	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
	279	print_size(nand_dev_desc[0].totlen, "\n");
	280	}
	281	}
	282	#endif
12537cc5 SR	283
	284
	285	#ifdef CONFIG_AUTO_UPDATE_SHOW
	286	void board_auto_update_show(int au_active)
	287	{
	288	if (au_active) {
	289	printf("\n Dies ist die board-funktion: Updating!!!\n");
	290	} else {
	291	printf("\n Dies ist die board-funktion: Updating done!!!\n");
	292	}
	293	}
	294	#endif