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Commit | Line | Data |
---|---|---|
dd84058d | 1 | CONFIG_PPC=y |
278b90ce | 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 |
9802154a | 3 | CONFIG_SYS_MALLOC_LEN=0x80000 |
a09fea1d TR |
4 | CONFIG_ENV_SIZE=0x4000 |
5 | CONFIG_ENV_SECT_SIZE=0x10000 | |
20ecfbe9 | 6 | CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb" |
2bba7807 | 7 | CONFIG_SYS_CLK_FREQ=66666667 |
d46e86d2 | 8 | CONFIG_ENV_ADDR=0xFE080000 |
7856cd5a | 9 | # CONFIG_SYS_PCI_64BIT is not set |
dd84058d | 10 | CONFIG_MPC83xx=y |
93de2530 | 11 | CONFIG_HIGH_BATS=y |
dd84058d | 12 | CONFIG_TARGET_MPC837XERDB=y |
21c1502a MS |
13 | CONFIG_DDR_MC_CLOCK_MODE_1_1=y |
14 | CONFIG_SYSTEM_PLL_FACTOR_5_1=y | |
15 | CONFIG_CORE_PLL_RATIO_2_1=y | |
16 | CONFIG_PCI_HOST_MODE_ENABLE=y | |
17 | CONFIG_PCI_INT_ARBITER1_ENABLE=y | |
18 | CONFIG_BOOT_MEMORY_SPACE_LOW=y | |
19 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y | |
20 | CONFIG_TSEC1_MODE_RGMII=y | |
21 | CONFIG_TSEC2_MODE_RGMII=y | |
22 | CONFIG_LDP_PIN_MUX_STATE_0=y | |
30915ab9 MS |
23 | CONFIG_BAT0=y |
24 | CONFIG_BAT0_NAME="SDRAM_LOWER" | |
25 | CONFIG_BAT0_BASE=0x00000000 | |
26 | CONFIG_BAT0_LENGTH_256_MBYTES=y | |
27 | CONFIG_BAT0_ACCESS_RW=y | |
28 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y | |
29 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y | |
30 | CONFIG_BAT0_USER_MODE_VALID=y | |
31 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y | |
32 | CONFIG_BAT1=y | |
33 | CONFIG_BAT1_NAME="SDRAM_UPPER" | |
34 | CONFIG_BAT1_BASE=0x10000000 | |
35 | CONFIG_BAT1_LENGTH_256_MBYTES=y | |
36 | CONFIG_BAT1_ACCESS_RW=y | |
37 | CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y | |
38 | CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y | |
39 | CONFIG_BAT1_USER_MODE_VALID=y | |
40 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y | |
41 | CONFIG_BAT2=y | |
42 | CONFIG_BAT2_NAME="IMMR" | |
43 | CONFIG_BAT2_BASE=0xE0000000 | |
44 | CONFIG_BAT2_LENGTH_8_MBYTES=y | |
45 | CONFIG_BAT2_ACCESS_RW=y | |
46 | CONFIG_BAT2_ICACHE_INHIBITED=y | |
47 | CONFIG_BAT2_ICACHE_GUARDED=y | |
48 | CONFIG_BAT2_DCACHE_INHIBITED=y | |
49 | CONFIG_BAT2_DCACHE_GUARDED=y | |
50 | CONFIG_BAT2_USER_MODE_VALID=y | |
51 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y | |
52 | CONFIG_BAT3=y | |
53 | CONFIG_BAT3_NAME="L2_SWITCH" | |
54 | CONFIG_BAT3_BASE=0xF0000000 | |
55 | CONFIG_BAT3_ACCESS_RW=y | |
56 | CONFIG_BAT3_ICACHE_INHIBITED=y | |
57 | CONFIG_BAT3_ICACHE_GUARDED=y | |
58 | CONFIG_BAT3_DCACHE_INHIBITED=y | |
59 | CONFIG_BAT3_DCACHE_GUARDED=y | |
60 | CONFIG_BAT3_USER_MODE_VALID=y | |
61 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y | |
62 | CONFIG_BAT4=y | |
63 | CONFIG_BAT4_NAME="FLASH" | |
64 | CONFIG_BAT4_BASE=0xFE000000 | |
65 | CONFIG_BAT4_LENGTH_32_MBYTES=y | |
66 | CONFIG_BAT4_ACCESS_RW=y | |
67 | CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y | |
68 | CONFIG_BAT4_DCACHE_INHIBITED=y | |
69 | CONFIG_BAT4_DCACHE_GUARDED=y | |
70 | CONFIG_BAT4_USER_MODE_VALID=y | |
71 | CONFIG_BAT4_SUPERVISOR_MODE_VALID=y | |
72 | CONFIG_BAT5=y | |
73 | CONFIG_BAT5_NAME="STACH_IN_DCACHE" | |
74 | CONFIG_BAT5_BASE=0xE6000000 | |
75 | CONFIG_BAT5_ACCESS_RW=y | |
76 | CONFIG_BAT5_USER_MODE_VALID=y | |
77 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y | |
78 | CONFIG_BAT6=y | |
79 | CONFIG_BAT6_NAME="PCI_MEM" | |
80 | CONFIG_BAT6_BASE=0x80000000 | |
81 | CONFIG_BAT6_LENGTH_256_MBYTES=y | |
82 | CONFIG_BAT6_ACCESS_RW=y | |
83 | CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y | |
84 | CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y | |
85 | CONFIG_BAT6_USER_MODE_VALID=y | |
86 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y | |
87 | CONFIG_BAT7=y | |
88 | CONFIG_BAT7_NAME="PCI_MMIO" | |
89 | CONFIG_BAT7_BASE=0x90000000 | |
90 | CONFIG_BAT7_LENGTH_256_MBYTES=y | |
91 | CONFIG_BAT7_ACCESS_RW=y | |
92 | CONFIG_BAT7_ICACHE_INHIBITED=y | |
93 | CONFIG_BAT7_ICACHE_GUARDED=y | |
94 | CONFIG_BAT7_DCACHE_INHIBITED=y | |
95 | CONFIG_BAT7_DCACHE_GUARDED=y | |
96 | CONFIG_BAT7_USER_MODE_VALID=y | |
97 | CONFIG_BAT7_SUPERVISOR_MODE_VALID=y | |
9c5df7a2 MS |
98 | CONFIG_LBLAW0=y |
99 | CONFIG_LBLAW0_BASE=0xFE000000 | |
100 | CONFIG_LBLAW0_NAME="FLASH" | |
101 | CONFIG_LBLAW0_LENGTH_8_MBYTES=y | |
102 | CONFIG_LBLAW1=y | |
103 | CONFIG_LBLAW1_BASE=0xE0600000 | |
104 | CONFIG_LBLAW1_NAME="NAND" | |
105 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y | |
106 | CONFIG_LBLAW2=y | |
107 | CONFIG_LBLAW2_BASE=0xF0000000 | |
108 | CONFIG_LBLAW2_NAME="VSC7385" | |
109 | CONFIG_LBLAW2_LENGTH_128_KBYTES=y | |
344a0e43 TR |
110 | CONFIG_ELBC_BR0_OR0=y |
111 | CONFIG_BR0_OR0_NAME="FLASH" | |
112 | CONFIG_BR0_OR0_BASE=0xFE000000 | |
113 | CONFIG_BR0_PORTSIZE_16BIT=y | |
114 | CONFIG_OR0_AM_8_MBYTES=y | |
115 | CONFIG_OR0_SCY_9=y | |
116 | CONFIG_OR0_XACS_EXTENDED=y | |
117 | CONFIG_OR0_EHTR_1_CYCLE=y | |
118 | CONFIG_OR0_EAD_EXTRA=y | |
119 | CONFIG_ELBC_BR1_OR1=y | |
120 | CONFIG_BR1_OR1_NAME="NAND" | |
121 | CONFIG_BR1_OR1_BASE=0xE0600000 | |
122 | CONFIG_BR1_ERRORCHECKING_BOTH=y | |
123 | CONFIG_BR1_MACHINE_FCM=y | |
124 | CONFIG_OR1_SCY_1=y | |
125 | CONFIG_OR1_CSCT_8_CYCLE=y | |
126 | CONFIG_OR1_CST_ONE_CLOCK=y | |
127 | CONFIG_OR1_CHT_TWO_CLOCK=y | |
128 | CONFIG_OR1_TRLX_RELAXED=y | |
129 | CONFIG_OR1_EHTR_8_CYCLE=y | |
130 | CONFIG_ELBC_BR2_OR2=y | |
131 | CONFIG_BR2_OR2_NAME="VSC7385" | |
132 | CONFIG_BR2_OR2_BASE=0xF0000000 | |
133 | CONFIG_OR2_AM_128_KBYTES=y | |
134 | CONFIG_OR2_SCY_15=y | |
135 | CONFIG_OR2_CSNT_EARLIER=y | |
136 | CONFIG_OR2_XACS_EXTENDED=y | |
137 | CONFIG_OR2_SETA_EXTERNAL=y | |
138 | CONFIG_OR2_TRLX_RELAXED=y | |
139 | CONFIG_OR2_EHTR_8_CYCLE=y | |
140 | CONFIG_OR2_EAD_EXTRA=y | |
be5abb0a MS |
141 | CONFIG_HID0_FINAL_EMCP=y |
142 | CONFIG_HID0_FINAL_ICE=y | |
143 | CONFIG_HID2_HBE=y | |
73df96a3 MS |
144 | CONFIG_ACR_PIPE_DEP_4=y |
145 | CONFIG_ACR_RPTCNT_4=y | |
e35012e8 | 146 | CONFIG_SPCR_TSECEP_3=y |
344a0e43 TR |
147 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y |
148 | CONFIG_LCRR_CLKDIV_8=y | |
73223f0e SG |
149 | CONFIG_OF_BOARD_SETUP=y |
150 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
bb597c0e | 151 | CONFIG_BOOTDELAY=6 |
c8be85f3 | 152 | CONFIG_BOARD_LATE_INIT=y |
8ccf98b1 | 153 | CONFIG_MISC_INIT_R=y |
c8be85f3 | 154 | CONFIG_PCI_INIT_R=y |
adad96e6 | 155 | CONFIG_HUSH_PARSER=y |
d0ee7f29 | 156 | CONFIG_SYS_PBSIZE=276 |
ad12dc18 | 157 | CONFIG_CMD_IMLS=y |
78d1e1d0 | 158 | CONFIG_CMD_I2C=y |
88663126 | 159 | CONFIG_CMD_MMC=y |
6500ec7a | 160 | CONFIG_CMD_PCI=y |
88663126 TR |
161 | CONFIG_CMD_SATA=y |
162 | CONFIG_CMD_USB=y | |
ef0f2f57 | 163 | # CONFIG_CMD_SETEXPR is not set |
a542e430 | 164 | CONFIG_BOOTP_BOOTFILESIZE=y |
89cb2b5f | 165 | CONFIG_CMD_MII=y |
78d1e1d0 | 166 | CONFIG_CMD_PING=y |
c9032ce1 | 167 | CONFIG_CMD_DATE=y |
89cb2b5f TR |
168 | CONFIG_CMD_EXT2=y |
169 | CONFIG_CMD_FAT=y | |
a2c48cb7 | 170 | CONFIG_OF_CONTROL=y |
20ecfbe9 | 171 | CONFIG_ENV_OVERWRITE=y |
fdfb17b1 TR |
172 | CONFIG_USE_BOOTFILE=y |
173 | CONFIG_BOOTFILE="uImage" | |
0e14cdfa TR |
174 | CONFIG_USE_ETHPRIME=y |
175 | CONFIG_ETHPRIME="TSEC0" | |
a2c48cb7 | 176 | CONFIG_DM=y |
9920d151 | 177 | CONFIG_FSL_SATA=y |
edca8cf7 | 178 | CONFIG_SYS_SATA_MAX_DEVICE=2 |
c7fad78e TR |
179 | CONFIG_SYS_BR0_PRELIM_BOOL=y |
180 | CONFIG_SYS_BR0_PRELIM=0xFE001001 | |
181 | CONFIG_SYS_OR0_PRELIM=0xFF800193 | |
182 | CONFIG_SYS_BR1_PRELIM_BOOL=y | |
183 | CONFIG_SYS_BR1_PRELIM=0xE0600C21 | |
184 | CONFIG_SYS_OR1_PRELIM=0xFFFF8396 | |
185 | CONFIG_SYS_BR2_PRELIM_BOOL=y | |
186 | CONFIG_SYS_BR2_PRELIM=0xF0000801 | |
187 | CONFIG_SYS_OR2_PRELIM=0xFFFE09FF | |
55dabcc8 | 188 | CONFIG_SYS_I2C_LEGACY=y |
6d5d0c95 TR |
189 | CONFIG_SYS_I2C_FSL=y |
190 | CONFIG_SYS_FSL_I2C_OFFSET=0x3000 | |
191 | CONFIG_SYS_I2C_SLAVE=0x7F | |
192 | CONFIG_SYS_I2C_SPEED=400000 | |
07dea2e7 | 193 | CONFIG_FSL_ESDHC=y |
e856bdcf | 194 | CONFIG_MTD_NOR_FLASH=y |
2fe88d45 AF |
195 | CONFIG_FLASH_CFI_DRIVER=y |
196 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y | |
b72713dc | 197 | CONFIG_SYS_FLASH_EMPTY_INFO=y |
2fe88d45 AF |
198 | CONFIG_SYS_FLASH_PROTECTION=y |
199 | CONFIG_SYS_FLASH_CFI=y | |
1db251bd | 200 | CONFIG_SYS_MAX_FLASH_SECT=256 |
c8be85f3 SA |
201 | CONFIG_DM_MDIO=y |
202 | CONFIG_DM_ETH_PHY=y | |
203 | CONFIG_RGMII=y | |
204 | CONFIG_MII=y | |
17151052 | 205 | CONFIG_TSEC_ENET=y |
9e39003e | 206 | CONFIG_SYS_NS16550=y |
645176d1 | 207 | CONFIG_USB=y |
64d6ac5b | 208 | CONFIG_USB_EHCI_HCD=y |
f76750d1 | 209 | CONFIG_USB_EHCI_FSL=y |